JPS59144947A - Data comparator - Google Patents

Abstract

PURPOSE:To decide the size of input data simply by applying the input data to one terminal of a comparator and applying the output of a counter to the other terminal. CONSTITUTION:Load pulses 3, 4 are applied to an up-counter 9 and a down- counter 11 respectively to step-advance the counters 9, 11. Input data are applied to a register 10. Comparators 12, 13 compare the contents of the counters 9, 11 and the register 10. An allowable deviation setting part 17 decides a digit to actuate the counters while considering the relation between data length and an allowable deviation value. When 25% allowable deviation is applied to 10-bit of data length e.g., the setting part 17 sets up 15 digits expressed by 4-bit from 2<5>- bit to 2<8>-bit, the value of 25%, as the number of counted pulses. Consequently, detection of coincidence can be executed for a short time.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] When comparing two numerical data, the present invention fixes one data and counts up and down the other data within an allowable deviation. and determining whether said one data is between said counted-down value and said counted-down value.

[Prior art]

A method of performing calculation processing using a computer to compare numerical data is a well-known technique. With this method, the data comparison time may be long depending on the calculation speed of the computer and the number of steps in the program.

There are also methods of using registers, amplifier counters, and down counters to compare numerical data. This is a method as shown in Japanese Patent Application No. 57-53873, in which one data is fixed, the other data is counted down and counted down within the allowable deviation, and the fixed data is counted down. It checks whether the value is between the value counted up and the value counted down, and determines whether the two data match.

A schematic configuration of a conventional example using this method is shown in FIG. In this figure, when data A is applied to terminal 1, the data A is applied to up counter 9 and down counter 1.
1 by load pulse 3. Further, data C applied to terminal 2 is taken into register 10 by load pulse 4. Thereafter, when the comparison start signal is applied to the terminal 6, the pulse output from the clock generator 5 is passed through the AND gate 7 to the tolerance setting section 8.
Up counter 9 and down counter 9 by the number specified by
It is applied to counter 11, which pulses the clock for counting up and counting down.

As a result, the data A stored in the counter 9 is counted up within the tolerance deviation, and the data 8 stored in the counter 11 is counted down within the tolerance deviation (in this process, the data C stored in the register 1o Comparison circuits 12 and 13 determine whether the data match within the allowable deviation or not, and the result is output as a match signal to the terminal 15 via the OR gate 14.If the respective data match within the allowable deviation, If so, the output signal of the OR gate 14 is applied to the allowable deviation setting unit 8, and the pulse output from the setting unit 8 is stopped.

As described above, it is determined whether data A and data C match, but if the tolerance is large, the data stored in counters 9 and 11 is counted up or down. becomes large, which causes a problem that the data comparison time becomes long.

[Purpose of the invention]

The purpose of the present invention is to
It is an object of the present invention to provide a device that compares data in a short time.

[Summary of the invention]

To achieve the above object, the data comparison device according to the above invention of the type mentioned at the outset furthermore comprises an up counter and a down counter that count up and count down, respectively, depending on the magnitude of the tolerance deviation. The gist is that means is provided for switching the starting digit. In an advantageous sister aspect of the invention, the means for switching the digits from which to start counting up and counting down, respectively, of the amplifier counter and the down counter are located at a higher position when the tolerance deviation is large; If it is smaller, the data is compared by counting at or above the lower digit, and the data is not compared at or above the above digit.

In the present invention, when comparing data consisting of a certain bit length, as shown in FIG. It is determined whether or not data consisting of bit length Z match within a permissible deviation. In this method, when the tolerance is small, the effective digit of the tolerance is adjusted to the least significant digit of the data, and the data is compared from the least significant digit within the effective tolerance indicated by the a bit to determine whether or not they match. do.

In addition, if the allowable deviation is large, set the effective digit of the allowable deviation to the upper digit side of the data, and compare the data within the effective allowable deviation indicated by the a bit on the upper side from this set value to determine whether or not they match. judge. When the tolerance becomes large, the effective digits of the tolerance are set to the upper digits of the data, so a bit n (this is called a residual bit) that is not processed at all is placed between the least significant digit of the data and the position where the effective digit of the tolerance is set. ) exists.

This residual bit becomes the error of the allowable deviation.

That is, the allowable deviation is (true allowable deviation) ±2n-1 digits (where n>1). However, this error is sufficiently smaller than the true allowable deviation, so there is no problem.

As described above, if the setting range of the number of effective digits of the allowable deviation is changed according to the allowable deviation and data is always compared with the same number of effective digits of allowable deviation, the data comparison time is always short. The specific details of this will be explained below using figures.

[Actual sister example of invention]

FIG. 3 is a block diagram showing the configuration of a data comparison device according to one embodiment of the present invention, and reference numbers common to those in FIG. 1 in the figure represent the same parts as in FIG. 1.

As an example, as shown in FIG. 4, the data length is 10 bits, and the respective values are 704 digits and 512 digits. When these values correspond to a data length of 10 bits, they are 69% and 5%, respectively.
The value is 0%.

Therefore, the allowable deviation is set to 25 inches, and whether or not the above data match within this range is determined using FIGS. 3 and 5.

In FIG. 3, the allowable deviation setting section 17 has an allowable deviation of 25
%, so in consideration of the resolution of data comparison, the digit switching signal 16 is applied to the amplifier counter 9 and the down counter 11 to start counting up or down from 25 bits of the up counter and down counter. Output to. Accordingly, the setting section 17 sets 15 digits tt - the number of count pulses for counting up or counting down, expressed by 4 bits from 25 bits to 28 bits, which is the value of 25 bits.

As a result, the output from the pulse generator 5 as shown in FIG.
), when the comparison start signal shown in FIG. 5(b) is applied to the terminal 6, the allowable deviation setting section 17 of the AND gate 7
, a pulse as shown in FIG. 5(C) is obtained. This is because the count up and count down are stopped by a coincidence signal, which will be described later, even though the number of pulses is six here.

By the way, up counter 9. down counter 11
5(d) and (0 load pulse 3,
4, the data A and B applied to terminals 1 and 2 are the fifth
(e), (stored as A and B indicated by ω. Up counter 9 and down counter 11 are
It has the configuration shown in No. 203546, and can count up or down from any arbitrary digit.

Therefore, the pulse shown in FIG. 5(C) is applied from the 26th bit of the up counter 9 and the down counter 11. Therefore, the output of the amplifier/counter is AI, A2, . A3°... On the other hand, the output of the down counter becomes Bl, B2, B3, etc. each time it is counted down, as shown in Figure 5 (ω, Figure 6 (g) to (e)), and it is counted down six times. If so, it matches data C.

As a result, the comparison circuits 12 output mismatch signals, but the comparison circuit 13 outputs a match signal, which is output to the terminal 15 via the OR gate 14. Furthermore, this coincidence signal is also input to the allowable deviation setting section 17, thereby preventing further counting up or down.

The allowable deviation setting section 17 has a configuration as shown in FIG.

The arithmetic unit 42 has a function of setting the number of valid digits of the allowable deviation and the count values of the up counter and down counter according to the allowable deviation of the data, and the valid digit setting register 4
4, the effective digit switching signal for the tolerance is counted up/
An up/down count number signal is output to the down register 43. Counter 40 receives pulse 18' from AND gate 7! il: When input, this pulse number is counted. When the number of pulses counted by the counter 40 and the value set in the count up/down register 43 match, the comparator 41 outputs a signal of 1'' to the OR gate 45. As a result, the OR gate 45 is comparator 4
Pulse 1 until a signal from 1 to a 1 p+ is output.
8 is outputted to an up counter 9 and a down counter 11 as a count pulse signal 19. In this way, the amplifier/counter 9 . A count pulse 19 is output to the down counter 11, but
When each data matches within the allowable deviation, a match signal of 1" is output from the OR gate 14 in FIG.
Since the pulse 18 is input to the gate 45, the pulse 18 becomes O from then on.
There is no output from R gate 45. This is the state shown in FIG. 5(C).

The data is compared as described above, but when compared with the conventional data comparison starting from the lowest digit, the difference in data is 192 digits, so June 192, or 3
This results in a data comparison speed difference of twice as much.

As mentioned above, depending on the allowable deviation of the data, the count
By switching the amplifier and the start digit of the countdown and comparing the data, the data can be compared in a short time regardless of the size of the tolerance, which is very effective. Note that in the above example, the lower digits that do not count up or count down match, but if they do not match, that part may be masked so as not to be compared.

In this case, the error in the tolerance is the masked amount, and in the data comparison example, 24 bits or less are masked, so it is 25-11, or 31 digits, which is 3% of the total, so the above In the example, the tolerance is 2
Although it was evaluated as 5±3chi, this is not much different from the true value of the allowable deviation and is not a problem.

Next, an application example of the present invention will be shown.

FIG. 8 is related to data comparison of multiplex control devices, and is intended for duplex control devices. For triple or higher systems, this comparison method for double systems may be combined.

In FIG. 8, control devices 21 and 22 take in signals from the sensor group 20, perform IP/O calculations on them, and output control signals to the actuator 25 via the switch 24. Due to the difference in the integral calculation value,
It is normal for the calculation results and other data to be somewhat different. Therefore, the data comparison device 23 is required to change the allowable deviation according to the comparison data and to compare the data in a short time, and the above-described data comparison device can be applied to this purpose with great effect.

Further, FIG. 9 shows an example in which the present invention is applied to a data transmission system.

Since the data transmission between the transmission device 30.31 and the transmission device 32.33 operates asynchronously, the device 30.31 receives the signal 'ff: from the Senna group 20 and transmits it to the device 32.
．． 33, the device at the same time is 32.33.
The data that has been transmitted is different. Conversely, the data transmitted from the devices 32, 33 to the devices 30, 31 is likewise different.

Therefore, when comparing data between each device, the allowable deviation must be changed significantly.

Therefore, if the data comparison device described above is applied to the data comparison device 23, the effect will be great.

In addition, 24.24M and 24N are switches, and 25M
, 25N are actuators, and 34 is a monitoring device.

〔Effect of the invention〕

As explained above, according to the present invention, since any numerical data can be compared in a short time, it is possible to improve the reliability of the multiplexing system and to achieve the effect of increasing the processing speed of the system.

The present invention is highly effective when applied to, for example, diagnosis of multiplex control systems and multiplex data transmission systems.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional data comparison device, FIG. 2 is a diagram showing the configuration of data input to the data comparison device for explaining the present invention in detail, and FIG. 3 is a block diagram showing the configuration of the data comparison device according to the present invention. A block diagram showing the configuration of the data comparison device, FIG. 4 is a diagram showing the configuration of two data to be compared, and FIG.
) to (h) are charts showing the timing of pulse signals used in the device shown in FIG. 3, and FIG. 6(g)
to (a) and (g) to -) are diagrams showing changes in the outputs of the amplifier counter and down counter, respectively, and FIG. 7 is a block diagram showing the configuration of the tolerance setting section of the device shown in FIG. 3. 8 and 9 are block diagrams illustrating two different applications of the invention. 1... Input terminal of amplifier counter and down counter, 2... Input terminal of register, 3, 4... Load pulse, 5... Clock generator, 6... Comparison start signal terminal , 7...AND gate, 8, 17 river tolerance setting section, 9 river up counter, 1o... register, 11... down counter, 12.13... comparison circuit, 14... OR gate, 15...output terminal,
16... Digit switching signal, 18... AND gate output pulse, 19 River count pulse, 2o... Sensor group, 21.22... Control device, 23... Data comparison device, 24. 24M, 24N...Switch, 25°2
5M, 25N... Actuator, 30, 31° 32
．． 33... Transmission device, 34... Monitoring device, 40...
- Counter, 41... Comparator, 42... Arithmetic device,
43...Count up/down register, 44
...Valid digit setting register, 45...OR gate. Agent Patent Attorney Masami Akimoto Figure 7// /j Fan 3 Figure 1/ Funeral 4-(2) Data c: 1000000000 Figure 5 Funeral Figure 6 (α) A6: [4■ balls 7 times (b) A5 : ro] ■ Le m 7 times' (C) A4-; ■■■ Four bose ■ Old mouth (d) A3
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2] No. 70 Swordsmanship Figure 8 Figure 1 Figure 9 5N Procedural amendment (method) % formula %, Indication of the case Showa 5g 2007 Patent Application No. 77 G7 IJ, Name of invention Data comparison 3, Name of the person making the amendment (510) Hitachi, Ltd., Agent 7, Subject of amendment #J Hoshosho, brief explanation of drawings 8
, Contents of the amendment Attachment Toshi 11, "Figure Z Q) to (B)) and (g> to (C))" on page 11I, lines 2 to 7 of the specification of the present application
"Figure 6 (a) to (b)) and (6) to 0
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Claims (1)

[Claims] 1. Whether or not the register that stores one of the two numerical data, the up counter and down counter that store the other, and the two numerical data coincide within a permissible deviation. and a comparator for determining the value of the amp counter and the down counter, further comprising means for switching the digits at which the amplifier counter and the down counter start counting up and down, respectively, depending on the size of the tolerance. A data comparison device comprising: 2. The means for switching the digits at which to start counting up and counting down, respectively, of the amplifier counter and down counter are located at the upper digits when the tolerance is large, and when the tolerance is small, the digits at or above the lower digits are counted. 2. The data comparison device according to claim 1, wherein the data is compared based on the number of digits specified above, and data beyond the above-mentioned digits are not compared.