JPS62100832A - Arithmetic checking circuit - Google Patents

Abstract

PURPOSE:To obtain an arithmetic checking circuit with low cost by checking the arithmetic result in a cycle N times as much as that of a main arithmetic circuit. CONSTITUTION:The data stored in the input registers 4a and 4b are sent to an arithmetic circuit 2 and calculated by the control signal sent from a control register 7. This arithmetic result is stored in the 1st output register 5. At the same time, the data on a buffer 6a is stored in the 2nd output register 6b and the new data is stored in the buffer 6a. While the arithmetic result of the circuit 2 stored in the register 5 is sent to a checking circuit 3. Then the arithmetic result of a main arithmetic circuit 1 stored in the register 6b is also sent to the circuit via a line 62. The coincidence between both arithmetic results is checked by the circuit 3. Then the coincidence signal of logic '1' is transmitted via a line 31 when the coincidence is obtained between both arithmetic results.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a check circuit for checking calculation data in a data processing device.

[Conventional technology]

Conventionally, this type of arithmetic check circuit has been configured to double the arithmetic circuit and check the arithmetic result. That is, as shown in FIG. 3, the arithmetic check circuit is composed of a main arithmetic circuit 1, a duplicated check arithmetic circuit 2, and a check circuit 3. The same data is input to the main arithmetic circuit 1 and the arithmetic circuit 2, and each arithmetic circuit 1.2 performs an arithmetic operation based on the input data.

The calculation results output from each calculation circuit 1.2 are input to the check circuit 3, and the check circuit 3 checks whether the calculation results match.

In this way, the calculation check circuit is configured to check whether the calculation results of the main calculation circuit 1 and the calculation results of the calculation circuit 2 match, so that the reliability of the calculation data can be improved.

[Problem that the invention seeks to solve]

However, in the conventional arithmetic check circuit, the main arithmetic circuit 1 and the check arithmetic circuit 2 are configured to have the same function. This requires an expensive device, and the check arithmetic circuit 2 itself is expensive. Furthermore, since the respective arithmetic circuits 1 and 2 are required to have the same hardware, there is a drawback that only the check arithmetic circuit 2 cannot be miniaturized.

An object of the present invention is to provide an arithmetic check circuit that can reduce the cost and size of the check arithmetic circuit.

[Means for solving problems]

The arithmetic check circuit of the present invention has a plurality of input registers that store the same data as the input data of the main arithmetic circuit at a period N times (N: an integer) that of the main arithmetic circuit, and inputs the data in each input register. a low-speed arithmetic circuit that performs calculations at a low speed; a first output register that stores the calculation results of this calculation circuit; and a second output register that stores the calculation results of the main calculation circuit at a cycle N times that of the main calculation circuit; It has a check circuit that checks the calculation results stored in the first and second output registers at a cycle N times that of the main calculation circuit.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. 1st
The structure of a preferred embodiment of the present invention is shown in FIG. 2 and FIG. In FIG. 2, the main arithmetic circuit 1 has a line 10
Calculation data is input via line 1.1.02, and line 103
An arithmetic control signal is inputted via. Similarly, the line 101 is also connected to the low-speed check highly integrated circuit (LSI) 10.
．． Calculation data is input through line 102, and calculation control signals are input through line 103. Check LSI
The calculation data input to l0 is stored in a register and used for calculation.

The main arithmetic circuit 1 executes arithmetic operations based on input data, and outputs the arithmetic results to the checking LSI 10 via a line 104. This calculation result is stored in a register in the checking LSI 10 at the same time as the input data and the calculation control signal, and it is checked whether or not it matches the internal calculation result. The result of this check is reported via line 31.

Since the check LSI10 operates at a cycle N times that of the main processing circuit 1, one of the N times of calculations performed by the main processing circuit 1 is
The result of the calculation is checked by the checking LSI 10. A specific configuration of this checking LSI 10 is shown in FIG. The checking LSI 10 includes input registers 4a and 4b in which calculation data is stored, a control register 7 in which calculation control signals are stored, an calculation circuit 2, a first output register 5 in which calculation results are stored, and an external main calculation circuit 1. A buffer 5a that stores the calculation results in the second output register 6b.
, a check circuit 3 that checks whether the contents of the first and second output registers 5.6b match.

Data are input to the checking LS 11.0 via lines 101-104. Of these lines 101-102
Input data input via line 103 is stored in input registers 4a and 4b, respectively, and an arithmetic control signal input via line 103 is stored in control register 7. At the same time, the calculation result of the main calculation circuit 1 is stored in the buffer 6a via the line 104. The data stored in the input registers 4a and 4b are sent to the arithmetic circuit 2 via lines 41 and 42, respectively, and then to the line 71.
The calculation is performed according to a control signal sent from the control register 7 via the control register 7. The result of this calculation is then stored in the first output register 5 via line 21.

At the same time, the data in buffer 6a is transferred via line 61 to the second
new data is stored in the output register 6b, and new data is stored in the buffer 6a. The data of the calculation result of the calculation circuit 2 stored in the first output register 5 is sent to the check circuit 3 via the line 51, and the data is sent to the check circuit 3 via the line 51.
The data of the calculation result by the main calculation circuit 1 stored in the main calculation circuit 1 is sent to the check circuit 3 via the line 62, and the coincidence between the two is checked. If the two calculation results match, a logic 1 match signal is output via the check circuit 3 twisted wire 31, and if they do not match, a logic 0 mismatch signal is output, indicating an error. What happened is reported.

〔Effect of the invention〕

As explained above, according to the present invention, the checking arithmetic circuit can be realized with an inexpensive, low-speed circuit. It becomes possible to use a highly integrated LSI with high speed and low power, and the excellent effect that the check arithmetic circuit can be made smaller can be obtained.

[Brief explanation of drawings]

FIG. 1 is a specific block diagram showing an embodiment of the present invention, FIG. 2 is a general block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional circuit. 1 ・・・・・・・・・・・・・・・・・・Main calculation circuit 2 ・・・・・・・・・・・・・・・・・・Calculation circuit 3
・・・・・・・・・・・・・・・Check circuits 4a, 4b ・・・・Input register 5 ・・・・
・・・・・・・・・・・・・・・First output register 5a
・・・・・・・・・・・・・・・Buffer 6b・
・・・・・・・・・・・・・・・Second output register 7
・・・・・・・・・・・・・・・・・・Control register 1
0 ・・・・・・・・・・・・Check LSI
Agent Patent Attorney Yoshiyuki Iwasa Figure 1

Claims (1)

[Claims] (1) Multiple input registers that store the same data as the input data to the main processing circuit at a cycle N times (N: an integer) that of the main processing circuit, and a low-speed register that stores the data in each input register and performs calculations. an arithmetic circuit, a first output register that stores the arithmetic results of the arithmetic circuit, and a second output register that stores the arithmetic results of the main arithmetic circuit at a cycle N times that of the main arithmetic circuit;
An arithmetic check circuit comprising a check circuit that checks the arithmetic results stored in the first and second output registers at a cycle N times that of the main arithmetic circuit.