JPS6442735A - Arithmetic circuit - Google Patents

Arithmetic circuit

Info

Publication number
JPS6442735A
JPS6442735A JP20052587A JP20052587A JPS6442735A JP S6442735 A JPS6442735 A JP S6442735A JP 20052587 A JP20052587 A JP 20052587A JP 20052587 A JP20052587 A JP 20052587A JP S6442735 A JPS6442735 A JP S6442735A
Authority
JP
Japan
Prior art keywords
value
count
down counter
comparing means
maximum value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20052587A
Other languages
Japanese (ja)
Inventor
Masaaki Nagami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Ten Ltd
Original Assignee
Denso Ten Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Ten Ltd filed Critical Denso Ten Ltd
Priority to JP20052587A priority Critical patent/JPS6442735A/en
Publication of JPS6442735A publication Critical patent/JPS6442735A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the arithmetic speed by controlling a count operation of an up-down counter, and stopping the count operation of the up-down counter by an output from a comparing means, when the count value becomes equal to the maximum value or the minimum value. CONSTITUTION:A count value of an up-down counter 21 is given to a comparing means, and also, to this comparing means, the maximum value being the upper limit value at the time when the counter 21 executes a count operation, and the minimum value being the lower limit value are given from a maximum value register 22, and a minimum value register 23, respectively. The comparing means 24, 25 compare the count value of the up-down counter 21, and the maximum value and the minimum value, respectively, and when the count value has become equal to the maximum value or the minimum value, an output is led out to a control means 28, and the count operation of the up-down counter 21 is stopped. In such a way, an arithmetic processing speed when an input signal such as an acoustic signal, etc., is brought to an arithmetic processing successively as time elapses can be improved.
JP20052587A 1987-08-10 1987-08-10 Arithmetic circuit Pending JPS6442735A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20052587A JPS6442735A (en) 1987-08-10 1987-08-10 Arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20052587A JPS6442735A (en) 1987-08-10 1987-08-10 Arithmetic circuit

Publications (1)

Publication Number Publication Date
JPS6442735A true JPS6442735A (en) 1989-02-15

Family

ID=16425759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20052587A Pending JPS6442735A (en) 1987-08-10 1987-08-10 Arithmetic circuit

Country Status (1)

Country Link
JP (1) JPS6442735A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5127036A (en) * 1974-08-30 1976-03-06 Yokogawa Electric Works Ltd DEIJITARU MARUCHIREBERUKON PAREETA
JPS59144947A (en) * 1983-02-07 1984-08-20 Hitachi Ltd Data comparator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5127036A (en) * 1974-08-30 1976-03-06 Yokogawa Electric Works Ltd DEIJITARU MARUCHIREBERUKON PAREETA
JPS59144947A (en) * 1983-02-07 1984-08-20 Hitachi Ltd Data comparator

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