JPH0731544B2 - Computational congestion monitoring device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a calculation traffic congestion monitoring device, for example, a programmable controller in sequence control.

[Conventional technology]

In the conventional sequence control, the operation congestion monitoring of the programmable controller is performed by the device having the configuration shown in FIG. In the figure, (1) is a counter circuit, (2)
Is the clock that becomes the count input of the counter circuit (1),
Reference numeral (3) is a CPU for performing a sequence operation, and the counter circuit (1) is reset each time the sequence operation is executed.

The calculation congestion monitoring of the conventional programmable controller is performed by the device configured as described above. When the sequence control operation starts, the CPU (3)
As long as the sequence calculation is performed smoothly, the counter circuit (1) is reset by a command from the CPU (3) every time the sequence calculation is completed, and the next sequence calculation is started.

Next, if the sequence operation by the CPU (3) is not smoothly performed and there is no reset signal from the CPU (3) before the counter circuit (1) counts up by the clock (2), the counter circuit (1 ), A traffic congestion signal is issued, and a predetermined alarm or display unit is activated.

[Problems to be solved by the invention]

In the conventional device for monitoring congestion of the pluggable controller as described above, for example, the CPU (3) erroneously writes / reads (WR) even if the sequence operation is not smoothly performed (CPU ( The problem that the calculation astringent signal is not output when the reset signal is constantly output to the counter circuit (2) due to the abnormal state of 3) and the constant of the counter circuit (2) is determined. There was a problem that the traffic congestion monitoring time was constant.

The present invention has been made to solve such a problem, and even when the CPU (3) is in an abnormal state, a traffic congestion signal is issued and traffic congestion such that the traffic congestion monitoring time can be programmable is changed. The purpose is to provide a monitoring method.

[Means for solving problems]

The operation congestion monitoring apparatus according to the present invention performs sequence control, mutually searches for abnormalities of the other party, and outputs the first and second abnormality detection signals when detecting the other party's abnormality, respectively. Each time a sequence operation is completed, the CPU and the reset signal input from the main CPU are reset, and the specified clock signal that is input is counted and programmable within the time indicated by the preset value set by the main CPU. A counter circuit that outputs a third abnormality detection signal when a reset signal is not input to and a logical sum circuit that performs a logical sum of the first, second, and third abnormality detection signals are provided. The traffic congestion signal is calculated.

[Work]

In the present invention, the main CPU and the sub CPU mutually search for the other party's abnormality, and when the other party's abnormality is detected, the first and second abnormality detection signals are output respectively, and the main CPU completes the sequence operation. The counter circuit that is reset by the reset signal that is input every time counts the predetermined input clock signal and does not input the reset signal within the time indicated by the preset value programmable by the main CPU. And a third abnormality detection signal are output, the logical sum of the first, second and third abnormality detection signals is obtained by the logical sum circuit, and the logical sum output becomes the operation congestion signal.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of an apparatus for monitoring traffic congestion according to the present invention. (1) is a counter circuit, (2) is a clock, (3a) and (3b) are main,
Sub CPU, (4) is an OR circuit, the main of (3a), (3b),
The sub CPU mutually searches for the other party's abnormality, activates the counter circuit (1) to time the sequence calculation of the main CPU (3), and when there is an abnormality, the OR circuit (4) outputs a traffic jam signal. It has become.

In the sequence control device configured as described above, the main CPU (3a) first sets the counter circuit (1) in a programmable manner and starts the sequence operation. main
When the CPU (3a) performs a sequence operation and this operation is completed within a predetermined time, the counter circuit (1) is reset via the A line shown in the figure by a command from the main CPU (3a). Main CP
If the sequence calculation by U (3a) is congested and the sequence calculation of each step is not performed within a predetermined time, immediately the third abnormality is caused in the logical sum circuit, for example, the OR circuit (5) via the B line shown in the figure. The detection signal is transmitted and the calculation congestion signal is issued.

When either the main CPU (3a) or the sub CPU (3b) is in an abnormal state, the first abnormality detection signal or the second abnormality detection signal or the second abnormality detection signal is sent to the OR circuit (5) via the illustrated C or D line, respectively.
The abnormality detection signal is transmitted, and the operation congestion signal indicated by E is issued.

In the above embodiment, the case of the sequence calculation by the programmable controller is described, but it goes without saying that the present invention can also be applied to the case of the calculation by another sequence control device.

〔The invention's effect〕

As described above, according to the present invention, the main CPU and the sub CPU mutually search for the other party's abnormality, and when the other party's abnormality is detected, the first and second abnormality detection signals are output, respectively.
A counter circuit that is reset by a reset signal that is input each time the sequence operation is completed counts a predetermined clock signal that is input and is programmable and resets within the time indicated by the preset value set by the main CPU in advance. When no signal is input, the third abnormality detection signal is output, the logical sum of the first, second and third abnormality detection signals is taken by the logical sum circuit, and this logical sum output is used as the operation congestion signal. Therefore, it is possible to perform programmable and accurate calculation traffic congestion detection, prevent detection omission in calculation traffic congestion detection, and improve the reliability of an apparatus using the detection traffic congestion.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an apparatus for monitoring traffic congestion according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional traffic congestion monitoring apparatus. In the figure, (1) is a counter circuit, (2) is a clock, (3a) is a main CPU, (3b) is a sub CPU, and (4) is an OR circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A main CPU and a sub CPU, which perform sequence control, mutually search for the other party's abnormality, and output first and second abnormality detection signals respectively when the other party's abnormality is detected, and a sequence operation. Each time the end of the above, it is reset by the reset signal input from the main CPU and counts a predetermined clock signal that is input, and the reset is performed within the time indicated by the preset value that is programmable in advance and set by the main CPU. A counter circuit that outputs a third abnormality detection signal when no signal is input, and a logical sum circuit that performs a logical sum of the first, second, and third abnormality detection signals are provided, and the output of the logical sum circuit is calculated. A traffic jam monitoring device characterized by using a traffic jam signal.