JPH02271449A - Bus fault detecting system - Google Patents

Bus fault detecting system

Info

Publication number
JPH02271449A
JPH02271449A JP1093489A JP9348989A JPH02271449A JP H02271449 A JPH02271449 A JP H02271449A JP 1093489 A JP1093489 A JP 1093489A JP 9348989 A JP9348989 A JP 9348989A JP H02271449 A JPH02271449 A JP H02271449A
Authority
JP
Japan
Prior art keywords
bus
timer
fault
equipment
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1093489A
Other languages
Japanese (ja)
Inventor
Akira Sekiguchi
章 関口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1093489A priority Critical patent/JPH02271449A/en
Publication of JPH02271449A publication Critical patent/JPH02271449A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent unnecessary bus holding at the time of the occurrence of bus fault and to improve the using efficiency of the bus by setting the monitoring time of a bus fault detecting timer to an optimum value at every equipment with which a data processor executes communication. CONSTITUTION:When a data processor 1 communicates with an equipment 4, the processor 1 sets the timer monitoring time for which the response speed of the equipment 4 is taken into consideration to a timer register 3a through the signal line 2c of a bus 2. When the processor 1 sends an order to the equipment 4, a bus fault detection timer 3b detects the address strobe signal of this order on the signal line 2b of the bus 2 to start the time monitor. When the equipment 4 is in fault, the address strobe signal of response information cannot be sent within the timer monitoring time set to the register 3a and the timer 3b overflows. The timer 3b detects the bus stack fault by this overflow and sends a bus error signal to the signal line 2a of the bus 2 to inform the processor 1 of this fault, and the output of the equipment in fault to the bus 2 is released.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は装置間をバス接続したデータ処理システムのバ
ス障害検出方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus fault detection method for a data processing system in which devices are connected via a bus.

〔従来の技術〕[Conventional technology]

従来、この種のデータ処理システムのバス障害検出方式
としては、バス制御線におけるスタックの時間監視を行
う方式がある。すなわち、データ処理装置からの通信に
対する他装置からの応答時間を監視するバス障害検出用
タイマを設け、このバス障害検出用タイマがオーバフロ
ーするまでに応答がないと、バス障害発生と判定してい
る。
Conventionally, as a bus failure detection method for this type of data processing system, there is a method of monitoring the stack time on the bus control line. That is, a bus fault detection timer is provided to monitor the response time from other devices to communication from the data processing device, and if there is no response before this bus fault detection timer overflows, it is determined that a bus fault has occurred. .

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のバス障害検出方式は、バス障害検出用タ
イマのバススタックの監視時間の値がデータ処理装置と
他の装置間にて行う通信によるバス保留時間の最大のも
のを考慮した固定値(例えば150μs)となっている
、また、−度バススタックが発生した場合、バススタッ
クの要因とは無関係にバス障害検出用タイマがオーバフ
ローするまでバスが開放されない。
In the conventional bus failure detection method described above, the value of the bus stack monitoring time of the bus failure detection timer is a fixed value ( For example, 150 μs), and if a -degree bus stuck occurs, the bus will not be released until the bus fault detection timer overflows, regardless of the cause of the bus stuck.

このため、バス保留時間の短い通信(例えば1μs)が
スタックした場合においても、不要な時間をバス障害検
出用タイマがカウントすることになり、不要なバス保留
を行うという欠点がある。
Therefore, even if a communication with a short bus holding time (for example, 1 μs) gets stuck, the bus fault detection timer counts unnecessary time, resulting in unnecessary bus holding.

本発明の目的は、データ処理システムのバス障害発生時
に、不要なバス保留をせず、バスの使用効率の向上を可
能とするバス障害検出方式を提供することである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a bus failure detection method that does not hold the bus unnecessary when a bus failure occurs in a data processing system and can improve bus usage efficiency.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のバス障害検出方式は、データ処理装置と前記デ
ータ処理装置と通信する複数の装置間をバスで接続した
データ処理システムの、前記バスの障害検出を前記装置
間の通信のスタックの時間監視により行うバス障害検出
方式において、前記データ処理装置が、通信先の前記装
置の応答時間に対応して、バス障害検出用監視時間の値
を設定することを特徴とする。
The bus fault detection method of the present invention detects a fault in the bus in a data processing system in which a data processing device and a plurality of devices communicating with the data processing device are connected by a bus, by monitoring the stack time of communication between the devices. In the bus fault detection method carried out by the method, the data processing device sets a value of a monitoring time for bus fault detection in accordance with a response time of the communication destination device.

〔実施例〕〔Example〕

次に図面を参照して本発明の詳細な説明する。 Next, the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例の構成を示すブロック図であ
る0本実施例のデータ処理システムは、データ処理を行
うデータ処理袋filと、データ処理装置1と通信しデ
ータの入出力動作を行う複数の装置4,5と、上記装置
間を接続するバス2と、監視時間の値を設定するタイマ
用レジスタ3aと、タイマ用レジスタ3aで指定された
時1mのバス2のスタックの監視を行うバス障害検出用
タイマ3bとを有するバス障害検出回路3とが設けられ
ている。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The data processing system of this embodiment includes a data processing bag fil that performs data processing, and a data processing device 1 that communicates with each other to perform data input/output operations. A bus 2 that connects the devices, a timer register 3a that sets the value of the monitoring time, and a stack of the bus 2 that is 1 m long when specified by the timer register 3a. A bus fault detection circuit 3 having a bus fault detection timer 3b is provided.

また、バス2は、バスエラ信号用の信号線2aと、アド
レスストローブ信号用の信号線2bと、その他の制御信
号やアドレス、データ信号用の信号112cとを備えて
いる。
The bus 2 also includes a signal line 2a for a bus error signal, a signal line 2b for an address strobe signal, and a signal 112c for other control signals, addresses, and data signals.

次に動作を説明する。データ処理装置1が装置4に対し
て通信を行う場合、前もってデータ処理装置1は装置4
の応答速度を考慮したタイマ監視時間をタイマ用レジス
タ3aに、バス2の信号線2cを介して設定する。デー
タ処理装置1が装置4に対してオーダの送出を行うと、
バス障害検出用タイマ3bがバス2の信号線2bにおけ
るこのオーダのアドレスストローブ信号を検出し、時間
監視を開始する。
Next, the operation will be explained. When data processing device 1 communicates with device 4, data processing device 1 communicates with device 4 in advance.
A timer monitoring time that takes into account the response speed of is set in the timer register 3a via the signal line 2c of the bus 2. When the data processing device 1 sends an order to the device 4,
The bus fault detection timer 3b detects the address strobe signal of this order on the signal line 2b of the bus 2 and starts time monitoring.

装置4が正常の場合は、タイマ用レジスタ3aに設定さ
れたタイマ監視時間以内に、応答の情報をデータ処理装
置1に返送する。バス障害検出用タイマ3bは、この応
答情報の信号112bにおけるアドレスストローブ信号
を検出し、時間監視を終了する。
If the device 4 is normal, it returns response information to the data processing device 1 within the timer monitoring time set in the timer register 3a. The bus failure detection timer 3b detects the address strobe signal in the response information signal 112b and ends time monitoring.

装W、4が障害の場合は、タイマ用レジスタ3aに設定
されたタイマ監視時間以内に、応答情報のアドレススト
ローブ信号を送出できず、バス障害検出用タイマ3bが
オーバフローする。バス障害検出用タイマ3bは、これ
によりバススタック障害を検出し、バス2の信号線2a
にバスエラ信号を送出して、データ処理装置lに通知す
るとともに、III′i!F装置のバス2への出力を解
除させる。
If the devices W and 4 are in failure, the address strobe signal of the response information cannot be sent out within the timer monitoring time set in the timer register 3a, and the bus failure detection timer 3b overflows. The bus fault detection timer 3b thereby detects a bus stack fault, and the signal line 2a of the bus 2
III′i! The output of device F to bus 2 is canceled.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明のバス障害検出方式は、バ
ス障害検出用タイマの監視時間の値をデータ処理装置が
通信を行なう装置ごとに最適な値に設定するので、バス
障害発生時に、不要なバス保留をなくし、バスの使用効
率を上げることができる効果がある。
As explained above, the bus fault detection method of the present invention sets the value of the monitoring time of the bus fault detection timer to the optimum value for each device with which the data processing device communicates, so that when a bus fault occurs, unnecessary This has the effect of eliminating the need for buses to be held and increasing the efficiency of bus usage.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の構成を示すブロック図であ
る。 1・・・データ処理装置、2・・・バス、2a+ 2 
b 。 2c・・・信号線、3・・・バス障害検出回路、3a・
・・タイマ用レジスタ、3b・・・バス障害検出用タイ
マ、4.5・・・装置。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 1... Data processing device, 2... Bus, 2a+ 2
b. 2c... Signal line, 3... Bus fault detection circuit, 3a.
... Timer register, 3b... Bus failure detection timer, 4.5... Device.

Claims (1)

【特許請求の範囲】[Claims] データ処理装置と前記データ処理装置と通信する複数の
装置間をバスで接続したデータ処理システムの、前記バ
スの障害検出を前記装置間の通信のスタックの時間監視
により行うバス障害検出方式において、前記データ処理
装置が、通信先の前記装置の応答時間に対応して、バス
障害検出用監視時間の値を設定することを特徴とするバ
ス障害検出方式。
In a bus failure detection method of a data processing system in which a data processing device and a plurality of devices communicating with the data processing device are connected by a bus, failure of the bus is detected by monitoring stack time of communication between the devices. A bus failure detection method characterized in that a data processing device sets a value of a monitoring time for bus failure detection in accordance with a response time of the communication destination device.
JP1093489A 1989-04-12 1989-04-12 Bus fault detecting system Pending JPH02271449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1093489A JPH02271449A (en) 1989-04-12 1989-04-12 Bus fault detecting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1093489A JPH02271449A (en) 1989-04-12 1989-04-12 Bus fault detecting system

Publications (1)

Publication Number Publication Date
JPH02271449A true JPH02271449A (en) 1990-11-06

Family

ID=14083757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1093489A Pending JPH02271449A (en) 1989-04-12 1989-04-12 Bus fault detecting system

Country Status (1)

Country Link
JP (1) JPH02271449A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2334652A (en) * 1997-12-15 1999-08-25 Lg Electronics Inc Apparatus and method for checking for defects in serial communication devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2334652A (en) * 1997-12-15 1999-08-25 Lg Electronics Inc Apparatus and method for checking for defects in serial communication devices

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