JPS63121999A - Output decision circuit for s/d converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an output determination circuit for an S/D converter that converts synchronized electrical machine data into digital data, and in particular,
S/D that prevents the abnormal output from being transmitted to a control device such as a computer when the output of the converter becomes abnormal due to noise etc.
The present invention relates to a converter output determination circuit.

[Conventional technology]

Signals such as ship logs and gyros are sent by synchro electric machine signals, but the output of the synchro electric machines may become abnormal due to the influence of noise.

If the ship's position is calculated using this abnormal value, an abnormal calculation result will be obtained, so some kind of countermeasure is required.

As a conventional technology that takes such measures, Japanese Patent Application Laid-Open No. 58-99
There is one described in Publication No. 898. In this prior art, the previous measurement data and the current measurement data are compared, and when these errors are large, an abnormality signal is output.

[Problem that the invention seeks to solve]

In the conventional technology described above, an abnormality signal is output when an abnormality occurs in data. However, simply outputting an abnormality signal requires that the computer that receives the abnormality signal process the results calculated based on the abnormality data input to the control device using software. There is a problem that the load increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide an S/D converter output determination circuit that performs hardware processing when abnormal data is output from the S/D converter and does not increase the load on the computer.

[Means for solving problems]

The above purpose is to develop an output determination circuit for an S/D converter.

A first register that sequentially holds the output data of the S/D converter, a second register that sequentially holds the contents of the first register, previous data in the second register, and current data in the second register. an error determination circuit that calculates the difference between the two and outputs an abnormal signal when the difference is equal to or greater than a predetermined value; This is achieved by arranging a third register which stops taking in data from the first register when it outputs an abnormal signal, holds the data before the stop, and outputs it to the subsequent stage.

[Effect]

The contents of the third register, which sends data to the subsequent stage of the control device, etc., are the same as the output data of the S/D converter while abnormal data is not output. When abnormal data is output, the third register often takes in this abnormal data and remains the normal data before the abnormal data occurred, so that the abnormal data is not sent to the control device.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows 57. FIG. 2 is a configuration diagram of a converter output determination circuit. In FIG. 1, a '/n conversion circuit 1. converts synchro electric machine data into digital data.
Register 2 to save digital data after S/D conversion
．． Register 6 to save the previous data, register 4 to save the data to be output to the outside. Each error judgment circuit 5 has a circuit that takes the difference between the previous data saved in register 3 and the current data saved in register 2, compares it with a given tolerance, and judges the rationality of the data. The timing generation circuit 6 which generates a timing pulse for saving data in the registers 2, 3.4, and the error determination circuit 6 are ANDed with the timing pulses of the timing generation circuit 6. It is composed of a 4ND circuit 7.

FIG. 2 is an operation timing chart of the output determination circuit shown in FIG. 1. PI + Pt + PI, p4 and P.

are timing pulses generated from the timing generator 6 and error determination circuit 5 to each register 2, 3.4 and AND circuit 7. Also, j6 + dl r (Lt l
'! and ct4 indicate data received by each register according to the timing pulse.

In FIG. 1, an S/D conversion circuit 1 receives synchro electric machine data d0 and outputs digital data d. Timing pulse p generated from timing generation circuit 6
, , p, and Ps are stored in register 2. at the timing shown. It is input to the register 3 and the AND circuit 7, and each register 2.3 sets data dl r dl, respectively, by this timing pulse PI*P2.

As can be seen from the time chart in Figure 2, the timing pulse P! The data d is set in the register 3 by this, and then the retator et1 is set in the register 2 by the timing pulse P1. As a result, the current data α is stored in register 2, and the previous data α++ is stored in register 3.
-1 (3 is a natural number) is set.

The error judgment circuit 5 has a comparison value A for checking rationality in the circuit.
The comparison value A can also be received from the outside. The error determination circuit 5 receives data d from the register 2 and the register 3, respectively.

and data d, and the absolute value of the difference B −Idt
-dsl is determined, the difference B is compared with the comparison value A, and if A>B, a timing pulse P4 is generated in the AND circuit 7. AND circuit 7 receives timing pulses P4 and vps of error determination circuit 5 and timing generator 6.

Timing pulse P when AND is obtained! occurs.

Timing pulse P causes register 4 to receive data d2 and output external hetator d4. Digital data d4 shown in FIG. 2 shows the behavior of data when data α3 is affected by noise or the like and becomes abnormal.

The above can be summarized as follows. The circuit shown in Figure 1 converts the input synchro electric machine data d0 into digital data d, and determines the error between the output data (current data) dt of the register 2 that has received this data and the previous data d. The circuit 5 compares the data, and if the rate of change is within the allowable value, the data d is output as d4, and if it is equal to or greater than the incorrect answer value, the data that has been output until now is output.

Normally, a control device such as a computer performs a process of determining the rationality of data input from the outside and eliminating unreasonable data. Especially when used in an environment with a lot of external noise, such as a ship system, this processing is performed by an electronic computer. For example, in the process of calculating the position of your own ship from moment to moment, course and speed data is
The data is input through /D conversion, and processed after the rationality of these data is determined by an electronic computer.

However, making this rationality determination using a computer increases the load on the computer. In the past, if data that had been checked for rationality was sent to a computer, the load on the computer would be reduced, leading to more effective use of the computer.

〔Effect of the invention〕

According to the present invention, since only reasonable data is sent to the control device side, highly reliable data can be obtained without increasing the burden on the computer.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an output determination circuit of an S/D converter according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation. 1...S/D converter 2.3.4...
·register

Claims (1)

[Claims] 1. A first register that sequentially holds the output data of the S/D converter, a second register that sequentially holds the contents of the first register, and the previous data in the second register and the current data in the first register. an error determination circuit that calculates a difference between the data and outputs an abnormal signal when the difference is equal to or greater than a predetermined value; and when the abnormal signal is not output, sequentially captures the contents of the first register and outputs them to a subsequent stage; an output determination circuit for an S/D converter, comprising: a third register that stops taking in data from the first register when the abnormal signal is output and outputs the data that has been taken and held before stopping to a subsequent stage;