JPS6213139A - Supervisory circuit - Google Patents

Abstract

PURPOSE:To supervise simply and surely a main signal of a buffer circuit by counting number of '1's of '0's of a digital signal in the unit of N bits and inverting the digital signal string at least one period per two periods in the process of supervising the buffer circuit. CONSTITUTION:The 1st count result 3 is obtained by the 1st counter circuit 101 at each period of a reference signal 1 from number of '1's or '0's of the digital signal 2. The '1' and '0' of the data are inverted by two periods by the 1st inverting circuit 102 from the 1st count result 3 and the digital signal 2. The 2nd inverting circuit 104 inverts the digital signal 5' and the 1st count result 6' again to output the digital signal 5 and the 1st count result 6. The 2nd count circuit 106 counts again the number of '1's or '0's of the digital signal 5 inverted again at each period of a reference signal 4 to output the 2nd count result 7. The 2nd count result 7 and the 1st count result 6 are compared by a comparison circuit 105 to attain the supervision of a bit delay circuit 103.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to monitoring circuits, and more particularly to bit delay circuits.

This invention relates to a circuit that monitors timing control circuits such as frame matching circuits and frame conversion circuits within bits and on a bit-by-bit basis.

[Conventional technology]

An example of a conventionally used monitoring circuit is a pin
□The case of monitoring the delay circuit will be explained with reference to FIG. In FIG. 2, numeral 101 is a first counting circuit which counts the number of 0'1'' or 0' of the digital signal 2 every 10 periods of the reference signal and outputs the first counting result 3. Reference numeral 103 denotes a bit delay circuit which delays the reference signal 1, digital signal 2 and first counting result 3 by a fixed amount in bit units, and outputs the reference signal 4.degree. digital signal 5 and the first counting result 6. 106 is a second counting circuit that counts the number of '°1' or '0' of the digital signal 5 every period of the reference signal 4, and outputs the second counting result 7. 105 is a comparison circuit. First counting result 6 and second counting result
□7 every 40 cycles of the reference signal, and if there is an error, error information 8 is output.

In this monitoring circuit, "'1" of digital signal 2 or I
The first counting circuit 1 calculates the number of I On every period of the reference signal 1.
01, together with reference signal 1 and digital signal 2,
The first counting result 3 is counted by the second counting circuit 106 again by the number of °'1'' or par0'' of the bit delayed mouth signal 5 every period of the reference signal 4, and the first counting result 6 is obtained. The bit delay circuit 103 is monitored by comparing it with the second counting result 7 in a comparison circuit 105 every cycle of the reference signal 4.

[Problem that the invention seeks to solve]

However, in this circuit, if an abnormality occurs in the bit delay circuit 103 and the digital signal 5 and the first counting result 6 are erroneously fixed at 0'', the second counting circuit 106
Since it is not possible to count the number of degrees 1'' in the digital signal 5 and outputs "o" as the second counting result 7, the comparator circuit 105 cannot detect an error. Similarly, the digital signal 5 and the first counting result 6 are mistakenly “1.”
Even if the error is fixed to ``, a situation may occur in which errors cannot be detected.

SUMMARY OF THE INVENTION An object of the present invention is to provide a monitoring circuit that eliminates the above drawbacks with a simple external circuit configuration.

[Failure to solve the problem]

The monitoring circuit according to the present invention detects ``1'' of a digital signal train.
Alternatively, a first counting circuit that counts the number of 0''' every N bits (N: natural number), and a first counting circuit that counts the number of 0''' in units of N bits (N: natural number), and converts the digital signal sequence into M periods (M: natural number) with L periods (M: natural number), L: natural number, M) A first inverting circuit that inverts data 1''''``0'' by L), and a muffer circuit that controls timing by inputting the output signal string of the -th inverting circuit.

a second inversion circuit that re-inverts the output of the buffer circuit; and a second counter that counts the number of It I II or II OII of the digital signal string output from the second inversion circuit in units of N bits. and a comparison circuit that compares the first counting result with the second counting result of the second counting circuit.

〔Example〕

Examples of the present invention will be described below.

FIG. 1 shows an embodiment of a monitoring circuit according to the present invention, and shows an example of monitoring a bit delay circuit.

Components that are the same as those in FIG. 2 are given the same numbers and their explanations will be omitted. Here, a case will be explained in which the reference signal 1 has a period of N bits, and N is an even number. 102 is a first inverting circuit which inverts the digital signal 2 and the first counting result 3 by using the period of the reference signal l as a period unit, and inverts the data °°1" and "0# only once every two periods. 9 outputs the inverted digital signal 2 and the first counting result 3'.

Therefore, the bit delay circuit 103 delays the reference signal 1, the inverted digital signal 2, and the inverted first count resultant by a fixed amount bit by bit, respectively. The first counting result 6' is output. 104 is a second inverting circuit, which uses 40 cycles of the reference signal as a unit of one cycle, and similarly to the first inverting circuit 102, it inverts data only once every two cycles.
11#.

"0P is inverted. As a result, the digital signal 5' and the first count result 6' are inverted again, and the digital signal 5 and the first count result 6 are output.

Next, the operation of this circuit will be explained.

A first counting result 3 is obtained from the number of degrees 1'' or 0'' of the digital signal 2 by the first counting circuit 101 every cycle of the reference signal 1. The first counting result 3 and the digital signal 2 are inverted by the first inverting circuit 102 by two periods with the period of the reference signal 1 as one period unit, and further converted into a reference signal. Bit delay circuit 103 along with signal 1
is delayed by a fixed amount in bits. The second inverting circuit 104 inverts the digital signal 5' and the first counting result 6' again, using one period of the reference signal 4 output from the bit delay circuit 103 as a period unit, and converts the digital signal 5' into the digital signal 5.
and the first counting result 6 are output. Second counting circuit 10
6 is "'1"' or " of the re-inverted digital signal 5.
0'' is counted again every cycle of the reference signal 4 and outputs the second counting result 7. This second counting result 7 and the first counting result 6 are compared by the comparator circuit 105. The delay circuit 103 can be monitored.

That is, in the bit delay circuit 103, the digital signal 5
1 and the first counting result 6' are °'】"alsoi'" o
”, the second inverting circuit 104 converts the digital signal 5 and the first division result 6 to “’1” every cycle.
As a result, the second divisor obtained by dividing the number of "1" or II OrH of the digital signal 5 by the second counting circuit 106 every period of the reference signal 4 is obtained. The result 7 is the first divisor result 6 and the comparison circuit 10.
5, there is always an error in one out of every two cycles, and errors can be detected reliably.

In the above description, a bit delay circuit was explained as a buffer circuit, but a frame matching circuit is used as a buffer circuit.

It is clear that even a frame conversion circuit or the like can be monitored in the same way as a bit delay circuit. The above explanation is for the case where N is an even number, but when N is an odd number, the first inversion circuit 102 and the second inversion circuit 104 invert only the digital signal train by one period every two periods. and the first counting result 3 is transferred to the first inverting circuit 102. It can be easily inferred that this can be handled by bypassing the bit delay circuit 103 and the second inverting circuit 104.

As described above, in this embodiment, the main signal of the buffer circuit can be easily and reliably monitored by inverting at least one period every two periods of the digital signal train in the process of monitoring the buffer circuit.

〔Effect of the invention〕

As explained above, the present invention is applicable to
Or count the number of '0''' in N bit units.

This counting result and at least the digital signal are divided into M periods with N bit periods as one period unit.
By inverting the period of the data P1''j, (IQ'''', the digital signal is converted into bits.

Main signals in buffer circuits such as bit delay circuits, frame matching circuits, frame conversion circuits, etc. that are controlled in units of bits can be easily and reliably monitored.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a monitoring circuit according to the present invention, and FIG. 2 is a block diagram of a conventional monitoring circuit. In the figure, 101 is a first counting circuit, 1o2 is a first inversion circuit, 103 is a bit delay circuit, 1o4 is a second inversion circuit, 105 is a comparison circuit, and 1o6 is a second divisor circuit.

Claims (1)

[Claims] 1. A first counting circuit that counts the number of "1" or "0" in a digital signal string every N bits (N: natural number);
The digital signal string is divided into M periods (M: natural number) and L periods (M: natural number, M>L) with N bit periods as one period unit.
), a buffer circuit that inputs the inversion circuit output signal sequence and controls timing, and a second inversion circuit that re-inverts the output of the buffer circuit. a second counting circuit that counts the number of "1"s or "0"s in the digital signal string outputted from the second inverting circuit in units of N bits; A monitoring circuit comprising: a comparison circuit for comparing the second counting result of the second counting circuit.