JPH02250442A - Signal missing release condition detector - Google Patents

Abstract

PURPOSE:To correct an error of a detection circuit with other detection circuit and to avoid erroneous signal missing release by providing 2 sets of detection circuits and a final stage AND circuit ANDing outputs of the 2 sets of the detection circuits. CONSTITUTION:A final stage AND circuit 30 ANDs outputs of detection circuits 10, 20 and even when an erroneous value is outputted by the detection circuit 10, clocks after the '33th' and succeeding clock are sampled for a half period (16 bits) by the detection circuit 20 in addition to clock from 18th till 32nd representing consecutive '0s' to avoid an error of signal missing release in 16-bit or over of consecutive '0s'. Thus, the error of one detection circuit is corrected by the other detection circuit to avoid erroneous signal missing release.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a maintenance device for an asynchronous multiplexing device, and particularly to a device for detecting a condition for canceling signal loss.

[Conventional technology]

FIG. 4 shows a conventional North American asynchronous digital multiplexer. In the same figure, 1allb is an AND circuit, 2a, 2b
is an inverter, 3.4 is a counter, 5 is an OR circuit, 6 is a timer, 7a and 7b are RS flip-flops, 8 is an AND circuit, and 9 is a latch circuit.

In FIG. 4, the timer 6 provides a 32-bit determination time, and the counter 3 detects whether the mark rate of the data string a between the pulses output from the timer 6 is 1/8 or more, Counter 4 is 1 when consecutive 0s in data string a
Detect whether it is 5 bits or less. Mark rate is 17
When the number is 8 or more, the counter 3 outputs rlJ, and when the number of consecutive "0" bits is 15 bits or less, the counter 4 outputs "0". Therefore, the inverter 2b outputs "1" when the number of consecutive "0"s is 15 bits or less. Also, AND circuit 8
takes the AND of the outputs of the RS flip-flop 7a and the inverter 2b, and the latch circuit 9 stores the output signal of the AND circuit 8 as an output pulse from the timer 6. Note that the number of focuses is determined by the number of clocks b in the target time.

[Problem to be solved by the invention]

However, in the conventional signal loss cancellation condition detection device, as shown in FIG.
” exists, and 14 consecutive bits r
In the case of data string a where OJ exists, a problem has occurred. In other words, in the case of a data string as shown in FIG.
8 or more, consecutive "0" is 15 bits or less, so
The output of the AND circuit 8 is "1", that is, the latch circuit 9 is "1".
” is latched. Therefore, even though there are 28 consecutive "0" bits in periods T2 and T1, signal loss (L
There was a problem in which the oss of Signal was canceled.

The present invention has been made in view of these points, and its purpose is to provide a signal that does not release signal loss when there are 16 or more consecutive "e"s as shown in periods T2 and T1. An object of the present invention is to obtain an erasure cancellation condition detection device.

[Means to solve the problem]

In order to achieve such an object, the present invention provides a signal loss cancellation condition detection device having a first detection circuit, a second detection circuit, and a final stage AND circuit, the first detection circuit comprising:
The mark rate of the data string between the first timer that gives the judgment time and the pulse output from this first timer is 1/
a first counter that detects that the number is 8 or more; a second counter that detects that the number of consecutive zeros in the data string is 15 bits or less; a first AND circuit that performs logical product;
a first latch circuit that stores the output signal of the AND circuit as a pulse output from the first timer; a second timer that outputs as a reference for the first timer; a third counter that detects that the mark rate of the data string between the pulses output from the first timer is 1/8 or more; a fourth counter that detects that the number of consecutive zeros is 15 bits or less, and a second AND circuit that takes the logical product of the output signals of the first counter and the second counter;
a second latch circuit that stores the output signal of the second AND circuit as a pulse output from a second timer;
The final stage AND circuit is configured to perform a logical product of the outputs of the first latch circuit and the second latch circuit.

[Effect]

In the signal loss release condition detection device according to the present invention, the judgment time given by the second timer is shifted by half a cycle from the judgment time given by the first timer.

〔Example〕

An overview of the present invention will be described. The present invention comprises a first detection circuit as a conventional signal loss canceling condition detection device, a second detection circuit having the same configuration as the conventional one but whose timer period is shifted by half a period, and a final stage AND circuit. The outputs of the first and second detection circuits are input to the final stage AND circuit.

In the conventional device, the period T2. in FIG. Even if rOJ is continuous for 16 bits or more as shown in Tl, the signal loss is canceled by the latch circuit 9 at the 32nd bit.However, in the device according to the present invention, the signal loss is not canceled. This is because the period of the timer of the second detection circuit is half a period (for example, 1
6 bits), consecutive "0"s in the data string input to the first detection circuit will be seen by the second detection circuit for an additional half cycle.

This eliminates the cancellation of signal loss that occurs in conventional devices, and enables error-free detection of signal loss cancellation conditions.

FIG. 1 is a system diagram showing an embodiment of the signal loss release condition detection device according to the present invention. In Figure 1, la, lb
is an AND circuit, 2a and 2b are inverters, 3 is a first counter, 4 is a second counter, 5 is an OR circuit, and 6 is a first counter.
, 7a and 7b are RS flip-flops, 8 is a first AND circuit, 9 is a first latch circuit, and 10 is a first detection circuit. Also, lla and llb are AND circuits,
12a and 12b are inverters, 13 is a third counter,
14 is a fourth counter, 15 is an OR circuit, 16 is a second timer, 17a and 17b are RS flip-flops, 18
is a second AND circuit, 19 is a second latch circuit, and 20 is a second detection circuit.

Furthermore, 30 is a final stage AND circuit.

FIG. 2 is a time chart for explaining the operation of the first detection circuit 10, and FIG. 3 is a time chart for explaining the operation of the second detection circuit 20 and the final stage AND circuit 30.

Next, the operation of the apparatus shown in FIG. 1 will be explained.

The detection circuits 10 and 20 shown in FIG.
a)), the timers 6 and 16 output one pulse every 32 clock cycles (FIG. 2(h)).

3(f)), in the data string a, during the detection period of the signal loss release condition, the central 4 bits of the clock are "l".
Before and after the "1" level corresponding to 4 bits, the 1 level corresponds to clock groups A and B shown in FIG. 2(a).
It is a 4-bit rOJ.

In the first detection circuit 10, from the time when the detection circuit 10 is reset by the output pulse of the timer 6 until the detection circuit 10 is reset again, "1" in the data a inputted through the AND circuit 1a is counted by the counter 3. If 4 or more (mark rate 1/8 or more) 1's are counted during 32 clock cycles (4 1's as shown in (C) in Figure 2), the counter 3 will count 1's. ” in Figure 2 (d)), R
Set the S flip-flop 7a (Fig. 2 (1))
. The output of the RS flip-flop 7a is input to an AND circuit 8.

Further, the inverter 2a inverts the data string a (FIG. 2(e)). As a result, when the data string a is rOJ, the clock b is input to the counter 4 via the AND circuit 1b (FIG. 2(f)). The counter 4 counts "0" in the data string a inputted through the AND circuit 1b, and if it counts 16 bits continuously, sets the RS flipflop 7b. However, in the case of Figure 2, there are 14 consecutive "0" bits during the detection period, and the output of counter 4 remains "0" (Figure 2 (g
)), RS flip-flop '7b is not sent. The inverter 2b inverts the output of the RS flip-flop 7b and inputs it to the AND circuit 8 (FIG. 2('')).

Next, each RS flip-flop 7a.

The output signal of 7b is input to the AND circuit 3. In FIG. 2, the RS flip-flop 7a is shown in FIG. 2(a).
The RS flip-flop 7b outputs "O", that is, the inverter 2b outputs "1", and the AND circuit 8 outputs "1" from the "11B" clock to the "32" clock shown in FIG. ``1'' is output from the ``32nd'' clock to the ``32nd'' clock. Therefore, the latch circuit 9 outputs "0" at the 633rd" clock shown in FIG. 2(a).
1", and this level "1" is output. Therefore, when the data string a in FIG. 2 is input to the detection circuit 10, the detection circuit 10 will prevent signal loss even if there are further clocks after clock group B as shown in FIG. 2(a). Eliminate.

When comparing the detection circuits 10 and 20, timer 6 and timer 16 are also timers that output pulses at 32 clock cycles, but timer 16 outputs pulses at half a cycle (16 clock cycles).
bit) differs in that it operates with a delay. However, in other operations, detection circuits 10 and 20 operate similarly.

As described above, with only the detection circuit 10, as shown in FIG. 2, even if a data string is input that should not cancel signal loss, the detection circuit 10 is reset by the timer 6 and then reset again. Since the detection circuit 10 does not count 16 clocks with the counter 4, the mark rate is 1/8 or more,
0” is considered to meet the standard of 15 consecutive bits or less,
Cancels signal loss.

However, by performing a logical AND operation on the outputs of the detection circuits 10 and 20 in the final stage AND circuit 30, even if the detection circuit 10 outputs an incorrect value, the continuous "0" shown in FIG. In addition to the 18th to 32nd clocks indicating the
0 can be sampled for an additional half cycle (16 bits), 16
It is possible to eliminate errors in canceling signal loss due to consecutive "0" bits or more.

Next, the operation of the detection circuit 20 outputting a signal indicating that the signal loss has not been canceled will be explained using FIGS. 1 to 3. Like the AND circuit 1a, the AND circuit 11a outputs a clock corresponding to the "1" level in the data string a (FIG. 3(a)). The counter 13 counts the number of output pulses from the AND circuit 11a in the same way as the power converter 3, and outputs "1" at the fourth pulse (see Fig. 3). The output pulse of the counter 13 is input to the RS flip-flop 17a and R
Set the S flip-flop 17a (Fig. 3(g)
), this state is maintained until the timer 16 outputs a reset pulse.

Further, in the same way as the inverter 2a, the inverter 12a inverts the data string a and outputs it to the AND circuit 11b (FIG. 3(C)). As a result, the AND circuit 11b allows the clock b to pass only while the data string a is "0" (Fig. 3(d)
)). The counter 14 counts the pulses output from the AND circuit 11b, and outputs a pulse of "1" at the 116th clock shown in FIG. 3(d).
1) Set the RSS flip-flop 1f and set the output of the inverter 12b to the "0" level (Fig. 3 (h)
). This state is maintained until the timer 16 outputs a reset pulse. From FIG. 3 (gl and (h)) showing the signals input to the AND circuit 18, the output of the AND circuit for one day is "0" as shown in FIG. 3 (1). Therefore, the output of the latch circuit 19 is also The result is "0" (Fig. 3 U)), and the AND circuit 30 that takes the AND of the latch circuits 9 and 19 becomes "0".
3(k)), and the signal loss is not canceled. In this way, detection circuit 20 can correct errors in detection circuit 10. Conversely, depending on the "1" of the data string a and the state of rOJ, the error in the detection circuit 20 may be corrected by the detection circuit 10.

〔Effect of the invention〕

As explained above, the present invention includes two sets of detection circuits and two sets of detection circuits.
By providing a final-stage AND circuit that takes the logical product of the outputs of the detection circuits in the set, an error in one detection circuit can be corrected by the other detection circuit, so there is no need to cancel the signal loss by mistake. There is an effect that can be used.

[Brief explanation of drawings]

FIG. 1 is a system diagram of an embodiment of the signal loss cancellation condition detecting device according to the present invention, FIGS. 2 and 3 are time charts for explaining the operation of the device shown in FIG. 1, and FIG. 4 is a conventional FIG. 5 is a system diagram showing the signal loss release condition detection device, and is a time chart for explaining the operation of the device shown in FIG. 4. la, 1b+ 8. lla, llb, 1B"'AND circuit, 2a, 2b, 12a, 12b...inverter,
3.4.13.14... counter, 5.15...
OR circuit, 6.16... timer, 7a, 7b, 17
a, 17 b. RS flip-flop, 9.19...
・Latch circuit, 10.20...detection circuit, 30...
Final stage AND circuit. Patent applicant: NEC Corporation Miyagi NEC Corporation

Claims (1)

[Claims] A signal loss release condition detection device having a first detection circuit, a second detection circuit, and a final stage AND circuit, wherein the first detection circuit has a first timer that provides a determination time. and,
A first counter detects that the mark rate of the data string between the pulses output from the first timer is 1/8 or more, and the number of consecutive zeros in the data string is 15 bits or less. a second counter that detects the occurrence of the
a first latch circuit that stores pulses output from the timer;
a third counter that detects that the mark rate of the data string between the pulses output from the first timer is 1/8 or more; a fourth counter that detects that the output signal is equal to or less than a bit; a second AND circuit that ANDs the output signals of the first counter and the second counter; a second latch circuit that stores data using pulses output from a timer, and the final stage AND circuit is characterized in that it takes the AND of the outputs of the first latch circuit and the second latch circuit. Signal loss release condition detection device.