JPS59144149A - 誘電体分離基板の製造方法 - Google Patents

誘電体分離基板の製造方法

Info

Publication number
JPS59144149A
JPS59144149A JP1914283A JP1914283A JPS59144149A JP S59144149 A JPS59144149 A JP S59144149A JP 1914283 A JP1914283 A JP 1914283A JP 1914283 A JP1914283 A JP 1914283A JP S59144149 A JPS59144149 A JP S59144149A
Authority
JP
Japan
Prior art keywords
silicon
substrate
single crystal
porous
crystal silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1914283A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6343887B2 (enrdf_load_stackoverflow
Inventor
Akinobu Satou
佐藤　倬暢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toko Inc
Original Assignee
Toko Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toko Inc filed Critical Toko Inc
Priority to JP1914283A priority Critical patent/JPS59144149A/ja
Publication of JPS59144149A publication Critical patent/JPS59144149A/ja
Publication of JPS6343887B2 publication Critical patent/JPS6343887B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/7627—Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
JP1914283A 1983-02-08 1983-02-08 誘電体分離基板の製造方法 Granted JPS59144149A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1914283A JPS59144149A (ja) 1983-02-08 1983-02-08 誘電体分離基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1914283A JPS59144149A (ja) 1983-02-08 1983-02-08 誘電体分離基板の製造方法

Publications (2)

Publication Number Publication Date
JPS59144149A true JPS59144149A (ja) 1984-08-18
JPS6343887B2 JPS6343887B2 (enrdf_load_stackoverflow) 1988-09-01

Family

ID=11991198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1914283A Granted JPS59144149A (ja) 1983-02-08 1983-02-08 誘電体分離基板の製造方法

Country Status (1)

Country Link
JP (1) JPS59144149A (enrdf_load_stackoverflow)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60189238A (ja) * 1984-03-09 1985-09-26 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPS62137839A (ja) * 1985-12-06 1987-06-20 テキサス　インスツルメンツ　インコ−ポレイテツド 半導体構造とその製造方法
US4910165A (en) * 1988-11-04 1990-03-20 Ncr Corporation Method for forming epitaxial silicon on insulator structures using oxidized porous silicon
US5258322A (en) * 1991-01-16 1993-11-02 Canon Kabushiki Kaisha Method of producing semiconductor substrate
US5427977A (en) * 1992-04-30 1995-06-27 Fujitsu Limited Method for manufacturing porous semiconductor light emitting device
US5439843A (en) * 1992-01-31 1995-08-08 Canon Kabushiki Kaisha Method for preparing a semiconductor substrate using porous silicon
US5766970A (en) * 1992-02-25 1998-06-16 Samsung Electronics Co., Ltd. Method of manufacturing a twin well semiconductor device with improved planarity

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60189238A (ja) * 1984-03-09 1985-09-26 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPS62137839A (ja) * 1985-12-06 1987-06-20 テキサス　インスツルメンツ　インコ−ポレイテツド 半導体構造とその製造方法
US4910165A (en) * 1988-11-04 1990-03-20 Ncr Corporation Method for forming epitaxial silicon on insulator structures using oxidized porous silicon
US5258322A (en) * 1991-01-16 1993-11-02 Canon Kabushiki Kaisha Method of producing semiconductor substrate
US5439843A (en) * 1992-01-31 1995-08-08 Canon Kabushiki Kaisha Method for preparing a semiconductor substrate using porous silicon
US5766970A (en) * 1992-02-25 1998-06-16 Samsung Electronics Co., Ltd. Method of manufacturing a twin well semiconductor device with improved planarity
US5427977A (en) * 1992-04-30 1995-06-27 Fujitsu Limited Method for manufacturing porous semiconductor light emitting device

Also Published As

Publication number Publication date
JPS6343887B2 (enrdf_load_stackoverflow) 1988-09-01

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