JPS5914222A - Ac switch circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AC switch circuit interposed between an AC power source and a load to prevent arcing between contacts that open and close.

In the prior art, an electrical change in a series circuit between an AC power supply and a load is detected, and an on pulse is derived every positive or negative half synchronization when the 441 and the second relay switch are off, and an on pulse is derived every positive or negative half synchronization when the 441 and the second relay switch are off. Derive the off pulse for each period,
The relay is driven by the coincidence of the command signal or its inverted signal for causing the first and second relay switches to operate eleven times and the on-pulse and off-pulse. However, undesigned on-pulses and off-pulses may occur when the load power supply recovers from a power failure or when the power is turned on.
As a result, there was a risk that 11 works would be created incorrectly.

The purpose of the present invention is to solve the above-mentioned technical problems and to solve the above-mentioned technical problems.
The purpose of the present invention is to provide an AC switch circuit that prevents the occurrence of damage.

The present invention will be described in detail with reference to 112 embodiments.

Referring to FIG. 1, an AC power supply 1 and a load 2 are interposed in series through terminals 3 and 4 in the AC switch circuit of the present invention. A series circuit 7 consisting of a diode 5 and a first relay switch 6 connected in series with the diode 5 is connected between the lines e3 and e4 connected to the terminals 3.4. A second relay switch 8 is connected in parallel to this series circuit 7.

(1 (< 1 6 relay switches, related to the first latching relay 10. This first latching relay IO is a so-called -wound type latching relay,
It has a relay coil 52. When this relay coil 52 is temporarily excited in the direction of arrow 57, the first relay switch 6 becomes conductive and mechanically maintains its conductive state. Furthermore, when the relay coil 52 is temporarily excited in the opposite direction of the arrow 58, the first relay switch 6 enters the cut-off state and maintains the cut-off state by itself.

A first relay drive circuit 61 is provided to drive the relay coil 52 of the first latching relay IO. In this first relay drive circuit 61, a transistor TR1 and a transistor TR2 serving as semiconductor switching elements
are connected in series, and their connection point 53 is connected to one terminal of the relay coil 52 of the first latching relay IO. Transistor TR3 and transistor TR4 are connected in series, and their connection point 54 is connected to the other terminal of relay coil 52.

Zener diodes 59 and 60 are connected in series in opposite directions between the connection points 53 and 54 to prevent back electromotive force of the relay coil 52.

The output of AND gate G4 is an inverting transistor TR5.
and the aforementioned transistor T
Given to the base of R4. The collector of transistor TR5 is connected to the base of transistor TR1. O
The output of the R GEG G7 is applied to the base of the transistor TR60, and is also applied to the base of the transistor TR2. The collector of transistor TR6 is connected to the base of transistor TR3.

When the output of AND gate G4 becomes high level, transistors TR4 and TR5 become conductive, and transistor TRI becomes conductive. The output of OR Gegu G7 is low level,
Therefore, transistors TR2 and TR6 are cut off. Therefore, transistor TR3 is cut off. Thus, the transistor TRI, the connection point 53, and the relay coil 52
, connection point 54, and transistor TR4, and a current flows through relay coil 52 in the direction of arrow 57. Therefore, the first relay switch 6 becomes conductive and self-maintained.

When the output from the OR gate G7 becomes high level, the transistors TR2 and TR6 become conductive, and the transistor TR3 becomes conductive. The output of AND gate G4 is at a low level, transistors TR4 and TR5 are cut off, and transistor TRI is cut off. In this way, transistor TR3, connection point 54, relay coil 52, connection point 53
A current path passing through the transistor TR2 is formed, and an excitation current flows through the relay coil 52 in the direction of arrow 58, which is the opposite direction to that described above. This causes the first relay switch 6 to shut off and maintain itself.

Second latching relay 13 associated with second relay switch 8 . Similarly to the first latching relay 10, the second relay latching relay is also a single-winding latching relay, and is provided with a second relay drive circuit 63 for driving the relay coil 62 thereof. this@
The two-relay intercostal path 63 is configured similarly to the first relay drive circuit 61, and includes transistors TR7 to TR12 and Zener diodes 68,69, and transistors *TR10, T
The output of AND gate G3 is applied to the base of R11, and the output of AND gate G3 is applied to the bases of transistors TR8 and TR12.

ANDG) When the output of G2 reaches the NO level, the transistors TRl0. TRII becomes conductive and transistor T
R7 is conductive. The output of AND gate G3 is at a low level, so transistors TR8 and TR12 are cut off. , so transistor TR9 is cut off. Thus, transistor TR7, connection point 64, relay coil 62, connection point 65, and transistor TR
A current path passing through l0 is formed, and current flows through relay coil 62 in the direction of arrow 6.6. Therefore, the second relay switch 8 becomes conductive and self-maintained.

When the output from the AND game 3 becomes high level, the transistors TR8 and TRI2 become conductive, and the transistor TR9 becomes conductive. The output of AND gate G2 is at a low level, and transistors TRl0. TRII is cut off and transistor TR7 is cut off. In this way, a current path passing through the transistor TR9, the connection point 65, the relay coil 62, the connection point 64, and the transistor FTR8 is formed.
Excitation current flows in seven directions. This causes the second relay switch 8 to shut off and maintain itself.

When the current flowing through the relay coils 52 and 62 is interrupted,
A voltage exceeding the voltage Vcc is generated in the relay coil 52.62, and the transistors TR1-TR12
In order not to destroy the Zener diode 59, 6 (1
, 68 and 69 are provided. Each terminal 1 (10a,
100b is given a supply type BEVCC. Here, the breakdown voltage of the Zener diodes 59, 60, 68°69 is a value exceeding the supply voltage Vcc (D voltage), and the first relay drive circuit 61 and the second relay [
This value is less than the voltage at which the transistors TRI to TR12 of the dynamic circuit 63 are destroyed.

AND gates G2, G3, G6 and OR gate G
When the outputs of 7 change from high level to low level, a counter electromotive force is generated in the relay coils 52 and 62. At this time, relay coil 52 → hA reading point s a → Zener diode 59- + Zener diode 60 → connection point 5
4 → Relay coil 52, Sea coil 62 → Connection point 64
→ Zener diode 8 → Zener diode 69 → Connection point as → IJ l/- Current flows in the coil 62 or the opposite direction, and the Zener diode 59, 60, 68.
69 is preikdakun. Zener diode 59,6
Since 0°68.69 is broken down, the back electromotive force is absorbed and the transistors TR1 to TR12 are not destroyed.

A series circuit consisting of a primary winding 18a of a transformer 18 and a resistor 17 is connected in parallel to the series circuit consisting of the second relay switch 8, the first J relay switch 6, and the diode 5. Further, a current transformer 25 is provided between the terminal 3 and the connection point of the second relay switch 8 on the line e3. An off-state detection circuit 16 is provided in association with the transformer 18 , and an on-state detection circuit 26 is provided in relation to the current transformer 25 .

In the off-time detection circuit 16, the secondary windings 18b of the transformer 18 [r, diodes 1' in mutually opposite directions], 20
are connected in parallel. Further, one end of the secondary winding 18b is connected to one input of the rectangular wave shaping circuit 21.

Further, at the other end of the secondary winding 18b, a terminal 22 is connected to a voltage dividing resistor 2.
Connected via 3.24. Furthermore, the other input of the rectangular wave shaping circuit 21 has a terminal 15 connected to a voltage dividing resistor 30.
connected via. Note that a supply voltage Vdd, which will be described later, is applied to the terminals 22 and 25. The output of the rectangular wave shaping circuit 21 is given to a differentiating circuit 95 consisting of an AND game 37 and an inversion circuit 32. A positive rectangular wave is derived from the differentiating circuit 95 as the off-state detection output. This output is output every positive or negative half cycle.

Further, in the on-time detection circuit 26, diodes 27 and 28 having mutually opposite directions are connected in parallel to the current transformer 25, respectively. One output end of current transformer 25 is connected to one input of rectangular wave shaping circuit 29 . A terminal 35 is connected to the other output end of the current transformer 25 via a voltage dividing resistor 37. 34.

Note that the supply voltage Vdd is applied to the terminals 35 and 36. The output of the rectangular wave shaping circuit 29 is the AN'D gate G.
38 and an inversion circuit 39. The differentiating circuit 96 outputs a clock pulse every positive or negative half period in response to a positive rectangular wave being derived as an on-time detection output.

The off-time detection output (hereinafter referred to as on-pulse) from the off-time detection circuit 16 is sent to the AND gate G2 via the differentiating circuit 95.
It is given to 4 and it is given to AND game goo 18. The on-state detection output (hereinafter referred to as off-pulse) from the on-state detection circuit 26 is applied to AND gates G34 and G35 via a differentiating circuit 96.

The command signal given to the input terminal 40 is transmitted through the diode 41
．． The signal is applied to a first noise removal circuit 45 via a diode 42, a resistor 43, and an inversion circuit 44 having a waveform shaping function. In the first noise removal circuit 45, the signal from the inverting circuit 44 is applied to one input terminal of an AND gate G29, and is passed through a first delay circuit 48 consisting of a resistor 46 and a capacitor 47 to the other input terminal of the AND gate G29. given at the end.

If the command signal applied to the input terminal 40 contains impulsive noise, there is a risk that it will be interpreted as an erroneous logical signal. The signal input to the @1 delay circuit 48 has a delay time ΔT
is derived from the first delay circuit 48 after l. Input terminal 40
When the signal applied to the signal is low level and includes high level impulsive noise, the high level impulsive noise is delayed by the delay time ΔTl. A
The output of the ND gate G29 is the logical product of both forces, and becomes low level by delaying the impulsive noise by the time ΔTl. Therefore, the first m f removal circuit 45 removes high-level impulsive noise.

The output of the AND gate G29 is input to the second noise removal circuit 71.

In the second noise removal circuit 71, the output from the AND gate G29 is given to one input terminal of the OR gate G28, and the other input terminal of the OR gate 628 via the second delay circuit 7o consisting of a resistor 72 and a capacitor 73. given to the terminal.

Assume that the command signal applied to the input terminal 40 includes high-level and low-level impulsive noise. This low-level impulsive noise is caused by the second delay time VjI! r7 (Delayed by l by delay time ΔT2. The output of OR gate 02B is the logical sum of the surface inputs, and therefore becomes a high level signal with low level impulsive noise removed. The output of OR gate G28 is OR gate, G27 (therefore OR gate), one input terminal of G27 receives low level and high level impulses (I[ft
- A logic signal that does not contain is provided. This OR gate G2
The output of 7 is applied to one input of AND gate G26, and is also applied to the other input of AND game 26 via a plurality of inverting circuits 92. AND gate G2
6 and the plurality of inverting circuits 92 constitute a differentiating circuit 93. Further, the output of OR gate G27 is applied via an inversion circuit 74 to one input of OR gate G25. The output of AND gate G26 is applied via monostable circuit 75 to the other input of OR gate G25. The output of OR gate G25 is applied to AND gate G23 via inverting circuit 76.

Terminal 77 is supplied with supply voltage VCC.

A series circuit consisting of a diode 78 and a resistor 79 is connected to this terminal 77, and this series circuit is connected to a capacitor 8.
Power supply terminal 1 of @1 relay drive circuit 61 via 0 (
10a. Also, a diode 1 is connected to the terminal 77.
01, resistor 102 and transistor TR13 are connected in series. Resistor 1()2 and transistor TR1a
A backup capacitor 104 is connected between them.

The collector of transistor TR13 is transistor TR1
Connected to 4 nohes. The collector of the transistor TR14 and the base of the transistor TR13 are connected to the emitter of the transistor TR13 via a resistor 1()5, and are grounded via a plurality of diodes 106.

The supply voltage Vdd is applied from the emitter of the transistor TR14.
is derived and given to the gate etc. Further, the emitter of the transistor TRl4 is grounded via a resistor 107 and a plurality of diodes 1()8. Furthermore, terminal 7
7, AND via resistor 109 and inverting circuit 110
It is connected to one input of the gate G30, and further connected to one input of the AND gate G30 via an inverting port Bit t. The output of AND Gamegoo 30 is A
Given to ND Gamegoo 4.

Resistor 1 connected to the emitter of transistor TR14
07 and a plurality of diodes 108, a resistor l12, a capacitor 113, a zener diode 114, and an inverting circuit 115 are connected in series to the connection point of the resistor 107 and the diode 108. The output of the inverting circuit 115 is applied to the OR gate G27 via the inverting circuit 116, the resistor 117, the diode 118, the Zener diode 119, and the inverting circuit 1211.

In addition, the output of the inverting circuit 115 is the inverting circuit 1211 resistor 1
22, the capacitor 123, the Zener diode 124, the inverting circuit 125, and the inverting circuit 126 to the AND gate G34, and also to one input of the AND gate G33. given to the other input. Note that the inverting circuit 127 and the AND game 33 constitute a differentiating circuit 128. The output of the inverting circuit 121 is applied to one input of an AND gate 636, and the output of the inverting circuit 125 is applied to the other input of the AND gate 36.

The output of AND gate G36 is given to AND gate G35.

The output of the differentiating circuit 128 is given to one input of an AND gate G32, and the output of the inverting circuit 81 is given to the other input of the AND gate G32.

The output of AND gate G32 is given to one input of OR gate G31, and the other input of OR gate G31 is given to A
The output of ND gate G35 is given. OR gate G3
The output of 1 is given to ORG13.

The output of AND gate G34 is applied to triAND gate G23 and also to AND gate G21.

The output of inverting circuit 76 is connected to AND gate G18. G19.
G23. G12. G3. Given to G4. The output of AND gate G23 is applied to one input of AND gate G14 and also to one input of OR gate G22. The output of OR gate G25 is the output of AND gate G
30°G24. G20. G21. Gll, given to G2. Output of AND gate G24 1dOR gate G22
AND gate G1
5 is applied to one input. The output of the OR gate G22 is a delay circuit FI! which is formed by connecting an inverting circuit 82 in series. r
It is applied to the inputs of AND gates G19 and G20 via 83. The outputs of AND gates G18 and G19 are reset to flip 70 and knob 84 via OR gate G16).
given to input R. AND Goo) G20. The output of G21 is applied to the set input S of seven lip-flops 84 via OR gate G17. The set output Q of the flip 70 knob 84 is given to the other input of the AND game 15, and the reset output Q of the flip 70 knob 84 is given to the other input of the AND game 14. AND gate G
14. Each output of G15 is given to an OR gate G13, and the output of the OR gate G13 is given to the other input of the if AND gate Gl.

The output of AND game l is ANDed through the delay circuit 85.
G12 is given to the other input of G12. AN
The output of the D gate GlO is given to one input of the OR gate GlO, and the output of the AND gate G12 is fed to the delay circuit 86.
1- to the other input of the OR GIO. The output of the OR gate GlO is given to a monostable circuit 87. The output of the monostable circuit 87 is connected to a plurality of inverting circuits 88 and N
It is applied to a monostable circuit F@90 via a differentiating circuit 89 consisting of an OR gamer 9 and to one input of an OR gamer G8. The other input VC of OR Gegu G8
is given the output of the monostable circuit 90.

The output of monostable circuit 9() is also connected to AND gate G2.6
given to 5. The output of OR Gegu G8 is the inverting circuit 81
AND Gamegoo 3. G4. G6
given to. AND gate G5. The output of G6 is given to OR Gegoo G7.

The operation will be explained with reference to FIG. AC power having a voltage waveform shown in FIG. 2(1) is supplied from the AC power supply 1 to the terminal 3. The waveform of the supply voltage Vcc supplied to terminal 77 is shown in FIG.
When the voltage Vcc reaches a constant voltage Vl, the supply voltage Vdd rises as shown in FIG. 2(3).

The output waveform of the capacitor 113 is shown in FIG. 2 (14),
Accordingly, the output of the inverting circuit 121 becomes as shown in FIG. 2 (5). In addition, the output waveform of the capacitor 123 is
The output of the inversion circuit 125 is shown in FIG. 2 (7) accordingly.

Therefore, the output of AND gate G36 becomes as shown in FIG. 2 (8). The output waveform of the capacitor 118 is shown in FIG. 2 (9), and the output of the inverting circuit 12 () is accordingly shown in FIG. 2 (10).

The waveform of the command signal given to terminal 4 () is shown in Figure 2 (++
), the output of the OR gate 628 is the second
Therefore, OR game) G2
The output of 7 becomes as shown in FIG. 2 (13). In addition, as the output of the inverting circuit 125 falls as shown in FIG. 2 (7), the AND gate G33 outputs +4
), a clock pulse An is issued.

Here, the first relay switch 6 becomes conductive as shown in Figure 9J2 (G), and the second relay switch 8 becomes conductive as shown in Figure 2 (A).
Assume that there is continuity as shown in .

When both relay switches 6.8 conduct, Fig. 2 (+5)
The load current flows as shown in FIG. 2 (off/<7L as shown in
/s is output. This off pulse RAND goo) G3
5 as shown in FIG. 2 (17). In response to the fall of the output of the OR gate G27 shown in FIG. 2 (13), a pulse with a pulse width W3 is derived from the monostable circuit 75 as shown in the second wheel. This pulse width W3 is set to cancel the chaku signal. A signal with a waveform shown in the second position is derived from the OR G25, and a signal with the waveform shown in the second position is thereby derived from the AND G23.
As shown in the figure (g), a tarok pulse corresponding to, for example, the third off-pulse is derived. This clock pulse is delayed by a time ΔT by a delay circuit 83 as shown in FIG.

On the other hand, when the first relay switch 6 and the second relay switch 8 are cut off, an ON pulse is derived from the AND game 37 as shown in FIG. As a result, the output power of the AND gate G24 becomes as shown in FIG.

The output of AND gate G19 is shown as OD in FIG.
The output of the D gate 18 is shown in FIG. 2, the output of the AND gate G20 is shown in FIG. 2 (b), and the output of the AND gate G21 is shown in FIG. 2 (to).

Ma7' (The output of OR Gegu G16 is shown in Fig. 2 q,
The output of ORGegoo G17 is shown in FIG. 2 (to).

In general, the blip 70 tube 840 set output Q is shown in FIG.

The delay circuit 85 receives the clock pulse from the AND gate G35 (as shown by 1) in FIG.
A by delaying the tarokk pulse from Gl by the time TI.
Give it to ND Gamer, G12. AND gate G1
The output from 2 is further delayed by a time T2 by a delay circuit 86, as shown in FIG. 2 (20). This time (TI+T2) Vi is the time to shift the off pulse to the timing at which the second relay switch 8 generates the relay control signal so that it is reset when the diode 5 is energized.

According to the output of OR gate G10, monostable circuit 87:
A pulse with a pulse width Wl is generated as shown in FIG. 2 (01). This pulse width Wl is used to set the difference in reset signal generation time of the first and %2 relay switches 6.8. In response to the pulse from the differentiating circuit 89, the monostable circuit 9() changes the pulse width W2 as shown in FIG.
generates a pulse. This pulse width W2 is! ! IJl
After the signal to set the relay switch 6 is generated, the second
This is for setting the time difference until the signal for setting the relay switch 8 is generated.

The output of the OR G8 is as shown in FIG. 2 (), and the output of the OR G8 is inverted by an inverting circuit 81 as shown in FIG. 2 (C). In this way, AN
The output of D game goo 3 is now shown as ) in Figure 2, the output of OR game goo G7 is now shown as ■ in Figure 2, and the output of AND gate G4 is as shown in Figure 2 θ The output of AND game 2 will be as shown in Figure 2.4. As a result, the first and second relay switches 6.8 are operated as shown in FIGS.

Referring to FIG. 3, first and second relay switches 6.
An explanation will be given of the operation when the supply voltage EEVCC is turned off due to a power outage during the off operation in the state where 8 is conductive and A is on. In this case, the waveform of AC power is shown in Figure 3 (l
The load current is shown in FIG. 3 (4), the operating state ratio of the first relay switch 6 is shown in FIG.
The U1 configuration of relay switch 8 is indicated by a cap in Figure 3.

The off pulse from AND game 38 is shown in Figure 3 (8)
It is indicated by. When the command signal applied to the terminal 40 at time t2 changes from the low level to the low level as shown in FIG.
Monostable times FI from Nr93! A clock pulse is applied to r75, whereby a pulse with a pulse width W3 is derived from the monostable circuit 75 as shown in FIG. 3(6). As a result, from the OR gate G25 to which the command signal and the output of the monostable circuit 75 are applied, a command signal with chatter canceled is obtained as shown in FIG. 3 (7). By ANDing the command signal shown in FIG. 3 (17) and the off pulse using the AND gate G21, the
From the R game) G17, a trigger pulse corresponding to the off pulse is given to the set force S of the 7 lip 70 knob 84 as shown in FIG. 3 (9), and therefore the 7 lip flop 84 is remains set as shown.

On the other hand, the output of the AND gate G23 to which the inverted signal of the output of the AND gate G25 and the off pulse are applied is shown in FIG.
The output of the AND gate G23 is delayed by a time .DELTA.T as shown in FIG. 3 (11) by the delay circuit 83. Here, the inverted signal of the output of the AND gate G25 and the output of the delay circuit 83 are given to the AND gate G19, and the reset power R of the flip-flop 84 corresponds to the output pulse of the delay circuit 83 L Tato! J Ka/<rus is given. Thereby, the flip 70 knob 84 is reset as shown in FIG. 3 (11).

The reset output Q and the off pulse of the flip-flop 84 are applied to an AND gate G14, and then the A
After the output of the ND game goo 25 becomes low level, the second off pulse is output from the AND gate G14 in Fig. 3 (13
) is derived as shown.

This off-pulse functions as an off-pulse for relay restraint operation. The off pulse from the AND gate 14 is sent to the delay circuit 8 via the OR gate G13 and the AND gate G1.
5 and is delayed by the time T1 in the delay circuit 85 as shown in FIG. 3 (14). Furthermore, AND gate G
1 is given the signal from the inverting circuit 81, therefore, only the off pulse from ANDG14 that appears when the monostable circuits 87 and 90 are not operating is sent to the delay circuit 8.
given to 5. The signal from the delay circuit 85 is as shown in FIG.
As shown in 15), the signal is further delayed by a time T in a delay circuit 86, and then provided to a monostable circuit 87. Accordingly, the monostable circuit 87 is pulsed as shown in FIG.
Outputs a pulse of 1ilWl. In response to the fall of the output of the monostable circuit 87, 11 monostable circuits 90 are activated.

In this state, the supply voltage Vcc is as shown in Fig. 3 (2).
Assume that the power supply is turned off due to a power outage at time t3 as shown in FIG. Due to the action of the backup capacitor 104, the circuit supply voltage Vdd does not drop suddenly as shown in FIG.
Derive the pulse of Therefore, the output of the AND gate G3 is set to a high level corresponding to the pulse width W2 as shown in FIG. 3 (17).
19). Here the supply voltage V
When cc is turned off, one input of AND gate G6 changes from low level to high level. Also AND
Since the OR output of the monostable circuit 87.90 is given to the other input of the gate G6, the output from the AND gate G6 via the OR gate G7 is as shown in FIG. 3 (08) from when the supply voltage Vcc is turned off. As shown, it is No Ireperu. At this time, the terminal 100 a of the first relay drive circuit 61
Since the power supply voltage is supplied by the function of VCLri and the capacitor 80, an excitation current flows through the relay coil 52 in the direction of the arrow 58, and the 11th J race switch 6 is reset.

Note that even if the supply voltage Vcc is turned off for a short time at time t1, the operation state at that time is maintained by the action of the backup capacitor 104.

Next, with reference to FIG. 4, an explanation will be given of the operation when the supply voltage Vcc is turned off due to a power failure while the first and second relays 8 are being turned on in a state where they are cut off. In FIG. 4, the waveform of the alternating current r1 is shown in FIG. 4ill, and the supply voltage Vcc is shown in FIG. 4(2),
The U+ operating state of the first and second relay switches 6°8 is shown in FIG. 4 (09) and FIG. 4 (Company). See you again F@
The waveform of the power supply voltage Vdd is shown in FIG.

The on-pulse from the AND game 37 is shown in FIG. 4 (6). Assume that the command signal changes to a high level at time t4 as shown in FIG. 4 (3) and includes chatter. Then, in response to the 21 pulses output from the differentiating circuit 93 in response to the first falling edge of the chatter, the monostable circuit 75 outputs a pulse with a pulse width W3 as shown in FIG. 4 (4). , Is that so? From OR gate G25, as shown in FIG. 4 (5),
A command signal with chatter canceled is obtained. From the AND gate G18 to the OR gate 61, the inverted signal of the command signal shown in this @4 diagram (5) and the ON pulse are applied.
6, a trigger pulse corresponding to the on-pulse is applied to the reset manual R of the flip-flop 84 as shown in FIG.
It continues to be reset as shown in Figure 4 (11).

On the other hand, the output I-i of the AND gate G25 to which the command signal and the ON pulse from the AND gate G25 are applied is as shown in FIG. 4 (8), and the AND gate G25
The output of is delayed by the time ΔT by the delay circuit 83 as shown in FIG. 4 (9). Here, AND gate G2
The output of 0 goes high in response to the output of the delay circuit 83 going high, and therefore the 7 lip-flop 84 is set as shown in FIG. 4(n).

The output of the AND gate G15 to which the set output Q of the flop flop 84 and the on-pulse are applied is shown in FIG.
As shown in O), at the second on-pulse after the command signal becomes high level, E> becomes high level,
It is derived as an on-pulse for relay control g operation via OR gate G13 and AND gate G1. This on-pulse is delayed by a time TI by the delay circuit 85 as shown by α in FIG.
From this, a pulse with a pulse width W1 is derived as shown in FIG. 4 (+3).

Assume that the supply voltage Vcc is turned off at time t5 while the monostable circuit 87 is in operation. Even after this supply voltage Vcc is turned off, the operation of the circuit is continued by the action of the backup capacitor 104. In the monostable circuit 90, the pulse width W changes as shown in FIG. 4 (14) in response to the fall of the output of the monostable circuit 87.
2 pulses are derived.

Here, in a normal state where the supply voltage Vcc is not turned off, the signal that should set the first relay switch 6 is AN
The set signal ij of the second relay switch 8 is obtained by the AND output of the output of the AND gate G25 via the D gate G30 and the OR output of the monostable circuit 87.90: AND
It is obtained by the AND output of the output of the gate G25 and the monostable circuit 90. However, when the supply voltage Vcc is turned off, the output of the AND gate G30 becomes low level.

Therefore @l relay switch 6 should be set IAND
The output of the game) becomes low level as shown in Figure 4 (07). On the other hand, one input of ANDG1-G6 has a monostable circuit 87. ! 110 is provided, and the other input is provided with an inverted signal of the supply voltage Vcc. Therefore, when the supply voltage Vcc is on, the output of the AND gate G6 is always at a low level. However, when the supply voltage Vcc is turned off, the other input becomes high level. Therefore, from the AND gate G6, as shown in the fourth row, in response to the output of the monostable circuit 90 becoming high level,
R game) A high level output is derived through G7, and the first
Relay switch 6 is reset. That is, when the supply voltage Vcc is turned off, the signal becomes a reset signal even though it is originally a set signal for the first relay switch 6.

As described above, according to this embodiment, the first on-pulse or A-off pulse is delayed by the time ΔT, and the delayed on-pulse or off-pulse causes the
When the lip flop is set or reset and the output of the clip 70 coincides with the on-pulse or off-pulse, the first and second relay drive circuits 61
．． Outputs a signal for driving 63. Therefore, the first and second relay switches 6.8 are activated by the second on-pulse or off-pulse, so that malfunctions due to undesigned on-pulse or off-pulse caused by momentary power outage can be avoided when the load power supply returns from a power outage. It is best to prevent it.

Note that by appropriately selecting the delay time, it is also possible to operate the first and second relay switches 6.8 by three or more plurality of on-pulses or off-pulses.

FIG. 5 is an overall circuit diagram of another embodiment of the present invention.
The same reference numerals are given to parts corresponding to the embodiments shown in FIGS. In this embodiment, two rectangular wave shaping circuits 131 and 132 are provided in the off-time detection circuit 130.

One end of the secondary winding 18b is connected to one input of one rectangular wave shaping circuit 131, and the voltage dividing resistor 13 is connected to the other input.
A divided voltage of 3,134 is given. The output of one rectangular wave shaping circuit 131 is output to a plurality of inverting circuits 135 and A
Ni) A through a differentiator circuit 136 consisting of G40
It is applied to one input of ND gate G41. One end of the secondary winding 18b is connected to one input of the other rectangular wave shaping circuit 132, and voltage dividing resistors 137, 13 are connected to the other input.
A divided voltage of 8 is given. The output of the other rectangular wave shaping circuit 132 is output from a differentiating circuit 140 consisting of a plurality of inverting circuits 139 and a NOR gate G42, and a monostable circuit 1.
50 to the other input of AND gate G41. The output of AND gate G41 is AND gate G24
given to.

In the on-time detection circuit 1i3141, two rectangular wave shaping circuits 142 and 143 are provided. One end of the current transformer 25 is connected to one input of one rectangular wave shaping circuit 142, and a divided voltage by voltage dividing resistors 144 and 145 is applied to the other input. The output of this rectangular wave shaping circuit 142 is applied to one input of an AND gate G44 via a differentiating circuit 147 consisting of a plurality of inversion circuits 146 and an AND gate G43. One end of the current transformer 25 is connected to one input of the other rectangular wave shaping circuit 143, and a voltage divided by resistors 148 and 149 is applied to the other input. The output of this rectangular wave shaping circuit W, 143 is transmitted to a plurality of inverting circuits 1
51 and NOR gate G45.
and is applied to the other input of AND gate G44 via monostable circuit 153. The output of AND gate G44 is output from AND gate G34. Given to G35.

Furthermore, in this embodiment, AND in the embodiment of FIG.
Gate G14. G15. G18. G19°G20. G2
1, OR Gut G16. G17. G22,
Delay circuit 83 and flip-flop 84 are omitted. The other configurations are the same as the embodiment shown in FIG.

The operation will be explained with reference to FIG. In this Fig. 6, the voltage waveform of AC power is shown in Fig. 6 ftl, the waveform of supply voltage Vcc is shown in Fig. 6 (2), and the waveform of supply voltage Vdd is shown in Fig. 6 (3). shown.

Further, the output of the inverting circuit 121 is shown in FIG. 6 (4), the output of the inverting circuit 125 is shown in FIG. 6 (5), the output of the inverting circuit 120 is shown in FIG. 6 (6), and the output of the inverting circuit 125 is shown in FIG. Gate G
The output Vi%6 of 33 is shown in Figure (7).

First of all! It is assumed that the jIJl relay switch 6 and the second relay switch 8 are cut off. Note that the 111 operation button of the first relay switch 6 is shown in FIG. 6 (c).
Operating state of second relay switch 8 #-j: m6 diagram (c)
It is indicated by fL. In this state, a signal synchronized with the load power supply is applied to one input of each of the two rectangular wave shaping circuits 131 and 132 in the off-time detection circuit 130, as shown by CD in FIG. Here, the voltage divided by the resistors 133 and 134 is set higher than the voltage divided by the resistors 137 and 138.

Therefore, one of the rectangular wave shaping circuits 131 outputs a pulse synchronized with the positive phase of the signal shown in FIG.
/''i Fig. 6 A pulse synchronized with the negative @ phase is output as shown in Fig. 966). An on-pulse is output in response to the rising edge of the pulse, and the pulse width W5 is output from the monostable circuit 150 in response to the falling edge of the signal from the rectangular wave shaping circuit 132, as shown in FIG.
A pulse is output. This pulse width W5 is set to be slightly larger than the time from the falling edge of the signal from the rectangular wave shaping circuit 132 to the rising edge of the signal from the rectangular wave shaping circuit 131. This determines whether the on-pulse is out of design. That is, the AND game 41 outputs an on-pulse corresponding to the second on-pulse, as shown in FIG. 6).

Here, it is assumed that the command signal applied to the terminal 40 becomes a low level and a high level at ``6'' as shown in FIG. 6 CD. Accordingly, the output value jJ of OR gate G29
tj: @ Figure 6).

Furthermore, even if the command signal contains chatter, the monostable circuit 75 cancels the chatter as shown in Figure 6), and the output of OR gate G25 is as shown in Figure 6. become. Therefore, a single ON pulse is output from the AND game 24 as shown in FIG.

In response to the on-pulse from the AND gate G24, the delay circuit 87 outputs a signal delayed by the time Tl as shown in FIG. The circuit 86 further delays the time T2.Furthermore, the monostable circuit 87 outputs a pulse with a pulse width W1 as shown in the sixth position, and the monostable circuit 90 outputs a pulse with a pulse width W2 as shown in FIG. The output is as shown in (19).Furthermore, the output of OR Gegu G8 is shown in Figure 6 (20
).

Therefore, the output l/-i of AND game 4 (
As shown in FIG.
It operates as shown in . Then, AND gate) G2 responds to the output of the monostable circuit 90 becoming high level.
As shown in FIG. 6(b), the level becomes high, and the second relay switch 8 is turned on and set as shown in FIG. 6(b).

When the first and second relay switches 6.8 conduct oil, a load current having a waveform as shown in FIG. 6(8) flows, and the two rectangular wave shaping circuits 142, A signal having a waveform shown in FIG. 6(9) is applied to one input of the circuit 143 in synchronization with the negative phase of the load current. Here, the voltage divided by resistors 144 and 145 is set to be larger than the voltage divided by resistors 148 and 149. Therefore, one rectangular wave shaping circuit 142 outputs a pulse synchronized with the positive phase of the signal in FIG. 6(9), as shown in FIG. 6(10), and the other rectangular wave shaping circuit 143 outputs a pulse synchronized with the positive phase of the signal in FIG. 1 Fig. 6 (as shown by +l Fig. 6 (9)
A pulse synchronized with the negative phase of the signal is output. As shown in FIG. 6 (I3), the differentiating circuit 147 outputs an off pulse corresponding to the rise of the pulse from the rectangular wave shaping circuit 142, and the monostable circuit w! l153 to il @
As shown in FIG. 6 (I2), a pulse with a pulse width W4 is output in response to the falling edge of the pulse from the rectangular wave shaping circuit 143. This pulse width W4tj:, rectangular wave shaping circuit 14
3 is selected to be slightly larger than the time from the falling edge of the pulse from the rectangular wave shaping circuit 142 to the rising edge of the pulse from the rectangular wave shaping circuit 142. This determines whether the off-pulse is out of design. That is, the AND gate G44 outputs an off pulse corresponding to the second off pulse as shown in FIG. 6 (14), and the AND gate G3
5 outputs Klotzbales as shown in FIG. 6 (15).

According to the command signal and the output of the AND gate G35, each circuit operates in the same manner as described above, and the output of the AND gate G3 becomes as shown in FIG. The result is as shown in Figure (c). In response, the first relay switch 6 is turned off as shown in FIG. 6(c), and the second relay switch 8 is turned off and reset as shown in FIG. 6(c).

In this embodiment, the first and second relay switches 6.8 are operated by the second on-pulse or off-pulse, so that malfunctions are prevented. Moreover, Figure 1~
Since no flip-flop is used as compared to the embodiment shown in FIG. 4, erroneous U+ operation due to noise can be prevented as much as possible.

As described above, according to the present invention, the @1 and second relay switches are activated by the coincidence of the plurality of ON/OFF pulses and the command signal 4I'1, so that the @1 and second relay switches are activated when the power is restored or when the power is turned on. Malfunctions are prevented from occurring.

[Brief explanation of drawings]

FIG. 1 is an overall circuit diagram of one embodiment of the present invention, and FIG.
A timing chart to explain the operation of the circuit shown in the figure,
FIG. 3 is a timing chart for explaining the operation when the supply voltage Vcc is turned off during the OFF operation, and FIG. 4 is a timing chart for explaining the operation when the supply voltage Vcc is turned OFF during the ON operation. FIG. 5 is an overall circuit diagram of another embodiment of the present invention, and FIG. 6 is a timing chart for explaining the circuit of FIG. 5. l...AC power supply, 2...load, 5...diode, 6...first relay switch, 8...second relay switch, 16.130...off detection circuit, 26. 1
41... ON detection circuit, 83... Delay circuit, 84
...Flip-prop, 150,153...Monostable circuit agent Patent attorney Kei Nishi part & 8 Sami Gagero & Karibura Tomomi a Tomomi a Tomomiji

Claims (1)

[Claims] Tl) Two first . The first relay switch is a second relay switch in which diodes are connected in series. turn on the relay switch, and after a delay turn on the second relay switch during the forward half period of the diode,
Furthermore, the OFF operation of the relay switch is such that the above voltage waveform turns off the second relay switch during the forward half cycle of the diode, and later turns off the first switch during the reverse half cycle of the diode. In a switch circuit, an ON switch detects an electrical change in a series circuit between an AC power source and a load when the first and second relay switches are OFF, and outputs an ON pulse every positive or negative half cycle. The first one constitutes a time detection circuit. It forms an off-time detection circuit that detects electrical changes in the series circuit between the AC power supply and the load when the second relay switch is on, and outputs an off-pulse every positive or negative half-sync. The output of the gate is delayed by a delay circuit when the on-pulse or the off-pulse matches, and the flip 70 knob is set or reset, and when the output of the flip 70 knob matches the on-pulse and the off-pulse, the first and second relay switches are activated. An AC switch circuit characterized by having a gate that outputs a signal for operation. (2) Two first load switching devices inserted in the series circuit of the AC power source and the load and connected in parallel to each other. The second relay switch is a second relay switch, and the ON operation of the first relay switch is such that the voltage waveform of the AC power supply is
Then, the first relay switch is turned on, and the second relay switch is turned on with a delay during the forward half period of the diode, and the off operation of the relay switch is such that the above voltage waveform is turned on during the forward half period of the diode. In the AC switch circuit which turns off the second relay switch and later turns off the relay switch 'Jl in a half cycle in the opposite direction of the diode, ifj, No. 1. Detects the electrical change in the series circuit between the AC power source and the load when the second relay switch is turned off, and f
fg l and one input of the second rectangular wave shaping circuit, and alternately generates signals from the first and second rectangular wave shaping circuits every positive and negative half cycle by comparison with the reference voltage applied to the other input. The off-time detection circuit is configured by providing a gate that derives a pulse between the two pulses, feeds one pulse to a time limit circuit that derives a pulse larger than the one between the two pulses, and outputs an on pulse when the output of the time limit circuit matches the other pulse. The first
, detects the electrical change in the series circuit between the AC power source and the load when the second relay switch is turned on, and switches the third and fourth relay switches.
pulses are alternately derived from the third and fourth rectangular wave shaping circuits every positive and negative half period by comparison with a reference voltage applied to the other input. , one pulse is given to another time limit circuit that derives a dog pulse from between the two pulses, and a gate is provided to output an off pulse when the output of the time limit circuit matches the other pulse, and an on-time detection circuit is constructed. An alternating current switch circuit comprising: a signal that causes the first and second relay switches to actuate U+ upon coincidence of the off-time detection circuit and the on-time detection circuit with a command signal.