JPS5914223A - Ac switch circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AC switch circuit interposed between an AC power source and a load to prevent arcing between contacts that open and close.

In the prior art, an input signal or an input inversion signal for turning the relay switch on or off, and an on pulse or an off pulse indicating that the relay switch is in a state where it can be turned on or off are input to an AND gate to control the relay. I'm getting a signal. However, if there is chatter in the human signal, the signal may become a reset signal instead of a set signal, or vice versa. When this happens, relays may malfunction, arcs may open and close, and diodes may be thermally destroyed.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned technical problems and provide an AC switch circuit that does not malfunction even if the input signal contains chatter.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is an electrical circuit diagram of an embodiment of the present invention.

AC power supply 1 and load 2 are connected to terminal 3 of this AC switch circuit.
, 4 in series. A series circuit consisting of a diode 5 and a first relay switch 6 connected in series with the diode 5 is connected between the lines 13 and 14 connected to the terminals 3.4. A second relay switch 7 is connected in parallel to this series circuit.

The first relay switch 6 is associated with the first latching relay 10. This first latching relay IO is a so-called single-winding latching relay, and has a relay coil 52. This relay coil 52 temporarily
When excited in the direction 7, the first relay switch 6 becomes conductive and mechanically maintains its conductive state. Further, when the relay coil 52 is temporarily excited in the opposite direction of the arrow 58, the first relay switch 6 is turned off and self-maintains in the off state.

A first relay drive circuit 61 is provided to drive the relay coil 52 of the first latching relay 10. In this 11th J-ray drive circuit 61, a transistor TR1 and a transistor TR serving as semiconductor switching elements are provided.
2 are connected in series, and their connection point 53 is connected to one terminal of the relay coil 52 of the first launching relay 10. Transistor TR3 and transistor TR4 are connected in series, and their connection point 54 is connected to the other terminal of relay coil 52. Zener diodes 59 and 60 are connected in series in opposite directions between the connection points 53 and 54 to prevent back electromotive force of the relay coil 52.

The output of AND game 5 is an inverting transistor TR5
and the aforementioned transistor T
Given to the base of R4. The collector of transistor TR5 is connected to the base of transistor TR1. AN
The output of the D gate G6 is applied to the base of the transistor TR5 and is also connected to the base of the transistor TR2. The collector of the transistor TR(3) is connected to the base of the transistor TR3.

When the output of AND game 5 becomes high level, transistors TR4 and TR5 become conductive, and transistor TRI becomes conductive. The output of AND gate G6 is at a low level, so transistors TR2 and TR5 are cut off. Therefore, transistor TR3 is cut off. In this way, a current path is formed that passes through the transistor TR1, the connection point 53, the relay coil 52, the connection point 54, and the transistor TR4, and a current flows through the relay coil 52 in the direction of the arrow 57. Therefore, the first relay switch 6 becomes conductive and self-maintained.

When the output from the AND game 6 becomes high level, the transistors TR2 and TR6 become conductive, and the transistor TR3 becomes conductive. The output of AND gate) G5 is low level, transistors TR4 and TR5 are cut off,
Transistor TRI is cut off. In this way, transistor TR3, connection point 54, relay coil 52, connection point 5
3 and transistor TR2, and an excitation current flows through relay coil 52 in the direction of arrow 58, which is the opposite direction to that described above. This causes the first relay switch to shut off and maintain itself.

The second latching relay 11 associated with the second relay switch 7 is also a single-winding latching relay like the first latching relay 10, and is provided with a second relay drive circuit 63 for driving the relay coil 62. It will be done. The second relay drive circuit 63 is configured similarly to the first relay drive circuit 61, and includes transistors TR7 to TR12 and Zener diodes 68 and 69, and includes a transistor TR10.
*The output of AND game 7 is given to the base of TR11, and the output of AND game 8 is given to the bases of transistors TR8 and TR12.

When the output of AND game 7 becomes high level, transistors TRl0. TRII becomes conductive and transistor TR
7 is conductive. The output of AND game 8 is at low level, so the transistors T 1N B , T
R12 is blocking. Therefore, transistor TR9 is cut off. Thus transistor TR7, connection point 6
4. A current path passing through the relay coil 62, the connection point 65 and the transistor TRIQ is formed, and the relay coil 62
A current flows in the direction of arrow 66. Therefore, the bacteria 2 relay switch 7 becomes conductive and is self-maintained.

When the output from the AND game 8 becomes high level, the transistors TR8 and TR12 become conductive, and the transistor TR9 becomes conductive. The output of AND game 7 is low level, and the transistor RITR10. TRII is cut off and transistor TR7 is cut off. In this way, transistor TR9, connection point 65, relay coil 62,
A current path is formed through connection point 64 and transistor TR8, and an excitation current flows through relay coil 62 in the direction of arrow 67, which is the opposite direction to that described above. As a result, the second relay switch 7 is cut off and self-maintained 0 When the current flowing through the relay coil 52 and 62 is cut off 1
Exceeding the supply voltage Vaa to the relay coil 52.62,
Zener diodes 59, 60, 68 .
69 is provided. Each terminal 100 is provided with a supply voltage Vac. Here Zener diodes 59, 60, 68
．． The breakdown voltage of 69 is a value exceeding the voltage of the supply voltage vCC and of the transistor TRI NTR1
2 is a value less than the voltage that causes breakdown.

When the outputs of the AND games 5 to G8 change from high level to low level, a counter electromotive force is generated in the relay coils 52 and 62. At this time, relay coil 52 - connection point 53 - Zener diode 59 - Zener diode 6
〇-Connection point 54-Relay coil 52, relay coil 62
- tlj Current flows in the reading point 64 - Zener diode 68 - Zener diode 69 - connection point 65 - relay coil 62 or vice versa, and the Zener diode 59,
60.68 and 69 break down. When the Zener diodes 59, 60, 68, and 69 break down, the back electromotive force is absorbed, and the transistors TR1 to TR12 are not destroyed.

In the off-time detection circuit 16, a series circuit consisting of a resistor 17 and a primary winding 18a of a transformer 18 is connected in parallel with the second relay switch 7. Transformer 18 secondary volume, 1
A capacitor 19 and a diode 20.21 are connected in parallel to ij18b.

One end of the secondary winding 118b is connected to one input of the rectangular wave shaping circuit 22. The other end of the secondary winding 1/iA 18 b is connected to the tangent point of the voltage dividing resistor 34.35. Further, the other input of the rectangular wave shaping circuit 22 is supplied with a voltage divided by voltage dividing resistors 36 and 37.

The positive rectangular pulse output from the rectangular wave shaping circuit 22 is derived as an off-time detection output every positive or negative half period. This crosspiece pulse at the time of OFF is A1. JD goo) is applied to one input of G9 and the inverting circuit 23
is applied to the other input of the AND game 9 via the .

Here, the inverting circuit 23 and A N ]'11 game) G9
The differential circuit 24 is tf) I+SF. The output of the differential circuit 24 is applied to one input of the AND gate G1 serving as the first gate.

A current transformer 25 is provided in the line 13 between the terminal 3 and the connection point of the first relay switch 6, which is connected so that the terminal (and the secondary are opposite poles 1 and 1). This current transformer 25
The output is input to the ON detection circuit 126. The off-state detection circuit 26 includes a capacitor 27, diodes 28, 29, and a square wave shaping circuit 30, similar to the above-described off-state detection circuit 16. One terminal of the current transformer 25 is connected to one power source of the square wave shaping circuit 30. The other terminal of current transformer 25 is connected to the connection point of voltage dividing resistors 39 and 40. In addition, the voltage dividing resistor 41 is connected to the other side of the rectangular wave shaping circuit 30.
A voltage divided by 42 is applied. ON detection circuit 2
The positive pulse from 6 is applied to a rising differential circuit 33 consisting of an inverting circuit 31 and an AND gate G10. The 111 power of the rising differential circuit 33 is given to one power of the AND gate G2 as the second gate. Note that the positive pulse from the on-time horizontal 111 circuit 26 is output every 1F or the negative half period as an on-time detection output.

A signal from input terminal 76 via signal control circuit 77 is applied to the other input of AND gate G1 and AND gate G2, respectively. An ON operation signal or an OFF operation signal is input to this input terminal 76.

(In the M quantity control circuit 77, the signal 5 from the terminal 76 is passed through diodes 78, 79, a resistor 80, a capacitor 81, and an inverting circuit 82 having a waveform shaping function to one input of the AND gate G12 and to the NOR gate G12. It is applied to one input, and is further passed through an inverting circuit 83 to AND gate)Gll and NOR gate)G12.
is given to each other input. The AND game and the inverting circuit 83 constitute a rising differential circuit 84, and the NO
The R game 12 and the inversion circuit 83 constitute a falling differentiation circuit 85. The outputs of the rising differential circuit 84 and the falling differential circuit 85 are applied via a monostable circuit 86 to one input of the OR gate G13. Also OR Age
The output of the inverting circuit 83 is given to the other human power of G13. The output of OR gate G13 is AN, D) Gl, G
3. G7°G5, and is applied to AND gate G2.G5 via an inverting circuit 87. G4. G8. Given to G6.

Each output of AND game l, ()2 is OR gate G16
The signal is applied to the first delay circuit D Ll via.

The output of this first delay circuit D TJ 1 is given to one input of AND gate G3 and AND gate G4. Further, the other input of the AND gate G3 is supplied with a signal from the OR gate G13 as described above, and the output of the inverting circuit 87 is supplied to the other input of the AND gate G4.

The output of the AND gate G3 is given to the OR gate (115) and also to the monostable circuit 4 via the OR gate G14.
given to 3. Further, the output of the AND gate G4 is applied to the second delay circuit DL2, and the output of the second delay M path DL2 is applied to the OR gate G15 and also to the monostable circuit 43 via the OR gate G14. The output of the monostable circuit 43 is applied to AND gates G6 and G7 and also to an inversion circuit 44. Inversion circuit 44
The output of
D Gamegoo 5, given to G8.

The output of the differential circuit 48 is applied to a monostable circuit 46 via an OR gate G15. The output of the monostable circuit 46 is an AND gate ()5, G6, G7.

Each is given to G8.

The operation will be explained with reference to FIG. AC' having the voltage waveform shown in FIG. 2 (1) from the AC power supply 1 to the terminal 3.
Gravity is supplied. When the first and second relay switches 6.7 are cut off, an induced voltage is generated in the secondary winding Hl 8b of the transformer 18 at each cycle of the voltage waveform.
An off-time detection signal is derived from the rectangular wave shaping circuit 22.

In response to the rise of this OFF detection signal, a clock pulse (
Thereafter, on-pulse and IIIP) are derived.

In this state, the signal applied to the input terminal 76 becomes chatter t4 at time t1 as shown in FIG. 2(3).
Suppose that it goes from low level to high level. A clock pulse is derived from the rising differential circuit 84 and the falling differential circuit 85- in synchronization with the rising and falling G of the input signal, and is applied to the monostable circuit 86. In response to the input of this clock pulse, the monostable circuit 86 outputs a pulse 1lli as shown in FIG. 2 (4).
A pulse of W3 is derived. This pulse width W3 is
It is selected to be longer than the operating time of the relay. Since the output of the monostable circuit 86 and the human input signal are input to the OR gate G13, an input negative sign with chatter canceled is output from the OR gate G13 as shown in FIG. 2 (5). . Therefore, the AND game group is shown in Figure 2 (6
), a single on-pulse is output.

The on-pulse is applied to the first delay circuit DLI via the OR gate 016. In the first delay circuit DL1, since the on-pulse is ahead of the load voltage in phase, the on-pulse is delayed by a delay time T1 corresponding to the phase shift time T1 for synchronizing with the positive phase of the load voltage. 2
The output shown in Figure (7) is derived. Note that the phase shift time Tl of the on-pulse is shorter than the phase shift time of the off-pulse, which will be described later.

The output of the first delay circuit DLI is given to the monostable circuit 43 via the AND gate 3. The monostable circuit 43
A pulse with a pulse width Wl is derived as shown in Figure (8). This pulse width W1 is selected to be the time from when the first relay switch 6 is turned on until the second relay switch 7 is turned off, that is, 1/2 cycle of the AC voltage.

The output of the monostable circuit 43 is outputted by the inverting circuit 44 as shown in FIG.
9), and when the inverted signal rises, a clock pulse is applied to the monostable circuit 46. In addition, the monostable circuit 46 includes an AND game 3
The output from the monostable circuit 46 passes through an OR gate G15 to generate two clock pulses separated by a time W1.
given to.

In response to the input of the two clock pulses X Htl, the monostable circuit 46 outputs a pulse lI'NI W 2 for 1h0 as shown in FIG. Note that the pulse rtjw W
2 is selected to be greater than the operating time of the first and second relay switches 6.7.

As described above, the output of the AND game 5 first responds to the first positive pulse from the monostable circuit 46 and becomes a NO level as shown in FIG. 2 (11). As a result, a current flows through the relay coil 52 in the direction of the arrow 57, and the first relay switch 6 turns on during the negative phase of the load voltage, that is, the half cycle in the opposite direction of the diode 5. and is set.

Then, in response to the second positive pulse from the monostable circuit 46, the output of the AND game 7 becomes high level as shown in FIG. The current flows in the 66th direction, and the 219th (1
4), the second relay suite F7 is set by turning on during the positive phase of the load voltage, that is, the half cycle of the diode 5 in the direction.

By the above-described operation, the load 2 can be energized without generating an arc.

As described above, in response to power activation, a load current as shown in FIG. 2 00 flows. Note that the portion indicated by diagonal lines in FIG. 200 flows to the diode 5. This load current is ``a<S''#18 a current of the transformer 18,
Therefore, no electromotive force is generated in the secondary winding 118b. The output generated by the current transformer 25 is input to a rectangular wave shaping circuit 30. In response to the rectangular wave from the rectangular wave shaping circuit 30, the rising differential circuit 33 outputs a clock pulse (hereinafter referred to as sub-pulse) shown in FIG.
A N D goo) is input to one side of G2.

Assume that at time t2 in such a state, the human input signal to the input terminal 76 changes from a high level to a low level with chatter as shown in 2'A (3). At the falling and rising edges of this input signal, clock pulses are applied from the falling differentiation circuit 85 and the rising differentiation circuit 84 to the monostable circuit 86. As a result, the monostable circuit 86 outputs a pulse having a pulse width W3 as shown in FIG. 2(4). The output and input signals of this monostable circuit 86 are sent through an OR gate G13 to cancel chatter as shown in FIG. Therefore, a single off pulse is output from the AND gate G2 as shown in FIG. 2 (08).

The off-pulse is given to the first delay circuit DLl, and the second
As shown in 14(7), at the time of delay, IUj T is delayed. Here, it is assumed that the off-pulse has a phase that is ahead of the negative phase of the load current by a time period (Tl-1-T2). Therefore, in the first delay circuit DLl, the phase of the off pulse is shifted by the time TI out of the phase shift time (TI+T, 2) of the off pulse. This delayed off-pulse is A
ND game goo 3. Given to G4. Here, the input signal is at a low level and the output of the inverting circuit 87 is at a high level as shown by 0η in FIG. given to.

In the second delay circuit DI2, the off-pulse is delayed by the remaining time T out of the off-pulse phase shift time (T I +T 2 ) as shown by the dotted line in FIG. The signal is applied to the monostable circuit 43 via the gate G15, and is also applied to the monostable circuit 46 via the OR gate G15.

The monostable circuit 43 inputs the off-pulse by 1+'2i to obtain the pulse width W1 such that Pis 21m (8) and /l<.
The monostable circuit 46 outputs two pulses of pulse 1fli+i W 2 as shown in FIG.

Therefore, the output of G7 (first A, N D goo) is the second
As shown in FIG. 4, the level becomes high, and a current flows in the direction of arrow 67 in the relay coil 62. Thereby,
When the second relay switch 7 is in the positive phase of the load current, that is, in the forward half period of the diode 5, the 21st JQ4)
It turns off and is reset as shown in .

Then, the output of the A N D gate G6 is as shown in FIG. 2 (121).
As shown, the level becomes high, and a current flows in the relay coil 52 in the direction of the arrow 58. As a result, the 11th J race switch 6 is turned off and reset in the negative phase of the load current, that is, in the reverse half cycle of the diode 5, as shown by 21ffl (1:l).

By the above-described operation, it is possible to de-energize the load 2 without generating an arc.

In the above embodiment, the phase shift time of the on-pulse is set to T1 and the phase shift time of the off-pulse is set to (T1+T2), or as another embodiment of the present invention, the phase shift time of the on-pulse is set to (Tl+T2).
2), and the off-pulse phase shift time may be set as Tl.

In this case, an input inverted signal is given to the AND gate 3,
A human signal may be given to the AND gate 4.

FIG. 3 is an overall circuit diagram of another embodiment of the present invention.
Parts corresponding to the illustrated embodiments are designated by the same reference numerals. In this embodiment, the outputs of the rising edge differential circuit 84 and the falling differential circuit 85 are applied to the set input of the 17th lip flop 90.

Also, the outputs of the metastable circuit 43 and monostable circuit 46 are OR
It is applied to a falling differentiation circuit 92 consisting of an inverting circuit 91 and a NOR gate G19 through an AGE-018.
The output of this differentiating circuit 92 is the 17th lip flop 9().
is given to the reset human power R. The set output Q of the 17th lip-flop 90 is applied to one input of the A N ]) gate G20, and the set output q of the 27th lip-flop 93 is applied to the other input of the AND gate G20. Also, the set output Q of the first flip-flop 90 is A
Also given to one input of ND gate G21, this AN
The reset output enable of the 27th lip-flop 93 is applied to the other input of the D game 21.

The output of AND gate G20 is AND gate G2゜G4
,06. G8, and a falling 1j distribution circuit 9 consisting of an inverting circuit 94 and a NOR gate 22.
5, and the output of this falling differentiation circuit 95 is given to the second
7 is given to the reset manual power R of the lip-flop 93.

The output of AND gate G21 is AND gate G3
．． G5. G7 and also to a falling differentiation circuit 97 comprising an inverting circuit 96 and a NOR gate G23, and the output of this falling differentiation circuit 97 is given to the set input S of the 27th lip-flop 93.

The operation will be explained with reference to FIG. The waveform of AC power is shown in FIG. 4 (1). When the first and second relay switches 6.7 are cut off, an on-pulse synchronized with the AC voltage is derived from the off-time detection circuit 16 as shown in FIG. 4(2). At this time, the input signal given to the terminal 76 at time t3 becomes chatter, as shown by the fourth mark (3).
Suppose that it goes from low level to high level including . In response to this input signal, the clock pulse shown in FIG. 4(4) is derived from the rising differentiation circuit 84 and the falling differentiation circuit 85. Therefore, the first flip-flop 9° is set by the first clock pulse, and the set output Q
becomes high level as shown in FIG. 4 (5). At this time, the set output Q of the 27th lip-flop 93 is at a low level as shown in FIG. 4 (6), while the reset output Q of the 27th lip-flop 93 is at a high level as shown in FIG. 4 (7). be.

Therefore, the output of the AND game 21 is at a high level as shown in FIG.
is canceled. As a result, a single on-pulse is output from the AND game l as shown in FIG. 4 (9).

In response to the single on-pulse, the clock pulse shown in FIG. It will be shown as follows. Further, the 41 stable circuit 43 outputs a pulse with a pulse width W 1 as shown by 0 in FIG. 4, which is inverted by the inverting circuit 44 as shown in Figure 4 (as shown by the shell), the pulse +i + HW 2 is output twice, and the output of the OR gate 018 becomes as shown in Figure 4 00. Also, in response to the fall of the output of the OR gate 018 From the falling differential circuit 'ff192, Qf in Figure 4
A clock pulse indicated by 9 is outputted, and at the same time as F6, the 17th lip flop 90 is reset as shown in FIG. 4(5).

On the other hand, the first pulse from the sheep stabilizing circuit 46 causes the output of the AND game 5 to go to a high level as shown at 0η in FIG. do. Then, a second pulse from the monostable circuit 46 causes AND game 7
The output becomes high level as shown by 0 in FIG. 4, and the second relay switch 7 is turned on as shown by K> in FIG.

Incidentally, when the set output Q of the first flip-flop 90 becomes a low level, the output of the AND gate 21 also becomes a low level as shown in FIG. 4(8). In response to the fall of the output of the AND game 21, a high-level trigger pulse is input to the set input S of the second flip-flop 93, and in response, the 27th flip-flop 93 is set and the set output Q is set to 4. The level becomes high as shown in (6). Therefore, the ml flip-flop 90 is set in response to the input signal going low, and is reset after the relay operation is completed.

When the first and second relay switches 6.7 conduct, a load current with the waveform shown in Figure 4 (01) flows, and an off pulse is output in synchronization with the load current as shown in Figure 4 (A). . At this time, it is assumed that the input signal becomes low level with chatter as shown in FIG. 4(3) at time t4. At the rising and falling edges of the chatter, a clock pulse is applied to the setting input S of the 17th lip-flop 90, and the 17th lip-flop 90 is set as shown by the 41st ffl(5). AND gate G to which the set output Q of the first flip-flop 90 and the set output Q of the second flip-flop 93 are applied.
20 becomes high level in response to the setting of the first flip-flop 90 as shown in FIG.
A single off pulse is output as shown at 3. This off-pulse is applied to the fourth [ff1O (delay circuit I as shown by e).
II, l delayed by time TI and correspondingly AND
The game controller 4 outputs an off pulse shown in FIG. 5 This off-pulse is delayed by a time T2, as shown in FIG. 4) with a delay 11n1MDL2.

In response to the output from the delay circuit DL2, the monostable circuit 43.
The outputs of 46 are as shown in FIG. 400, FIG.

Therefore, first, the second relay switch 7 is
The first relay switch 6 is turned off as shown in .
is turned off as shown by the fourth negative part.

In this embodiment, the input signal will not be longer than it actually is, as in the embodiments of FIGS. 1 and 2, and therefore the operation will not be delayed.

FIG. 5 is an overall circuit diagram of another embodiment of the present invention, and parts corresponding to each of the embodiments described above are given the same reference numerals. In this embodiment, the output of the inversion circuit 82 is provided to the first noise removal circuit 100. In this first noise removal circuit 100, the signal from the inversion circuit 82 is connected to the AND gate G25.
is applied to one input of the AN
It is given to the other human power of D game goo 25. Also fg
l The output of the noise removal circuit 100 is the second noise removal circuit 1? ,
104. In this second noise removal circuit 104, the output of the AND gate G25 is given to one input of an OR gate 026, and is also given to the other input of the OR gate 026 via a delay circuit 107 consisting of a resistor 105 and a capacitor 106. . The output of the second carton noise removal circuit 104 is applied to one input of the AND game 2, and is also applied via the inverting circuit 108 to one input of the AND'D gate G1 and one input of the OR gate.

Note that the primary and secondary current transformer 25 are not reversed in polarity, and the output of the rectangular wave shaping circuit 30 is the polarity reversal circuit 1 of the current transformer 25.
09 and a NOR gate 028, it is applied to the input of the other power of the AND game G2 via a falling differentiation circuit 110 consisting of a NOR gate 028. Also, the 111 force of the square wave forming circuit 1'i+ 22 is the inverting circuit 111 of the complex (and the AND game 29
A and ND are applied to the other inputs of Gl through a rising differential circuit 112 consisting of the following.

The AND gate Ql(7) output is applied to one input of OR gate G16 and also to monostable circuit 113. The output of AND game 2 is given to the other input of OR gate G16. OR game) G16 output is AN
It is applied to one input of D gate G24, and the output of A'HD gate G24 is applied to monostable circuit 115. The output of the monostable circuit 113 is given to the other input of the OR gate G27, and is also connected to the NAND gate via the inverting circuit 114.
K) G is given to one input of 30. This NA
The output of OR gate G32 is applied to the other input of ND gate G30. The output of the OR gate G27 is given to one input of the AND gate G
The output of the NAND game 0 is given to the other input of 31.

The output of monostable circuit 115 is connected to inverting circuit 116 and NO.
It is applied to a falling differentiation circuit 117 consisting of an R game 33 and also to an OR gate G32. AND
The output of the game goo 31 is ANDed through the inverting circuit 118.
It is applied to one side of gate G34, and is directly applied to one input of AND gate G35. AN'D Game) Goo 4゜35 Falling differentiation circuit 1 is used as input for other force.
17 outputs are provided respectively. Also, the inversion circuit 118
The output of is given to AND game 5 and G7.

The output of AND gate G34 is applied to a monostable circuit 119, and the output of this monostable circuit 119 is applied to OR gate G32 and also to a falling differentiation circuit 121 consisting of an inversion circuit 120 and a NOR gate 26. The output of this falling differentiation circuit 121 is OR Age-G3
7, and the output of the A iJ D gate G35 is applied to the other input of the OR Age-G37.

The output of OR gate G37 is given to monostable circuit 43. The output of this monostable circuit 43 is a falling differential circuit 123 consisting of an inverting circuit 122 and a NOR group 038.
is applied to the monostable circuit through the gate, and also directly to one input of OR gate G39. monostable circuit 46
The output of is given to AND game 6 and G7, and also given to input 11 of OR game G39.

The output of OR gate G39 is applied to OR gate G32, AND gate 5 and G8, and is further applied to the other input of AND gate 24 via inverting circuit 124. Note that the output of the AND gate G31 is also given to AND gates 5 and G7.

The operation will be explained with reference to FIG. When the first and second relay switches 6.7 are off, the rising differential circuit 112 outputs an on-pulse synchronized with the AC power having the waveform 61d(1) as shown in FIG. 6(2). Output. In this state, it is assumed that the input signal applied to the terminal 76 changes from a low level to a high level with chatter at time t5, as shown by the sixth [J(3)]. The AND game G1 to which this input signal and the on-pulse are applied outputs an on-pulse as shown in FIG.
6 to one input of the A'ND gate G24. The monostable circuit 113 outputs a pulse having a pulse width W4 as shown in FIG. 6(5). From the OR gate G27 to which this pulse and a signal obtained by inverting the input signal by the inverting circuit 108 are applied, a signal in which chatter within the pulse width W4 is canceled is obtained as shown in FIG. 600.

A N D goo) Monostable circuit 4 is connected to the other input of G24.
3.46 inverted signal is given, monostable circuit 4
3.46 is not operating, so the inverted signal is at a high level. Therefore, from AND gate G24, AN
An on-pulse is output from the D gamer 1, and a pulse with a pulse width W5 is output from the monostable circuit 115 as shown in FIG. 6 (6). This pulse O'lil W 5 is
This is to generate an on-pulse so that the first relay switch 6 is turned on when the diode 5 is reverse biased.

At the end of this output, the falling differentiation circuit 117 outputs an on pulse.

The AND gate 31 is supplied with the output of the OR gate G27 and the output of the NAND gate G30, shown as 01# in FIG. Here, if W4>W5+wl+w2, then N
The output of AHD gate G30 remains at high level as shown in FIG. 6 (4). Therefore, AND gate G
From 31, an input signal with chatter canceled is derived as shown in FIG. 6 (11). This input signal and the output of the differentiating circuit 117 are given to the monostable circuit 43 via an AND gate G35 and an OR gate G37, and the monostable circuit 43 outputs a pulse width Wl as shown in FIG. 6 (7). pulses are derived. This monostable circuit 43
In response to the fall of the output, the monostable circuit 46 outputs a pulse 1lf14W2 as shown in FIG. 6(9). Furthermore, from OR gate G39, as shown in FIG.
As shown in 9), a pulse with a pulse width (W1+W2) is output. In this way, the output of the AND game 5 becomes high level as shown at 0'4 in FIG. 6, and the first relay switch 6 is turned on as shown in FIG. 6(A).

Then, the output of AND game 7 is the 6th II (L,'
It becomes high level as shown by l, and it reaches the end of 2.

- The switch 7 is turned on as shown in FIG. 6. When the first and second relay switches 6.7 are turned on, the load 't+1fft flows as shown in FIG. 6 0→.

In response, the falling differentiation circuit 110 outputs an off pulse as shown at 0 in FIG. At this time, the time is 6
Assume that the input signal has chatter and changes from high level to low level. This input signal and off pulse are A
By being applied to the ND gate 2, an off pulse is output from the AND gate 2 as shown in QQ in FIG. 6, and is applied to the AND gate G24. Inversion circuit 12
4 is at a high level, the off-pulse is given to the monostable circuit 11'5, and the output of the monostable circuit 115 becomes as shown in FIG. 6 (6). OR Age-G32
The output of the monostable circuit 115 goes high as shown in FIG. 6 (08), and the output of the inverting circuit 114 goes high as shown in FIG. 6 (01). Therefore, the output of the NAND gate G30 is at a low level while the output of the OR gate G32 is at a high level, as shown by the sixth negative end. Therefore, chatter
As soon as the monostable circuit 113 starts operating, the input signal containing the input signal becomes low level as shown in FIG. 6 (01).

As a result, the chatter after 1 is caused by the OR gate G32.
is canceled when the output is at high level, that is, when the relay is operating.

In this way, the output of AND game 8 is
), and the second relay switch 7 is turned off as shown in FIG. Then A
The output of the ND game goo 6 becomes high level as shown in FIG. 6 (@), and the first relay switch 6 turns off as shown in FIG. 6 (c).

According to this embodiment, the input signal is not extended for a long time to cancel chatter, and the operation is not delayed.

As described above, according to the present invention, even if the input signal contains chatter, the chatter is canceled, so malfunctions are prevented and the diode is not damaged by heat.

[Brief explanation of the drawing]

FIG. 1 is an overall circuit diagram of one embodiment of the present invention, and FIG.
A timing chart to explain the operation of the circuit shown in the figure,
FIG. 3 is an overall circuit diagram of another embodiment of the present invention, FIG. 4 is a timing chart for explaining the operation of the circuit in FIG. 3, and FIG. 5 is an overall circuit diagram of another embodiment of the invention. , FIG. 6 is a timing chart for explaining the operation of the circuit shown in FIG. 5. 0 1... AC power supply, 2... Load, 5... Diode, 610. 1st relay switch, 7... 2nd relay switch, 16... OFF detection circuit, 26... ON detection circuit, 76... Input terminal, 84... Rise differential circuit, 85...・Falling i differential circuit, 86...monostable circuit, 90...17th lip-flop, 93...
・27th Lip Flop, 113... Monostable circuit agent Patent attorney Kei Nishi

Claims (4)

[Claims] (1) Two first and second relay switches for switching loads inserted in a series circuit of an AC power source and a load and connected in parallel to each other, the first relay switch having a diode connected in series. The ON operation of the relay switch is such that the voltage waveform of the AC power supply turns on the first relay switch during the half cycle in the reverse direction of the diode, and after a delay turns on the second relay switch during the half cycle in the forward direction of the diode. Furthermore, the off-operation of the relay switch is such that the voltage waveform turns off the second relay switch during the forward half-cycle of the diode, and later turns off the first switch during the reverse half-cycle of the diode. In the circuit, a pulse generating means is provided which continuously generates a pulse longer than the operating time of the relay in response to a change in the level of an input signal for turning the load on or off, and the output of the pulse generating means is
The on-pulse or the first on-pulse is outputted from the off-time detection circuit every positive or negative half period by detecting the electrical change in the series circuit of the AC power source and the load when the first relay switch of 642 is off. , detects the electrical change in the series circuit when the second relay switch is turned on, and outputs an off pulse from the on-time detection circuit every positive or negative half cycle, and the first and second relay switches An AC switch circuit characterized in that it creates a control signal for a circuit that drives the AC switch circuit. (2) The pulse generating means includes a rising differential circuit that generates a pulse in response to a rising edge of a human input signal, and a falling differential circuit that generates a pulse in response to a falling edge of an input signal, and the outputs of both differential circuits are 2. The alternating current switch circuit according to claim 1, further comprising a monostable circuit that generates a pulse longer than the relay operation time in response to the relay operation time. (3) The pulse generating means includes a rising differential circuit that generates a pulse in response to a rising edge of an input signal, a falling differential circuit that generates a pulse in response to a falling edge of an input signal, and is set by the outputs of both differential circuits. the 17th lip flop, the 27th lip 70 knob, and the 1st lip flop. A gate for outputting a signal for turning off the first and second relay switches and resetting the 27th lip-flop when the set outputs of the 27th lip-flop match, and a set output for the 17th lip-flop and a reset output for the 27th lip-flop. and a gate for outputting a signal for turning on the first and second relay switches and for setting a twenty-seventh lip-flop in response to a coincidence of the two relay switches. . (4) The pulse generating means includes a monostable circuit that generates a pulse longer than the relay operation time in accordance with the output from the gate that is output when the ON pulse matches the input signal for the ON operation, and the monostable circuit The OR output of the output of the gate and the input signal for the on operation is used as a relay control signal for the on operation, and the signal output from the gate when the input signal for the off operation matches the off pulse is used as the relay control signal for the off operation. An alternating current switch circuit according to item 1 of the Patent Mf & Claims, characterized in that the relay control signal is a relay control signal.