JPS60100326A - Ac switch circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

TECHNICAL FIELD The present invention relates to an AC switch circuit that detects the phase of an AC power source and operates a relay switch at a preset phase.

BACKGROUND ART A conventional AC switch circuit has an input terminal that provides an input signal to turn the relay switch on and off with no arc opening and closing under load, and a reset terminal that forcibly turns off the relay switch with no arc opening and closing under no load. It has a reset terminal that provides a signal, and a setting terminal that provides a signal that causes the initial state of the relay switch to be set or reset without arcing when the power supply VCC is turned on from off.

In order to perform such an operation, the aforementioned eight terminals are required, which is inconvenient in use.

OBJECT An object of the present invention is to solve the above-mentioned technical problems and provide an AC switch circuit that can perform the above-mentioned operations with one input signal.

Embodiment FIG. 1 is an electrical circuit diagram of an embodiment of the present invention. Second
The operation of this electric circuit under load will be explained with reference to the timing chart shown in the figure. relay switch a1 and a
At the point A' of the line 11 from the winding 4 of the transformer 1 when 2 is off, the signal IA shown in FIG. 2 (2), which is synchronized with the AC power supply voltage EO shown in FIG. 2 (1), is obtained. . transformer 1
The core 3a includes a primary winding 3, a secondary winding 2, and a tertiary winding 4.
This signal A is applied to the inverting input terminal 5' of the comparator 5. The comparator 5 compares the signal A with the voltage level applied to the non-inverting input terminal 5', and the signal A is amplified by an amplifier circuit including a transistor Tr3. At the connection point between resistor R12 and resistor R13, signal B shown in FIG. 2 (3) is connected.
is sent. When obtaining this rectangular wave signal B, the comparator 5
The threshold value changes depending on the output of the comparator 5, and α of the signal A
In a case like the above, the signal B, which would prevent the output of the comparator 5 from changing, is ANDed with the NOT gate 6 of the odd stage
A circuit that generates a pulse at the rising edge of a rectangular wave consisting of a gate 7, and a circuit that generates a pulse at the falling edge of a rectangular wave consisting of odd-numbered NOT gates 6 and NOR gates 8. From the output terminal of AND gate 7,
) is sent out, and the output terminal of the NOa gate 8 sends out a signal C shown in FIG. 2 (8). These signals C and D are pulse signals synchronized with the zero cross of the AC power supply voltage EO.

In this state, the signal S1 shown in FIG. 2 (9) applied to the interface La1li+9 changes from low level to high level. If this signal S1 contains chatter as shown in FIG. 2 (9), the Schmitt circuit I
By passing through O, a chatter-free waveform like the signal E shown in FIG. 2 QO is obtained. This signal E passes through the Schmitt circuit 11 and becomes a signal F delayed by a time W4. EX
The -0 gate 12 outputs the signal G shown in FIG. 2(2) as an output by the exclusive OR of the signal E and the signal F. The time W4 of the high level M of this signal G is the AC power supply'
The time for determining whether there is a load LO following the voltage EO and the number of times the relay drive signal is repeatedly generated are determined. AND of this signal G and signals C and D
The presence or absence of the load is determined by taking the value. Power supply voltage v
When the CC is on, the output of the Schmitt circuit 14 is always at a high level, so the pulse signal H synchronized with the zero cross of the load power supply voltage EO from negative to positive is generated by ANDing the signal C and the signal G as shown in FIG. AND gate 1 as shown in 13
Sent from 5. The output of the Schmitt circuit 16 and the output of the Schmitt circuit 14 are applied to an EX, -, OR gate 17. Since the output of the EX, -OR gate 17 can only be obtained when the power supply voltage VCC is turned on or turned off, the output of the AND gate 16 is not always sent out.

The signal H shown in FIG.
An error is applied to the one-shot circuit 20 via the OR gate 19. In the one-shot circuit 20, relay switch a1
．． Considering the on-operation time of a2, the V-switch a1
When the diode DO is cut off, the AC power supply voltage EO is applied to the load L
The zero-cross detection pulse (No. 3 M in Fig. 2 marked 0) is delayed by a predetermined time t1 from the output (signal J) of the AND goo? 21.
The output is given to a circuit that generates a pulse at the falling edge 9 of a rectangular wave, which is composed of odd-numbered stages of NOTOR gates 17 and OIt gates 23. The NOR gate 23 sends out a pulse signal %K shown in FIG. 2, 0υ, which is delayed by the time υ tl from the detection pulse signal J. This pulse signal has a NAND gate 2
4 to the one-shot circuit 25, and the one-shot circuit 25 sends out a signal shown in FIG. The one-shot circuit 28 is used for the pulse signal percentage of αG in FIG.
One-shot circuit 2 is created by AND with the inverted signal of the output of
5, ANDIC with the output signal of one shot 25, j
:'7' is given to the yacht circuit 28. For this reason, the one-shot circuit 25 always operates before the one-shot circuit 28, and while the one-shot circuit 25 is operating,
When a 1 occurs in the next pulse signal indicated by a 0, the one-shot circuit 28 generates vJ.

The one-shot circuits 25 and 28 generate a rectangular wave having a pulse width longer than the time required for relay operation. If the pulse width time t1 of the one-shot circuit 20 is 1/2 cycle or less, the signal RI which is the output of the one-shot circuit 25 and the pulse signal RI synchronized with the zero cross from positive to negative of the AC power supply voltage EO are The one-shot circuit 20 operates again with the pulse signal J obtained by AND. One-shot circuit 20 and odd-numbered NOTOR gates 40OR
The signal shown in FIG. 2 obtained by the circuit consisting of the gate 23 is delayed by the time t1 from the signal
It is applied to one-shot circuit 28 via ND gate 25 and NOR gate 27. The one-shot circuit 28 sends out a signal M shown in FIG. 2 αQ. The output of the one-shot circuit 25 is an odd-numbered NOTOR gate 40O.
The pulse signal Q shown in FIG. 2(C) is sent from the NOR gate 30 at the falling edge of the @ mark. This pulse signal O is applied to one input terminal of the AND gate 26. One shot circuit 2
The signal M from 8 is inverted by NOTOR gate 40 and
It is applied to the input end of the curved blade of the D gate 26. However, in this case, no signal is sent out from the AND gate 26. The output of the Schmitt circuit 32 is always at a high level when the power supply voltage VCC is on. Therefore, a high level signal is applied to one input terminal of the AND game 133, and a signal E from the Schmitt circuit 10 is applied to the input terminal of the output terminal. A
The output of the ND gate 33 is applied to one input terminal of the ANI) gate 136. A signal from the one-shot circuit 25 is applied to the input terminal of the gate 36. A signal SSN shown in FIG. 2 (4) is sent from the AND gate 36, and this signal qssN becomes a set signal for the relay switch a1.

The output of the one-shot circuit 28 is ANDed with the output of the Schmitt circuit 10, and becomes a set signal for the relay switch a2. A signal SMN shown at ψυ in FIG. 2 is sent from the gate 37. Signal SIN and signal SΔ1N are input to relay drive circuit 7, which causes current to flow through the relay coil so that relay switches a1 and a2 are set.

As described above, by turning on the relay switch a1 when the diode DO is cut off and then turning on the relay switch a2 when the diode Di is turned on, it is possible to energize the load L1 with electric power without arcing.

Next, the operation when powering down the load L1 will be described. When relay switches a1 and a2 are on, a signal synchronized with the load current is transmitted on line 11 from transformer 1. The winding polarity of the transformer l is set so that the output of the transformer l has a phase opposite when detecting the load power supply voltage and when detecting the load current. The output of the AND gate 17 is the pulse signal C shown in FIG. 2 (7), and the output of the OR gate 8 is the puffless signal shown in FIG. 2 (8). The input signal Si applied to the interface circuit 9 changes from high level to low level as shown in FIG. 2 (9).

One shot circuit 20 operates as described above during power activation. In the one-shot circuit 20, relay switches a1. Taking into consideration the off-operation time of a2, it is used to delay the zerox b detection pass signal H by the time tl+t2 so that the relay switch a2 turns off when the diode DO is conductive. Also, one-shot circuit 2
0, the Schmitt circuit 10 cancels chatter from the input signal Si to delay tl when the relay switch a1 is on and tl+t2 when the relay switch a1 is off.
The OR time constant of the one-shot circuit 20 is changed by the signal E from the circuit.

The one-shot circuit 25 and the one-shot circuit 28 are
It operates as described in the power activation section above. The rectangular wave output from the one-shot circuit 25 becomes the reset f word SΔfF of the relay switch a2 by AND with the inverted signal of the signal E.

This reset @ number SMF is sent out from the OR gate 40. The rectangular wave output from the one-shot circuit 28 is ANDed with the inverted signal of the signal E to become a reset signal $88F for the relay switch a1.

This reset signal SSF is sent from the JR gate 43.The reset signal S1F is input to the relay drive circuit, and current flows through the relay coil in the direction of resetting the relay switch a1. Input to drive circuit 47, relay switch a2
A current is passed through the relay coils in the direction to reset the current.

In the above manner, relay switch a2 is connected to diode D
By turning off the relay switch a1 when O is conductive and turning off the relay switch a1 when diode DO is cut off, power can be extinguished without arcing.

Next, the operation under no load will be explained with reference to the timing chart of FIG. Since there is no output from the transformer l when there is no load, it is not possible to obtain a pulse signal from the AND gate 7 and the NOR gate 8 as when there is a load. Therefore, at the falling edge 9 of the signal G output from the EX-OR gate 12, N
The OR gate 46 outputs the signal P shown in FIG. 3 00.

The one-shot circuit 20 is operated by this @ number P, and then the one-shot circuit 25 is operated. At the falling edge of the signal shown in FIG. 3 (8), which is the output of the one-shot circuit 25, N
The OR gate 30 outputs the signal O shown in FIG. 309. This @ number 0 is applied to one input terminal of the D gate 26 to A. The output signal M from the one-shot circuit 28 is inverted by the NUT gate 1-81 and applied to the input terminal of the AND gate 26.

The output of AND game 126 is applied to one-shot circuit 28 via NOR gate 27. In this case, the one-shot circuit 28 is not operating because the pass signal cannot be obtained continuously from the one-shot circuit 20 as in the case of a loaded state. Therefore, the one-shot circuit 28 operates with the half-less signal O shown in FIG. 2(c). Below, in the same way as when loaded, depending on VbeM of the input IFI number Si given to the interface circuit 9, relay switch a1
．． Turn a2 on and off.

Referring to FIG. 4, relay switch a1. The operation of turning on and off a2 will also be explained. Input signal 8 given to interface circuit 9
Set i to high level.

As a switching initial setting function, when the input signal Si is high level, the relay switches al and a2 are initially set, and when the input signal Si is low level 2, the relay switches al and a are set.
This is to perform an initial reset operation on 2. Also, in this case, a backup capacitor C6 is required for driving the relay. When the power supply voltage VCC is turned on from OFF, when the power supply voltage CC reaches the level 1 shown in Figure 4 (7), the Schmitt circuit 32 sends the @ number shown in Figure 4 (3). do. The constant voltage circuit 48 is a circuit that creates a constant voltage VDD7i- based on the power supply voltage CC. Power supply voltage CC is applied to constant voltage circuit 48 and Schmitt circuit 32 via diode D5.

The cathode of diode D5 is grounded via capacitor C7. The signal output from the Schmitt circuit 32 is delayed by the time WO in the Schmitt circuit 14, and the signal S shown in FIG. 4(9) is sent out from the Schmitt circuit 14. Furthermore, this signal S is delayed by a time W5 in the Schmitt circuit 49, and the signal T shown in FIG. 4 is sent out from the Schmitt circuit 49. EX-OR gate 17 outputs signal S and signal T.
is received, and the @ number U which is a rectangular wave shown in FIG. 4 is sent out by exclusive OR. This signal U has the same function as the signal G from the EX-OR gate 12 during the basic operation described above, and when loaded, it is an AN with the zero-cross detection pulse signal.
D, one-shot circuit 20, one-shot circuit 2
5. Operate one-shot circuit 28 in sequence to turn on relay switches al and a2 without arcing.

As shown in FIG. 4 (7), when the power supply voltage VCC turns from on to off, when the power supply voltage CC reaches the level v1, the Schmitt circuit 32 performs a switching operation, and the @ level changes from high level to low level. Become. Next, Schmitt circuit 14, Schmitt circuit 16, one-shot circuit u20. Each circuit operates in the order of one-shot circuit 25 and one-shot circuit 28. However, as a backup for these circuits, a capacitor C7 is connected in front of the constant voltage circuit 48. Nyumit episode v! When the output of &82 goes from high level to low level, it goes from low level to high level as the NO'l' gate 150 goes down. NOT gate 50
The output from the one-shot circuit 25 and the output from the one-shot circuit 25 are
The output of AND game 139 is 011.
Reset signal of relay switch a2 via game 140
Becomes SMF. Applying the output from the NOT gate 50 and the output from the one-shot circuit 28 to the AND game 142,
The output of the AND gate 142 becomes the reset signal %88F of the relay switch al via the OR gate 43. The relay drive circuit 47 is driven by these reset signals SMF and 88F, and the relay switches a2 and al are reset. A backup capacitor C6 is provided at the input stage of the relay drive circuit 47, and the relay switches al and a2 are turned off without arcing.

FIG. 5 is a detailed electrical circuit diagram of the circuit shown in FIG. Components that are the same as those shown in FIG. 1 are given the same reference numerals. In FIG. 5, a constant voltage circuit 48, a Schmitt circuit 32, a Schmitt circuit 14, a Schmitt (iIj[
49, interface circuit 9, Schmitt circuit 310. Schmitt circuit 11. One-shot circuit 5, one-shot circuit 25, and one-shot circuit 28 represent equivalent circuits, respectively. The operation of the circuit shown in FIG. 5 will be explained with reference to the timing chart shown in FIG. The load L1 has the sixth
An AC power supply voltage EO shown in FIG. (1) K is applied via the first winding 3 of the transformer l and the relay switch a2. A signal AI shown in FIG. 6(2) is transmitted to a line 11 of a resistor 3 connected to one end of the tertiary winding 4 of the transformer 1.

This signal AI is applied to the transistor jr1 in the ratio voltage converter 5.
It is compared with the emitter potential of 0 and amplified by the transistor Tr11. ]・The output from the collector of transistor Tr11 is sent to odd-numbered NOT gates 62, OR gates 60,
and the AND gate 61, and the NOOR gate 6
4 are sent out from the AND gate 61 are a pulse signal B1 shown in FIG. 6(3), and a path signal C1a shown in FIG. 6(4).

On the other hand, the power supply voltage CC applied to the anode of the diode D5 increases as shown in FIG. 6(5). The voltage VDD of the constant voltage circuit 48 changes from a low level to a high level as shown in FIG. 6(6)K. Schmidt times 1 heat 3
2 sends out the signal D1 shown in FIG.
It is applied to the ND gate 133 and the AND gate 35. The voltage of the capacitor C6 included in the Schmitt circuit 14 is
The result is as shown in FIG. 6 (8). The output voltage E1 of the Schmitt circuit 14 is as shown in FIG. 6 (9). The voltage of the capacitor C7 included in the Schmitt circuit 49 is shown in FIG. 6 αQ. From the Schmitt circuit 49, α
A signal Fl indicating the temperature is sent out. This signal F is NOT
It is applied to one input terminal of AND game 163 via gate 62 . A signal E is applied to the input terminal of the AND gate 63, and a signal Gl shown in FIG. 6 is sent from the output terminal of the AND gate 163. This belief tG1 is OR
It is applied to one input terminal of the NOOR gate 64 through the gate 64, and to the input terminal of the NOOR gate 66 through the OR gate 64 and the odd-numbered NOT gate 65, and from the NOR gate 166 as shown in FIG. A pulse signal H1 is sent out. A signal Si shown in FIG. 6 is applied to the Δ1UNO terminal of the intermediate frequency circuit 9.

One word 8i containing chatter has the chatter removed by the Schmitt circuit 10, and is output from the Schmitt circuit IO as shown in FIG.
The signal Ml shown in b) is sent out. This signal Ml is @
No. SiJ: is delayed by time W3.

The Schmitt circuit 11 supplies a signal N1 delayed by p time W5 from the signal bil to one input terminal of the EX-OR gate 73. Further, the Schmitt circuit 11 supplies a signal P1 delayed by a time W4 from the signal M1 to one input terminal of the EX-0 gate 74. A signal M1 is applied to the input terminals of EX-0 and the capabilities of gates 73 and 74. EX-(
From the JR gate 73, the signal 01 shown in FIG.
is sent. The EX-OR gate 74 sends out a signal Ql as shown in FIG. Signal 01 is passed through AND gate 80 and OR gate 64 to AND gate 6
7, one input end of the NOR game 166,
and is applied to the input terminal of NOT gate 65. AND
A pulse signal Bl is applied to the horizontal input end of the gate 67, and a buffless call signal 1 shown in FIG. 6 is sent out from the output end of the AND gate 67. EX-OR gate 74
The empty signal Ql is applied to an AND gate 68. A
The ND gate 68 performs the logical product of the signal B1%@signal E1, the signal Ql, and the signal from the N (JT gate 153) and provides this output to the OR gate 70. The signal 11 shown in FIG.

The output of the one-shot circuit 10 is 1 for a signal having a pulse width W1 as shown in FIG. 6 αη.

The output of the one-shot circuit 11 is a signal Lla having a pulse width W2 as shown in section α in FIG.

The AND gate 71 outputs the signal T1 of FIG. 6G (υ) by ANDing the signal C1a and the signal Kl.

The one-shot circuit 5 is operated by the NQOR gate 72 and the NOR of the signal Il and the signal Tl.

The set signal SΔIN of FIG. 7(3), which is output from the AND gate 37, is sent out by ANDing the signal D1, the signal M1, and the signal L1. The set signal SSN in FIG. 7(2), which is the output from the AND game 136, is @No.D1
is sent by ANDing the signal 111 and the signal 1 with 1. When the load power supply voltage EO is applied to the load LO, the p5 relay switch a1 is first set by the set signal SSN, and then the clean switch a2 is set by the set signal 8MN. Therefore, the load power supply voltage EO is applied to the load LO. Reset 1iIr No. 8MFi, AN of FIG. 7(5) which is the output from OR gate 40
The output of the D gate 138 is also sent out by the output of the AND gate 139.The AND gate 38 sends out an output signal by ANDing the signal 1, the signal DI, and the inverted signal of the signal M1. The signal is OR gate 40
becomes the reset signal SMF via the . Person A D Gate 39
From then on, no output signal is sent out due to the inversion of the signal DI. Therefore, the reset signal SMF is sent from the zero gate 40 according to the output of the AND gate 38'. This reset signal 8MF causes relay switch a
2 is reset as shown in FIG.

The reset signal 88F in FIG. 7(4) which is the output from the 01t gate 43 is the
It is sent out by the output of ND gate 42.

The A-to-D gate 41 sends out an output signal by ANDing the @ signal D1, the inverted signal of the signal M1, and the IJ signal L1. A
No output signal is sent from the ND gate 42 due to the inverted signal of the signal Dl. Therefore, the OR gate 43 outputs the reset signal SSF by the output of the A gate 41.
is sent. This reset t@ number SSF resets the relay switch a1 as shown in FIG. 609. As a result of the above, the load power supply voltage EO of the load L1 is cut off.

Effects As described above, according to the present invention, by operating the first relay switch and the second relay switch in accordance with the input signal applied to one control input terminal, the user's usability is improved and the device is used more easily. fewer terminals.

[Brief explanation of drawings]

Fig. 1 is a 7E electrical circuit diagram of an embodiment of the present invention, Fig. 2 is a timing chart for explaining the operation of the electrical circuit shown in Fig. 1 under load, and Fig. 3 is a 7E electrical circuit diagram of an embodiment of the present invention. Timing chart for explaining the operation of the circuit under no load, No. 4
The figure is a timing chart to explain the operation of turning on and off the relay switches al and a2 by turning on and off the voltage CC, and Figure 5 is a detailed γE electric path diagram of the electric circuit shown in Figure @1. 6 and 7 are timing charts for explaining wJ operation of the electric circuit shown in FIG. 5. FIG. EO...AC power supply, LO...load, 3a...core, 3...primary winding, 2...secondary winding, 4...tertiary winding, al... 1st relay switch, a2...2nd
Relay switch, DO...diode, 10.11.
...Nummit circuit, 25.28... One-shot circuit agent Patent attorney Kei Nishi Partial procedure amendment 71) Commissioner of the Patent Office 1. Indication of the case Patent application 1982-159392 2. Name of the invention AC switch circuit 3, relationship with the amended case Applicant address name (583) Matsushita Electric Works Co., Ltd. Representative 4, agent address Shinkosan Building Kokusai EX, 1-13-38 Nishihonmachi, Nishi-ku, Osaka City 0525-5985 IMTAPT J
6. Detailed explanation of the invention column, brief explanation of drawing column and drawing 7 of the specification subject to amendment, Contents of amendment (1) "Inverting input terminal 5'" on page 3, line 11 of the specification (2) In the 7th line of page 6 of the specification, "detection signal J" is corrected to "detection signal I". (3) In the second line of page 7 of the specification, the expression [)< time tlJ of the pulse width is corrected to "time W1 of the pulse width". (4) In the 10th line of page 7 of the specification, the phrase ``Signal H is better'' is corrected to ``Signal 1 is better signal J''. (5) In the 11th line of page 7 of the specification, the phrase l'-AND gate 125J is corrected to ``AND gate 25aj.'' (6) In the 15th to 16th lines of page 8 of the specification. "
"Schmitt circuit 10" is replaced with "Schmitt circuit 10".
, 32J. (7) On page 9, line 3 of the specification, “diode DO
Correct "J" to "diode D1". (8) In the third to fourth lines of page 10 of the specification, [Diode DOJ is corrected to "diode D1." (9) In the 3rd line of page 11 of the specification, ``relay switch all'' is corrected to ``relay switch a2J.'' (10) In the 6th line of page 11 of the specification, ``relay switch a2J'' is corrected. ``Corrected to ``relay switch all.'' ``Corrected ``diode DOj'' to ``diode D1'' in lines 8 to 9 of page 11 of the specification at α. 0■ In the 12th line of page 12 of the specification, “Figure 2 (24
)j should be corrected to ``Fig. 3 05)''. a■ In the 1st and 2nd lines of page 16 of the specification, "one-shot circuit 5" is replaced with "one-shot circuit 20".
Correct. α → In the 17th page, line 12 of the specification, "signal F" is corrected to "signal Fil." In the 17th page, 15th line of the specification, "signal E" is corrected to "signal Ell." (g) In the second line of page 18 of the specification, the phrase "intermediate frequency circuit 9" is corrected to "input intern eighth circuit 9." In the 10th line of page 19 of the αF specification, "one-shot circuit 10" is corrected to "one-shot circuit 25." (G) On page 19, line 19 of the specification, “Figure 7 (3)
)'' should be corrected to [Figure 6 (34) J. In the first line of page 20 of the 0!1 specification, the phrase "with rLl" is corrected to "with rL1'a." In the second line of page 20 of the specification, “Fig. 7 (2)” is corrected to “Fig. 6 (33) J.” (21) In the 10th line of page 20 of the specification, “Fig. Figure 7 (
6)” should be corrected to “Figure 6 (36) J. (22) In the second line of page 21 of the specification, “Figure 7 (4)
)'' should be corrected to [Figure 6 (35) J. (2)) In the sixth line of page 21 of the specification, the phrase "with signal L1" is corrected to "with signal Lla." (24) In the 10th line of page 22 of the specification, the words "and FIG. 7" are deleted. b) Figures 1, 2, and 5 are corrected as shown in the attached sheet. Figure 7 of C has been deleted and Figure 6 has been added as a separate sheet. Patent Application No. 58-159392 dated December 20, 1980 outside the above amendment procedures 2. Name of the invention AC switch circuit 3. Relationship with the person making the amendment Applicant Address 1-chome Nishihonmachi, Nishi-ku, Osaka [113-38] No. Emerging Building Country Equipment EX 0525-5985 INTAPT
J International FAX GIff&G] I (06)538-
0247 December 18, 1980 (shipment date) 6. Subject of amendment No. 6 of drawings other than procedural amendments submitted on May 16, 1980
As shown in Figure 7, the contents of the amendment are attached. Below-1 formula 6)

Claims (1)

[Claims] A series circuit trap including an AC power source, a load, and a primary winding wound around the core, a series circuit including a first relay switch and a diode, a second relay switch, and a primary winding wound around the core. turned 2
A series circuit including a secondary winding is connected in parallel, and the first relay is activated when the diode is cut off based on the output from the tertiary winding wound around the core, prior to power energization of the load. 2') When the diode is conductive, the second relay switch is conductive, and when the load is de-energized, the diode is conductive. In an AC switch circuit that shuts off a switch, the basic wJ operation, initial setting operation, initial set, and initial reset of the first and second relay switches are performed according to the level μ of the input signal applied to one control input terminal. An alternating current switch circuit characterized by comprising a circuit for performing the operation.