SU957379A1 - Transistor converter - Google Patents

Description

(Sk TRANSISTOR CONVERTER

1 The invention relates to a conversion technique and can be used in automation and secondary power devices. Devices are known that contain a master oscillator, a saw-tooth voltage generator, a comparator, and a counting trigger whose outputs through a selector are connected to the power transistors of the converter 11, and 13. The drawbacks of the known devices are the complexity and the inability to use a bridge converter circuit, since the power inputs transistors must be galvanized. Closest to the present invention, there is a transistor converter containing a master oscillator through a comparator connected to one of the selector inputs and also connected to a frequency divider and another selector input, the output of which is connected to the power amplifier, the output connected to the output terminals z associated with the comparator .k. The disadvantages of the device are the complexity and the presence of through currents through the power transistors in a mode in which the fill factor of the control pulses is one (at start-up and an abrupt increase in load current) - which leads to a decrease in the efficiency and reliability of the device and is unacceptable for high-voltage (input) inverters. The purpose of the invention is to simplify, increase the efficiency and reliability of the device. The goal is achieved by the fact that in the transistor converter the master oscillator is made according to the asymmetric relaxer circuit, the master clock time, the switch of which is connected to the comparator input, and the second input of the selector is connected to the output of the master oscillator and the input of the frequency divider, 395 and the outputs of the selector and frequency divider are connected to the inputs of the input control voltage driver, the output of the power connected to the amplifier. In addition, in order to expand the functionality, the control voltage driver is made according to a circuit in which the outputs of a frequency divider are connected to the primary winding of the transformer, the secondary windings of which are connected to one input of the intermediate amplifier, and the outputs of the frequency divider are also connected to the first inputs of two logical NAND elements, the second inputs of the office are connected to the output of the selector, and the outputs are connected to the inputs of the RS flip-flop, the outputs of which through another transformer are connected to other inputs and an intermediate body force. FIG. 1.Predstavlenna schematic diagram of the transistor converter; in fig. 2 - time diagrams; in fig. 3 diagram with advanced functionality; in Fig., k are graphs explaining the operation of the circuit. The converter consists of a master oscillator 1, which includes a differential UGM 2, a resistive divider 3 positive feedback, resistors and 5, a diode 6, and a capacitor 7, which form the negative feedback of the master oscillator. The capacitor 7 is connected to the input of the comparator 8, the other input of which is connected to the error amplifier 9, and the output through the selector 10 to the intermediate amplifier transistor 11, the inputs of transistors 12 and 13 of which are connected to the outputs of the divider frequency I. In addition, the secondary windings of the transformer 15 are connected to the power transistors of the power amplifier 16, to which a load 18 is connected via a rectifier with a filter 17.

The scheme works as follows.

When the supply voltage is applied at the output of the UFT, a positive level of the output voltage is established (Fig. 2, point a), and the capacitor 7 begins to charge through the resistors 5 and diode 6.

When the voltage on the capacitor reaches the voltage level at the non-inverted input of the DCF 2, the last

Suppose that the state of the divider AND frequency is such that the transistor 12 of the intermediate amplifier is open at the indicated time interval. The transistor 11 is also open in the interval 6 ... (a positive pulse at the output of the comparator UQ), therefore, the primary half-winding of the transformer 15 is connected to the supply voltage and the control voltage is supplied to the power transistors of the power amplifier 16. At point B, the output voltage of the comparator closes the transistor 11 and the transformer 15 is disconnected from the supply voltage. There is no surge voltage on the windings of the transformer 15 (U, dashed),

since the self-induced emf closes on the open transistor 12 and the diode shunt the transistor 13, which makes it possible to use one transformer (amplifier) to control

Claims (3)

power transistors adjustable power amplifier. At interval B ... and the transistor 11 is closed and on the windings of the transformer 15 both of them reliably turn over, the voltage at its output becomes close to zero and the capacitor 7 is discharged through the resistor k. Due to the presence of nonlinear feedback (resistors C, 5, diode 6), the form of voltages at the capacitor (s) and at the output of the DCF (U) is asymmetric in time (Fig. 2). The voltage from the capacitor 7 goes directly to the comparator 8, which eliminates the need for a special sawtooth generator and uses the timing element of the generator 1 as the FPG. To the other input of the comparator 8, the output voltage of the error body 9 is fed, and at the output of the comparator width-modulated control pulses are generated, coming through the selector 10 to the intermediate amplifier transistor 11, the other transistors 12 and 13 of which are connected to the outputs of the frequency divider 1, as which has an estimated trigger. Divider 1 changes the voltage at the outputs at the points b, t, i.e., the trigger is triggered from the falling edge of the positive pulse of the output voltage of the master oscillator U. Consider one half-cycle of the scheme (points b ... d). , - 5, 95 zero voltage level is applied. Since in transient conditions (starting, abruptly increasing the load current) the fill factor of the comparator output pulses is equal to one, there are through currents through the power transistors of the power amplifier 16. To eliminate the through-currents of the transitional periods between the comparator 8 and the transistor 11, a selector 10 is introduced, the other input of which is connected to the output of the master oscillator. At intervals a ... S, 1 ... E, regardless of the state of the comparator, the transistor 11 is blocked by the output voltage of the master oscillator, which ensures a guaranteed pause in the control voltage. The selector can be made on a transistor, the input of which is connected to the master oscillator, and the output shunts a baso-emitter switch; the course of the transistor 11. The output voltage of the transformer 15 with a maximum fill factor is shown in FIG. 2 (Uxfg). In the advanced functionality diagram (Fig. 3), the outputs of the frequency divider k are connected to the primary winding of the transformer 19. The secondary winding is connected to the input of the intermediate amplifier 20 RS logic flush-mounted elements 21 and 22 are connected to the outputs of two logic AND-NOT elements 23 and 2k. At the moment of equality of the voltages U-j and the voltage Ug from the amplifier output, the comparator switches, at the output of the selector 10, a high potential, the trigger switches to the state determined by the output voltages of the frequency divider. On the secondary side of the transformer, a rectangular voltage shifted from / to the voltage of the frequency divider at the time, defined by the moment the comparator triggers, is formed. After the comparator has tripped, the previously turned on transistors of the power amplifier 16 are turned off. At start-up, when the voltage at the output 9 is always higher than the voltage level U-, the switching of the flip-flops 21 and 22 is performed by the voltage and, thus, the through currents in the power amplifier 16 are eliminated. In the other extreme mode of the comparator, when the voltage at the output 9 is always less than the voltage U., the output of the comparator 8 is low, the output of the selector 10 is always high potential and the voltage is always antiphase voltage U, i.e. the transistors of the power amplifier 16 are always locked. The main advantage of this driver voltage driver circuit is that it can be used with various intermediate amplifiers. The proposed device is easier known. It improves efficiency and reliability by using a single selector controlled from an unbalanced master oscillator, which provides a guaranteed pause in the control voltage. Claim 1. Transistor converter containing a master oscillator through a comparator connected to one of the selector inputs and also connected to a frequency divider and another selector input, the output of which is connected to the power amplifier, output connected to the output terminals and feedback circuit associated with the comparator, characterized in that, in order to simplify it and increase reliability, the master oscillator is designed as an asymmetrical relaxator, the time master capacitor of which is connected to the comparator input and the second input of the selector is connected to the output of the master oscillator and the input of the frequency divider, with the outputs of the selector and frequency divider being connected to the inputs of the input control voltage driver, the output connected to the power amplifier, 2. The converter according to claim 1, characterized in that, in order to expand its functionality, the control voltage driver is made according to a scheme in which the outputs of the frequency divider are connected to the primary winding of the transformer, the secondary winding of which is connected to one of the intermediate amplifier inputs, in addition, the outputs of the frequency divider are also connected to the first inputs of two logical elements AND-NOT, the second inputs of which are connected to the output of the selector, and the outputs are connected to the inputs of the RS flip-flop, the other of which nsformator bonded 7:, 957379 8 with other inputs of intermediate usi-2. Collection ETVA. M., Soviet Literary Radio, 1978, №10, p. 9b. Information sources, 3. USSR author's certificate taken into account in the examination №, cl. H02 R 13/16, 1977. 1, USSR author's certificate5 k. USSR authorship No. H 02 M 3/335, 1976.W 586530, cl. H02 M 3/2, 1976. v 1 /, l / f fe /