JPH0161206B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AC switch circuit, and more specifically, the present invention relates to an AC switch circuit, and more particularly, two switch circuits for switching loads, which are inserted in a series circuit between an AC power source and a load to form a closed loop, and are connected in parallel to each other. The first and second relay switches have diodes connected in series, and the ON operation of the relay switch is as follows:
The closed-loop load voltage is detected when the first and second relay switches are off, and an on-pulse is generated correspondingly to each positive or negative half cycle, and the on-pulse is input to turn on the load. Based on the coincidence of the command signal and the on-pulse, the voltage waveform of the AC power source turns on the first relay switch during the reverse half cycle of the diode, and after a delay turns on the second relay switch during the forward half cycle of the diode. The on and off operations of the relay switch are as follows:
Detects the closed loop load current when the first and second relay switches are on, creates an off pulse that is output in response to each positive or negative half cycle, and creates an off pulse that is input to turn off the load. Based on the coincidence of the command signal and the off pulse, the voltage waveform of the AC power source turns off its second relay switch during the forward half-cycle of the diode, and later turns off the first switch during the reverse half-cycle of the diode. This relates to an AC switch circuit that turns off.

Referring to FIG. 1, in the prior art, a switching circuit 3 is connected to an AC power source 1 and a load 2 in a closed loop. In order to detect the timing for changing the switching mode of the switching circuit 3, a current detector CT detects the current flowing in the closed loop when the switching circuit 3 is conductive;
A voltage detector PT is provided to detect the voltage across the switching circuit 3 when the switching circuit 3 is cut off. Current detector CT and voltage detector PT
The output from the switch control circuit 4 is given to the switch control circuit 4. The switch control circuit 4 changes the switching mode of the switching circuit 3 at a desired arc-free timing in response to outputs from the current detector CT and voltage detector PT and on and off command signals applied to the control input terminal 5. Change the switching mode to the desired one. However, the current detector CT and the voltage detector PT are used individually, and the number of parts is large, and the space for the current detector CT and the voltage detector PT is large, resulting in high cost. When voltage detector PT is detecting voltage, current detector CT is not detecting current. Conversely, when current detector CT is detecting current, voltage detector PT is not detecting voltage.
Since the voltage detector PT and the current detector CT detect voltage and current alternately in this way, the voltage detector PT and the current detector CT are not used efficiently.

The purpose of the present invention is to solve the above-mentioned technical problems,
To provide an AC switch circuit that can efficiently detect current and voltage, reduce the number of components for the detection, and minimize the space required.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit diagram of one embodiment of the present invention. AC power supply 11, load 12 and terminals 13,1
A switching circuit 15 is connected to 4 to form a closed loop. The switching circuit 15 includes a first relay switch 16, a second relay switch 17, and a diode 18. 1st relay switch 1
6 and diode 18 are connected in series. A second relay switch 17 is connected in parallel to a series circuit consisting of a first relay switch 16 and a diode 18.

In the middle of the closed loop, the first ring of the annular iron core 19
Coils 20 are connected in series. Annular core 19
has a second coil 21 and a third coil 22. The second coil 21 is connected in series with a resistor 23 having high impedance. Second coil 21
and resistor 23 are connected in parallel to second relay switch 17. The third coil 22 is connected to the switch control circuit 31. The first, second and second coils 20, 21, 22 are magnetically coupled to each other.

When the switching circuit 15 is conductive, that is, the first and second relay switches 16 and 17
is conducting, AC power supply 11 → load 1
A large current i0 flows through the path 2→terminal 13→second relay switch 17→first coil 20→terminal 14→AC power supply 11 or the opposite path, and the load 1
2 is powered on. Large current i in the first coil 20
When 0 flows, the annular iron core 19 is saturated, and a saturated output at the time of load current detection is derived from the third coil 22 to the switch control circuit 31.

When the switching circuit 15 is cut off, that is, the first and second relay switches 16 and 17
is cut off, AC current 11 → load 1
2 → terminal 13 → resistor 23 → second coil 21 → first
A small current i1 flows through the coil 20→terminal 14→AC power supply 11 path or the reverse path, and the load 12 is de-energized. When a small current i1 flows through the first and second coils, the annular iron core 19 is unsaturated, and an unsaturated output is derived from the third coil 22 to the switch control circuit 31 when the load voltage is detected.

The first relay switch 16 is associated with the first latching relay 32. This first latching relay 32 is a so-called single-turn latching relay, and has a relay coil 33. When the relay coil 33 is temporarily excited in the direction of the arrow 34, the first relay switch 16 becomes conductive after the operating time W1 required for it to become conductive, and mechanically maintains its conductive state. Further, when the relay coil 33 is temporarily excited in the opposite direction of the arrow 35, the first relay switch 16 enters the cut-off state after the operating time W2 required for cut-off, and maintains the cut-off state by itself.

Relay coil 33 of first latching relay 32
A first relay drive circuit 36 is provided in the switch control circuit 31 to drive the switch control circuit 31 . In this first relay drive circuit 36, the transistor TR1 and the transistor TR2, which serve as semiconductor switching elements, are connected in series, and their connection point 37
is the relay coil 33 of the first latching relay 32.
Connected to one terminal of Transistor TR3 and transistor TR4 are connected in series, and their connection point 38 is connected to the other terminal of relay coil 33.

Zener diodes 39 and 40 are connected between the connection points 37 and 38 to prevent back electromotive force of the relay coil 33.
are connected in series in opposite directions.

The output of the AND gate G1 is applied to the base of the inverting transistor TR5 and also to the base of the aforementioned transistor TR4. The collector of transistor TR5 is a transistor
Connected to the base of TR1. AND gate G2
The output of is applied to the base of transistor TR6 and to the base of transistor TR2. The collector of transistor TR6 is connected to the base of transistor TR3.

When the output of AND gate G1 becomes high level,
Transistors TR4 and TR5 become conductive, and transistor TR1 becomes conductive. The output of AND gate G2 is at low level, so the transistor
TR2 and TR6 are blocked. Therefore, transistor TR3 is cut off. In this way, a current path passing through the transistor TR1, the connection point 37, the relay coil 33, the connection point 38, and the transistor TR4 is formed, and the relay coil 33 is connected to the arrow 34.
Current flows in the direction of. Therefore, the first relay switch 16 becomes conductive and self-maintained.

When the output from AND gate G2 becomes high level, transistors TR2 and TR6 become conductive, and transistor TR3 becomes conductive. The output of AND gate G1 is at a low level, transistors TR4 and TR5 are cut off, and transistor TR1 is cut off. In this way, a current path passing through the transistor TR3, the connection point 38, the relay coil 33, the connection point 37, and the transistor TR2 is formed, and an excitation current flows in the relay coil 33 in the direction of the arrow 35, which is the opposite direction to the above. This makes the first
Relay switch 16 is shut off and self-maintained.

The second latching relay 41 associated with the second relay switch 17 is also a single-winding latching relay like the first latching relay 32, and in order to drive the relay coil 42, the second latching relay 41 is A relay drive circuit 43 is provided. This second relay drive circuit 43 is configured similarly to the first relay drive circuit 36, and has a transistor
TR7~TR12, Zena diode 44, 45
The output of AND gate G3 is connected to the bases of transistors TR10 and TR11, and the output of AND gate G3 is connected to the bases of transistors TR8 and TR12.
4 outputs are given.

When the output of AND gate G3 becomes high level,
Transistors TR10 and TR11 become conductive, and transistor TR7 becomes conductive. The output of AND gate G4 is at a low level, so transistors TR8 and TR12 are cut off. Therefore, transistor TR9 is cut off. Thus transistor TR7, connection point 46, relay coil 4
2, a current path passing through connection point 47 and transistor TR10 is formed, and current flows through relay coil 42 in the direction of arrow 48. Therefore, the second relay switch 17 becomes conductive and self-maintained after the operating time W3 required for it to become conductive.

When the output from AND gate G4 becomes high level, transistors TR8 and TR12 become conductive, and transistor TR9 becomes conductive. AND
The output of gate G3 is low level, transistors TR10 and TR11 are cut off, and transistor TR
7 is blocking it. Thus transistor TR
9, connection point 47, relay coil 42, connection point 46
A current path passing through the transistor TR8 is formed, and an excitation current flows through the relay coil 42 in the direction of arrow 49, which is the opposite direction to that described above. As a result, the second relay switch 17 is self-maintained by shutting off after the operating time W4 required for shutting off.

When the current flowing through the relay coils 33, 42 is cut off, the relay coils 33, 42 are connected to the supply voltage.
A voltage exceeding Vcc occurs and transistor TR1
- Zener diodes 39, 40, 44, and 45 are provided to prevent the TR 12 from being destroyed. Each terminal 5
0 is given the supply voltage Vcc. Here, the breakdown voltage of the Zener diodes 39, 40, 44, 45 is a value exceeding the voltage of the supply voltage Vcc, and the transistors TR1 to TR12 of the first relay drive circuit 36 and the second relay drive circuit 43
is less than the voltage at which it breaks down.

When the outputs of the AND gates G1 to G4 change from a high level to a low level, a back electromotive force is generated in the relay coils 33 and 42. At this time, relay coil 33 → connection point 37 → Zena diode 39 → Zena diode 40 → connection point 38 → relay coil 33, relay coil 42 → connection point 46
→Zena diode 44 →Zena diode 45
→ Connection point 47 → Current flows in the relay coil 42 or vice versa, and the Zener diode 39, 4
0, 44, 45 break down. Since the Zener diodes 39, 40, 44, and 45 break down, the back electromotive force is absorbed and the transistor
TR1 to TR12 will not be destroyed.

In the switch control circuit 31, the annular iron core 19
Diodes 61 and 62 having mutually opposite directions are connected in parallel to the tertiary coil 22 . The diodes 61 and 62 serve to suppress the output from the tertiary coil 22 within their forward voltage range. The DC voltage +Vcc is divided by resistors 63 and 64, and this divided voltage V1 is applied to one end of the tertiary coil 22. The other end of the tertiary coil 22 is connected to a non-inverting input of a rectangular wave shaping circuit 65 and an inverting input of a rectangular wave shaping circuit 66, respectively.

The inverting input of the rectangular wave shaping circuit 65 is supplied with a voltage V2 of DC voltage +Vcc divided by resistors 67 and 68. The rectangular wave shaping circuit 65 performs waveform shaping using the voltage V2 as a threshold. The non-inverting input of the rectangular wave shaping circuit 66 has a DC voltage +Vcc.
A voltage V3 divided by the resistors 69 and 70 is applied. The rectangular wave shaping circuit 66 performs waveform shaping using the voltage V3 as a threshold. The threshold value V2 of the rectangular wave shaping circuit 65 is set to be larger than the threshold value V3 of the rectangular wave shaping circuit 66 (V2>V3).

The output of the rectangular wave shaping circuit 65 is an AND gate G.
5, and through an odd number (two shown) of inverters G6 and G7.
It is applied to the other input of AND gate G5.
A rising differential circuit is configured by AND gate G5 and inverters G6 and G7. AND gate G5 outputs a high-level pulse when the output of rectangular wave shaping circuit 65 rises. This pulse becomes the zero detection output of the load power supply voltage.
The output of AND gate G5 is AND gate G8, G
9, respectively.

The output of the rectangular wave shaping circuit 66 is an AND gate G.
10, and via an odd number (two shown) of inverters G11, 12.
It is applied to the other input of AND gate G10.
The output of the rectangular wave shaping circuit 66 is also applied to one input of an AND gate G13 and, via an inverter G14, to one input of an AND gate G15. The output of AND gate G10 is given to monostable circuit 71. monostable circuit 7
1 outputs a high-level signal with a predetermined pulse width W5 in response to a high-level differential pulse from the AND gate G10. This monostable circuit 71
is provided to determine whether the annular core 19 is detecting load voltage or detecting load current. This pulse width W5 is shorter than the pulse width W6 of the high level output of the rectangular wave shaping circuit 66 when detecting the load voltage, and the pulse width of the high level output of the rectangular wave shaping circuit 66 when detecting the load current.
It is set longer than W7 (W6>W5>W7). The output of the monostable circuit 71 is passed through the inverter G16.
It is applied to the other input of AND gate G13 and the other input of AND gate G15.

The output of AND gate G13 is NOR gate G1
7 and the other input of NOR gate G17 via an odd number (two shown) of inverters G18 and G19.
NOR gate G17 and inverter G18,G
19 constitutes a differentiating circuit, and when the output of AND gate G13 falls, NOR gate G1
7 outputs a high level differential pulse. NOR
The output of gate G17 is given to monostable circuit 72. The monostable circuit 72 responds to the differential pulse from the NOR gate G17 and generates a predetermined pulse width.
Outputs W8 high level pulse. This pulse width W8 is set to a time longer than the time difference from when the output of the rectangular wave shaping circuit 66 changes from high level to low level until the output of the rectangular wave shaping circuit 65 changes from low level to high level. In other words, the monostable circuit 72 performs an AND operation when detecting the load voltage.
It plays the role of passing only the pulse from gate G5. The output of the monostable circuit 72 is an AND gate G
8 to the other input. AND gate G8
is the high level output from the monostable circuit 72, and
A high-level pulse is output in response to the pulse from AND gate G5 (hereinafter referred to as an on-pulse). This on-pulse is applied to one input of AND gate G23.

The output of AND gate G15 is NOR gate G2
0 and is also applied to the other input of NOR gate G20 via an odd number (two shown) of inverters G21 and G22.
NOR gate G20 and inverter G21,G
22 constitutes a differentiation circuit, and when the output of AND gate G13 falls, NOR gate G2
0 outputs a high level differential pulse. NOR
The output of gate G20 is given to monostable circuit 73. The monostable circuit 73 responds to the differential pulse from the NOR gate G20 and generates a predetermined pulse width.
Outputs W9 high level pulse. This pulse width W9 is set to a time longer than the time difference from when the output of the monostable circuit 71 changes from high level to low level until the output of the rectangular wave shaping circuit 65 changes from low level to high level during current detection. be done. That is, the monostable circuit 73 serves to pass only the pulse from the AND gate G5 when detecting the load current. The output of the monostable circuit 73 is
It is applied to the other input of AND gate G9.
AND gate G9 outputs a high level pulse (hereinafter referred to as an off pulse) based on the high level output from monostable circuit 73 and the pulse from AND gate G5. This off-pulse is applied to one input of AND gate G24.

An on command signal for turning on the load 12 or an off command signal for turning off the load 12 applied to the control input terminal 81 is transmitted through the diode 82,
83, a resistor 84, and a buffer G25 having a waveform shaping function. In the first noise removal circuit 85, the buffer G
The signal from 25 is applied to one input terminal of AND gate G26, and is also applied via a first delay circuit 88 consisting of a resistor 86 and a capacitor 87.
It is applied to the other input terminal of AND gate G26.

If the input signal applied to the control input terminal 81 contains impulsive noise, there is a risk that it will be interpreted as an erroneous logic signal. The signal input to the first delay circuit 88 is transmitted to the first delay circuit 88 after a delay time ΔT1.
8. When the signal applied to the control input terminal 81 is low level and includes high level impulsive noise, the high level impulsive noise is delayed by the delay time ΔT1. The output of the AND gate G26 is the logical product of both inputs, and becomes low level by delaying the impulsive noise by a time ΔT1. Therefore, the first noise removal circuit 85 removes high-level impulsive noise. AND gate G26
The output of is input to the second noise removal circuit 89.

In the second noise removal circuit 89, the output from the AND gate G26 is applied to one input terminal of an OR gate G27, and is also passed through a second delay circuit 92 consisting of a resistor 90 and a capacitor 91.
It is applied to the other input terminal of OR gate G27.

Assume that the command signal applied to the control input terminal 81 contains high-level and low-level impulsive noise. This low-level impulsive noise is delayed by the second delay circuit 92 by a delay time ΔT2. The output of the OR gate G27 is the logical sum of both inputs, and therefore becomes a high level signal from which low level impulsive noise has been removed. Since high level impulsive noise is removed in the first noise removal circuit 85 and low level impulsive noise is removed in the second noise removal circuit 89, high level and low level impulsive noise are removed from OR gate G27. A removed on or off command signal is output.

The output of OR gate G27 is AND gate G1,
One input of G3, G28, AND gate G23
and the input of inverter G29. The output of inverter G29 is connected to one input of AND gates G2, G4, and G30.
It is applied to the other input of AND gate G24.
The output of AND gate G23 is given to one input of OR gate G31. The output of AND gate G24 is given to the other input of OR gate G31. The output of OR gate G31 is AND gate G
32. AND gate G
The output of inverter G33 is given to the other input of G32. The output of AND gate G32 is given to the input of delay circuit 101. Delay circuit 10
1 outputs the output of the AND gate G32 with a delay of time W10. This time W10 is set so that the relay set signal is issued earlier by the operation time W1 of the first relay switch 16, and the on-pulse is delayed so that the first relay switch 16 becomes conductive when the diode 18 is in the cut-off state. .

The output of the delay circuit 101 is connected to the AND gate G28,
G30's other input.
The output of AND gate G28 is given to one input of OR gate G34. The output of AND gate G30 is given to the input of delay circuit 102. The delay circuit 102 delays the output of the AND gate G30 by a time W11 and outputs the delayed output. The sum of this time W11 and the above-mentioned time W10 (W10+W11) is such that the relay reset signal is output earlier by the operating time W4 of the second relay switch 17, and the second relay switch 17 is cut off when the diode 18 is in a conductive state. for,
Set by delaying the off pulse.

The output of delay circuit 102 is given to the other input of OR gate G34. The output of OR gate G34 is given to the input of monostable circuit 103. Monostable circuit 103 outputs a high-level pulse with a pulse width W12 in response to a high-level signal from OR gate G34. This pulse width W12 is determined by the time difference between when the first relay switch 16 is turned on and when the second relay switch 17 is turned on, and the time difference between when the second relay switch 17 is turned off and when the first relay switch 16 is turned off. This is the time before and after a half cycle of the AC power supply 11.

The output of monostable circuit 103 is NOR gate G35
through an odd number (two shown) of inverters G36 and G37.
It is applied to the other input of NOR gate G35.
NOR gate G35 and inverter G36,G
37 constitutes a differentiator circuit, and monostable circuit 1
At the falling edge of 03, the NOR gate G35 outputs a high-level differential pulse. monostable circuit 10
The output of 3 is also applied to one input of OR gate G38. The output of NOR gate G35 is given to monostable circuit 104.

The monostable circuit 104 responds to the differential pulse from the NOR gate G35 and outputs a high-level pulse with a pulse width W13. This pulse width W13 is longer than the operation time W3 of the second relay switch 17,
That is, the time required for a sufficient current to flow through the coil 42 to cause the second relay switch 17 to conduct, and the time longer than the operation time W2 of the first relay switch 16, that is, the time required for the first relay switch 16 to flow through the coil 33 only to cause the first relay switch 16 to turn off. The time is set to allow sufficient current to flow.

The output of the monostable circuit 104 is connected to the AND gate G2,
It is applied to the other input of G3 and the other input of OR gate G38. OR gate G38
The output of is given to the other input of AND gates G1 and G4 and the input of inverter G33, respectively.

The operation will be explained with reference to FIG. AC power supply 1
AC power having a voltage waveform shown in FIG. 3 is supplied from terminal 1 to terminal 13. When the first and second relay switches 16 and 17 are closed, the load voltage is detected from the tertiary coil 22 of the annular core 19 at each period of the voltage waveform as shown by the arrow 111 in FIG. The unsaturated output is derived. When the first and second relay switches 16 and 17 are conductive, the load current is detected from the tertiary coil 22 of the annular core 19 at each cycle of the voltage waveform as shown by the arrow mark 112 in FIG. The saturated output is derived.

The unsaturated and saturated outputs from the tertiary coil 22 are processed by the rectangular wave shaping circuit 65 at a threshold value V2.
The waveform is shaped by The output of the rectangular wave shaping circuit 65 is shown in FIG. The output of the rectangular wave shaping circuit 65 is connected to an AND gate G5, an inverter G6,
The rise is differentiated by G7, and the AND gate G
The differential pulse output from 5 is shown in FIG.

The unsaturated and saturated outputs from the tertiary coil 22 are also processed at a threshold value in a square wave shaping circuit 66.
The waveform is shaped by V3. The output of the square wave shaping circuit 66 is shown in FIG. Square wave shaping circuit 66
The output of is differentiated by AND gate G10 and inverters G12 and G13,
The differential pulse output from AND gate G10 is shown in FIG. 36. The monostable circuit 71 is an AND
In response to the differential pulse from gate G10, the third
As shown in FIG. 7, a high-level pulse with a pulse width W5 is output.

The AND gate G13 detects the load voltage of the annular core 19 as shown in FIG. Outputs a high-level pulse only when The output of AND gate G13 is differentiated to fall by NOR gate G17 and inverters G18 and G19. The differential pulse output from NOR gate G17 is shown in FIG. 39. monostable circuit 72
responds to the differential pulse from the NOR gate G17 and outputs a high-level pulse with a pulse width W8 as shown in FIG. 310. AND gate G8
outputs a high-level pulse, that is, an on-pulse, only when the load voltage of the annular core 19 is detected, as shown in FIG. 3, by the pulse from the monostable circuit 72 and the pulse from the AND gate G5. .

The AND gate G15 detects the load current of the annular core 19 as shown in FIG. Outputs a high-level pulse only when The output of AND gate G15 is differentiated to fall by NOR gate G20 and inverters G21 and G22. The differential pulse output from NOR gate G20 is shown in FIG. 3. monostable circuit 73
responds to the differential pulse output from NOR gate G20, and changes the pulse width as shown in FIG.
Only W9 outputs a high level pulse. AND gate G9 receives the pulse from monostable circuit 73,
The third
As shown in FIG. 15, a high-level pulse, that is, an off-pulse, is output only when the load current of the annular core 19 is detected.

With the first and second relay switches 16 and 17 in the cutoff state, a high-level ON command signal for energizing the load 12 is applied to the control input terminal 81 at time t1 as shown in FIG. 3. When given, the on-pulse from AND gate G8;
OR gate G27 with impulsive noise removed
The AND gate G23 outputs a high-level pulse as shown in FIG. 17 in response to the high-level signal from . The high level pulse from AND gate G23 is passed through OR gate G31.
It is applied to one input of AND gate G32.
The AND gate G32 receives the high level pulse from the AND gate G23 only during the period when the output of the inverter G33 is at the high level, as shown in FIG. 3. As shown in FIG. 19, the signal is passed through and applied to the delay circuit 101. Delay circuit 101
outputs the high level pulse from the AND gate G32 with a delay of time W10 as shown in FIG. 320.

The high level output from the delay circuit 101 is
Since one input of AND gate G28 is at high level, AND gate G28 and OR gate G
34 to the monostable circuit 103. The monostable circuit 103 outputs a high level pulse for a time W12 as shown in FIG. 3, in response to the high level pulse from the OR gate G34.

The high level output of the monostable circuit 103 is
NOR gate G35 and inverter G36,G
It is differentiated by 37 in the falling direction. The differential pulse output from the NOR gate G35 is shown in FIG.
is shown. Monostable circuit 104 is NOR gate G
In response to the differential pulse from 35, a high level pulse with a pulse width W13 is output as shown in FIG. OR gate G38 is monostable circuit 10
3, 104 outputs a high level pulse with a pulse width (W12+W13) as shown in FIG.

As described above, first, the output of the AND gate G1 becomes high level as shown in FIG. 25 in response to the positive pulse from the OR gate G38.
As a result, a current flows through the relay coil 33 in the direction of the arrow 34, and as shown in FIG.
The relay switch 16 is turned on and set during the negative phase of the load voltage, that is, the reverse half cycle of the diode 18.

The output of AND gate G3 then changes as shown in FIG.
The level is high as shown in . By that,
A current flows through the relay coil 42 in the direction of the arrow 48, and as shown in FIG. be done.

By the above-described operation, the load 12 can be energized without generating an arc.

As described above, depending on the power energization of the load 12, the third
A load current flows as shown in FIG. As the load current flows, an off pulse is output from the AND gate G9 as described above.

With the first and second relay switches 16 and 17 in conduction, a low-level off command signal for de-energizing the load 12 is applied to the control input terminal 81 at time t2 as shown in FIG. 3. When given, inverter G29 has OR gate G27
A low level signal from which impulsive noise has been removed is provided. The output of inverter 29 is shown in FIG. 30. AND gate 24 is AND
Off pulse from gate G9 and inverter G2
31 by the high level signal from 9.
Outputs a high-level pulse as shown in .
The high level pulse from AND gate G24 is
It is applied to one input of AND gate G32 via OR gate G31. AND gate G32 is
The output of inverter G33 shown in FIG.
As shown in FIG. 3, the high-level pulse from the AND gate G23 is passed only during the high-level period, that is, the period excluding when the monostable circuits 103 and 104 are in operation, as shown in FIG. give to The delay circuit 101 receives the high level pulse from the AND gate G32 as shown in FIG.
As shown in 0, the output is delayed by a time W10.

The high level output from the delay circuit 101 is
Since one input of AND gate G30 is at high level, it is applied to delay circuit 102. The delay circuit 102 delays the high level pulse from the AND gate G30 by a time W11 as shown in FIG. 32 and outputs the delayed pulse. The output of the delay circuit 102 is
It is applied to monostable circuit 103 via OR gate G34. Monostable circuit 103 is OR gate G3
3 in response to the high level pulse from 4.
As shown in 1, a high level pulse is output for a time W12.

The high level output of the monostable circuit 103 is
NOR gate G35 and inverter G36,G
It is differentiated by 37 in the falling direction. The differential pulse output from the NOR gate G35 is shown in FIG.
is shown. Monostable circuit 104 is NOR gate G
In response to the differential pulse from 35, a high level pulse with a pulse width W13 is output as shown in FIG. OR gate G33 is monostable circuit 10
3, 104 outputs a high level pulse with a pulse width (W12+W13) as shown in FIG.

As described above, the output of AND gate G4 becomes high level as shown in FIG. 33,
A current flows through the relay coil 42 in the direction of arrow 49 . As a result, the second relay switch 17 is turned off and reset in the positive phase of the load current, that is, in the forward half cycle of the diode 18, as shown in FIG. 3.

Then, the output of AND gate G2 is as shown in FIG.
The level becomes high as shown in , and relay coil 3
3, a current flows in the direction of arrow 35. As a result, the first relay switch 16 is turned off and reset in the negative phase of the load current, that is, in the reverse half period of the diode 18, as shown in FIG. 26.

By the above-described operation, it is possible to de-energize the load 12 without generating an arc.

As described above, according to the present invention, load current and load voltage can be detected efficiently using a single annular core, the number of components for detection can be reduced, and the space can be saved as much as possible. It can be made small.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the prior art, FIG. 2 is an overall circuit diagram of an embodiment of the present invention, and FIG. 3 is a timing chart for explaining its operation. 11... AC power supply, 12... Load, 16... First relay switch, 17... Second relay switch, 18... Diode, 19... Annular iron core, 2
0...First coil, 21...Second coil, 22...
... Third coil, 67 to 70 ... Resistor, 31 ... Switch control circuit, 65, 66 ... Rectangular wave shaping circuit, 71 ... Monostable circuit, 81 ... Control input terminal.

Claims (1)

[Scope of Claims] 1. Two first and second relay switches for switching a load, which are inserted in a series circuit of an AC power source and a load in a closed loop and are connected in parallel to each other, The first relay switch has a diode connected in series, and the on operation of the relay switch corresponds to each positive or negative half cycle by detecting the closed loop load voltage when the first and second relay switches are off. Create an on-pulse that is output by
Based on the match between the ON command signal input to turn on the load and the ON pulse, the voltage waveform of the AC power source turns on the first relay switch during the half period in the opposite direction of the diode, and after a delay, the second relay switch is turned on. The switch is turned on during the forward half cycle of the diode, and the relay switch is turned off every positive or negative half cycle by detecting the closed loop load current when the first and second relay switches are on. Create an off pulse that is output by
Based on the coincidence of the off command signal input to turn off the load and the off pulse, the voltage waveform of the AC power source turns off its second relay switch during the forward half period of the diode, and after a delay turns off the first relay switch. In an AC switch circuit that turns off the switch in a half period in the opposite direction of the diode, a first coil connected in series in the middle of the closed loop to detect the load current, a high impedance coil and parallel to the second relay switch. A second coil is connected to the second coil for detecting the load voltage, and a third coil is magnetically coupled to the first and second coils to derive a saturated output when detecting a load current and to derive an unsaturated output when detecting a load voltage. An AC switch circuit characterized in that an annular iron core equipped with a coil is provided, and an off-pulse and an on-pulse are created by discriminating between saturated output and unsaturated output.