JPS5914221A - Ac switch circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AC switch circuit interposed between an AC power source and a load to prevent arcing between contacts that open and close.

In the prior art, the first time limit circuit is operated and the second time limit circuit is operated by a gate that outputs when an input signal for operating the first and second relay switches matches an on pulse or an off pulse. Furthermore, a second time limit circuit is operated by the trailing edge of the output of the first time limit circuit, and the output of the second time limit circuit is used as a control signal for the first and second relay switches. In such prior art, the output pulse width WB of the second time limit circuit must be longer than the operating time TL of the relay and smaller than the output pulse width WA of the first time limit circuit (T
L(WB(WA).Here, if the variations in WA and WB are ΔWA and ΔWB, then the worst condition to satisfy the above conditions is WB=WB+ΔWBf, and WA=WA
−ΔWA. In such a case, WB+ΔWB)WA
If it becomes 10 ΔWA, the second time limit circuit will not perform the second operation. As a result, only a control signal for turning on the first relay switch is generated during the on operation, and the control signal for turning on the first relay switch is applied to the second relay switch state during the off operation. In this state, the diode is used to conduct electricity, and only half a wave of current is passed, which may result in thermal damage to the diode. Furthermore, the pulse width WI3 must be kept below the operating time of the relay; on the other hand, if it becomes too thin, it will become unusable unless the relay has an operating time below the pulse width WB.

An object of the present invention is to solve the above-mentioned technical problem, and to provide an AC switch that allows for slight variations in the first and second time limit circuits and reliably operates the first and second relay switches. The purpose is to provide circuits.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is an electrical circuit diagram of an embodiment of the present invention.

AC power supply 1 and load 2 are connected to terminal 3 of this AC switch circuit.
．． 4 in series. A series circuit consisting of a diode 5 and a first relay switch 6 connected directly to the diode 5 is connected between the lines f3.14 connected to the terminals 3.4. This series circuit has a second
Relay switches 7 are connected in parallel.

The first relay switch 6 is associated with the first latching relay 10. The first latching relay 10 is a so-called single-winding latching relay, and has a relay coil 52. This relay coil 52 temporarily
When excited in the direction 7, the first relay switch 6 becomes conductive and mechanically maintains its conductive state. Further, when the relay coil 52 is temporarily excited in the opposite direction of the arrow 58, the first relay switch 6 is turned off and self-maintains in the off state.

A first relay drive circuit 61 is provided to drive the relay coil 52 of the first launching relay 10 once. In this first relay type circuit 61, a transistor TR1 and a transistor T serving as semiconductor switching elements
R2 are connected in series, and their connection point 53 is connected to one terminal of the relay coil 52 of the first latching relay 10. Transistor TR3 and transistor TR4 are connected in series, and their connection point 54 is connected to relay coil 5.
Connected to the other terminal of 2. Between the connection points 53 and 54,
To prevent back electromotive force of the relay coil 52, Zener diodes 59 and 60 are connected in series in opposite directions.

A N I) The output of the gate G5 is applied to the base of the inverting transistor TR5 and also to the base of the aforementioned transistor TR4. transistor TR5
The collector of is connected to the base of transistor TR1. The output of AND game 1-G6 is the transistor TR6.
When applied to the base of transistor TR2, it is connected to the base of transistor TR2. The collector of transistor TR6 is connected to the base of transistor TR3.

(AND game) When the output of G5 reaches the 1 level, transistors TR4 and TR5 become exclusive, and transistor TRI
is conductive. The output of AND game) G6 is at a low level, so transistors TR2 and TR6 are cut off. Therefore, transistor TR3 is cut off. In this way, a current path passing through the transistor TR1, the connection point 53, the relay coil 52, the connection point 54, and the transistor TR4 is formed, and current flows through the relay coil 52 in the direction of the arrow 57. Therefore, the first relay switch 6 becomes conductive and is self-maintained.

When the output from AND game (G6) becomes high level, transistors TR2 and TR6 are turned on, and transistor TR3 is turned on. A N I) The output of gate G5 is at a low level, transistors TR4 and TR5 are cut off, and transistor 'lR1 is cut off. In this way, the transistor TR3, the connection point 54, the relay coil 52,
A current path passing through the connection point 53 and the transistor TR2 is formed, and an excitation current flows through the relay coil 52 in the direction of the arrow 58, which is the opposite direction to that in the above. This causes the first relay switch to shut off and maintain itself.

The second latching relay 11 associated with the second relay switch 7 is also a single-winding latching relay like the first latching relay 10, and is provided with a second relay drive circuit 63 for driving the relay coil 62. It will be done. The second relay drive circuit 63 is configured similarly to the first relay drive circuit 61, and includes transistors TR7 to TR12 and Zener diodes 68, 69, transistors TR10,
The output of the AND gate G7 is given to the base of TR11, and the output of the AND gate G8 is given to the bases of the trench transistors 'rR8 and TR12.

When the output of AND gate G7 becomes high level, transistors TRl0. TRII becomes conductive and transistor TR
7 is conductive. The output of AND gate G8 is at a low level, so transistors TR8 and TRI2 are disconnected. Therefore, transistor TR9 is cut off. Thus transistor TR7, connection point 64, relay coil 62, connection point 65 and transistor TRl0
A current path is formed through the relay coil 62, and current flows through the relay coil 62 in the direction of the arrow 66. Therefore, the second relay switch 7 becomes conductive and self-maintained.

When the output from AND game) G8 becomes high level, transistors TR8 and TR12 become conductive, and transistor TR9 becomes conductive. AND game) The output of G7 is low level, and the transistors TRIO and TRI1
is inferred, and transistor TR7 is cut off. Thus, transistor TR9, connection point 65, relay coil 62
, a current path passing through connection point 64 and transistor TR8 is formed, and an excitation current flows through relay coil 62 in the direction of arrow 67, which is the opposite direction to that described above. This causes the second relay switch 7 to shut off and maintain itself.

When the current flowing through the relay coil 52.62 is inferred,
A voltage exceeding the supply voltage Vcc is generated in the relay coil 52.62, and the transistors TR1 to TR12
Zener diodes 59, 60,
68,. 69 is provided. Each terminal 100 is provided with a supply voltage Vcc. Here, Zener diode 59,
The breakdown voltage of 60,68.69 is the supply voltage V
c is a value exceeding the voltage of c, and the voltage of the transistor T
This is the value of the voltage at which RI to TR12 is destroyed.

AND game) When the outputs of G5 to G8 change from 71 high level to low level, relay coil 52.62
A back electromotive force is generated. At this time, relay coil 52→
Connection point 53 → Zener diode 59 → Zener diode 60 → Connection point 54 → Relay coil 52, relay coil 6
2→lLa64→Zena diode 68→Zena diode 69→Connection point 65→Relay coil 62 or vice versa, current flows through Zener diodes 59, 60, .
68.69 breaks down. zener diode 5
The back electromotive force is absorbed by the breakdown of 9, 60, 68, and 69, and therefore the transistor TRI
~TR1,2 are often destroyed.

In the off-time detection circuit 16, a series circuit consisting of a resistor 17 and a primary winding 18a of a transformer 18 is connected in parallel with the second relay switch 7. Trance 18's second best 11
A capacitor 19 and a diode 2 are connected in parallel to 18b.
0.21 is connected.

One end of the secondary winding 18b is connected to one input of the rectangular wave shaping circuit 22. The other end of the secondary winding 18b is a voltage dividing resistor 34
．． 35 tangent points. In addition, the rectangular wave shaping circuit 22
A voltage divided by voltage dividing resistors 36 and 37 is applied to the other input.

The positive rectangular pulse output from the rectangular wave shaping circuit 22 is derived as an off-time detection output every positive or negative half period. This off-time detection pulse is applied to one input of AND gate G9 and is applied to the other input of AND gate G9 via a plurality of (odd number) stages of inversion circuits 23. Here, the inverting circuit 23 and the AND gate G9 constitute a rising differentiation circuit 24. The output of the rising differential circuit 24 is given to one input of the A N I) gate G1 serving as the first gate.

A current transformer 25 is provided on the line f3 between the terminal 3 and the connection point of the first relay switch 6. The output of this current transformer 25 is input to an on-state detection circuit 26 . The on-state detection circuit 26 includes a capacitor 27, diodes 28, 29, and a square wave shaping circuit 30, similar to the off-state detection circuit 16 described above.

One terminal of current transformer 25 is connected to one input of rectangular wave shaping circuit 30 . The other terminal of the current transformer 25 is connected to the voltage dividing resistor 39,400 connection point.

In addition, a voltage dividing resistor 41 is connected to the other input of the rectangular wave shaping circuit 30.
．． A voltage divided by 42 is applied. The positive pulse from the on-time detection circuit 26 is sent to a plurality of (odd number) stage inverting circuits 3.
1 and a NOR gate G1°. The output of the falling differential circuit 33 is given to one input of the second gate AN I) G2.

Note that the positive pulse from the on-time detection circuit 26 is outputted as an on-time detection output every half cycle of either the positive or negative side.

A signal from input terminal 76 via signal control circuit 77 is applied to the other input of AND gate G1 and AND gate G2, respectively. An ON operation signal or an OFF operation signal is input to this input terminal 76. Note that instead of the rising differentiation circuit 24 and the falling differentiation circuit 33,
A circuit consisting of a capacitor and a resistor may also be provided.

In the signal control circuit 77, the signal from the terminal 76 is passed through the diodes 7B, 79, and the resistor 80. The signal is applied to a first noise removal circuit 83 via an inversion circuit 81 and an inversion circuit 82 having a waveform shaping function. In this first noise removal circuit 83, the output of the inverting circuit 82 is applied to one input of the AND gate (AND gate) through a delay circuit 86 consisting of a resistor 84 and a capacitor 85.
Gl 1 is given to the other input. The output of the first noise removal circuit 83 is given to the second noise removal circuit 90. In the second noise removal circuit 90 of B, the first noise removal circuit 83
The output of is applied to one input of OR gate G12, and also applied to the other input of OR gate G12 via a delay circuit 89 consisting of a resistor 87 and a capacitor 88.

The output of the second noise removal circuit 90 is the AND gate G13.
and is applied to one input of NOR gate G14, and also applied to the other input of ANI) gate G1.3 and NOR gate G14 via a multi-stage inversion circuit 91. ANDNO gate G1 and inversion circuit 91
The rising differential circuit 92 may be composed of a sensor and a resistor, and the falling differential circuit 93 may be composed of an inverting circuit, a capacitor, and a resistor. Both differential circuits 92.93
The output of is applied to the third monostable circuit 94 via the OR gate G1.5, and the output of the third monostable circuit 94 is applied to one input of the OR gate G16. OR gate GL
The output of the OR game G i 2 is given to the other input of 6.

The output of OR gate G16 is A N D gate G7゜G5
AND game) Gl.

Given to G4. Further, the output of OR gate G16 is passed through an inverting circuit 95 to AND gate G2. G3 and A N I) gate G6. Given to G8.

Each output of AND gate GI, G2 140 R gate G
5 to one input of AND gate G6. The output of this AND gate G6 is given to the first delay circuit DL1, and the output of the first delay circuit 1) L1 is applied to the AND gate G3. Given to G4. The output of AND gate G4 is given to one input of OR gate G17, and A, [D
The output of G3 is applied to the other input of OR gate G17 via second delay circuit DL2.

The output of the OR gate G17 is given to the first monostable circuit 100, and the output of the first monostable circuit 100 is sent to the second monostable circuit via a falling differentiator circuit 102 consisting of a plurality of inverting circuits 101 and a NOR gate G18. 103 and one input of ORG and G19. The output of the second monostable circuit 103 is OR (gu)01
9 and AND game 6
．． Given to G7. Also, the output of OR gate G19 is A
The signal is applied to the ND game 5 and G8, and is also applied to the AND game 6 via the inverting circuit 104. Note that a timer or the like may be used instead of the first monostable circuit 100. Furthermore, the falling edge differential circuit 102 may be a circuit consisting of an inverting circuit, a capacitor, and a resistor.

The operation will be explained with reference to FIG. An alternating current power having a curve shown in FIG. 2 f1+ is supplied from an alternating current power source 1 to a terminal 3. When the first and second relay switches 6.7 are cut off, an induced voltage is generated in each period of the voltage waveform of the secondary winding 18bK of the transformer 18, and due to the action of the diode 20.21, as shown in FIG. As shown in 2), a signal with a waveform in which the voltage on the forward voltage effect has been cut is applied to the rectangular wave shaping circuit 22. An off-time detection signal is derived from the rectangular wave shaping circuit 22. In response to the rise of this off-time detection signal, a clock pulse (hereinafter referred to as an on-pulse) is derived from the rise differentiation circuit 24 as shown in FIG. 2(3).

Assume that the signal applied to the input terminal 76 in this state has chatter and changes from a low level to a high level at time t1, as shown in FIG. 2(4). Clock pulses are derived from the rising and falling differentiating circuits 92 and 93 in synchronization with the rising and falling edges of such input signals, and are applied to the monostable circuit 86. In response to the input of this clock pulse, the pulse width νV3 is output from the monostable circuit 8 as shown in FIG. 2 (5).
pulses are derived. This pulse width W3 is selected to be longer than the relay operation time. Since the output of this monostable circuit 86 and the input 1 word are input to the OR gate 01'6, an input signal with chatter canceled from the OR gate 01'6 as shown in FIG. 2 (6). is output. Therefore, the AND game 1 outputs a single on-pulse as shown in FIG. 2 (7).

The on-pulse is OR gate) G5 and AND gate G
6 to the first delay circuit DLI. In the first delay circuit DLI, since the on-pulse is ahead of the load voltage in phase, the on-pulse is delayed by a delay time T1 corresponding to the phase shift time T1 required to synchronize with the positive phase of the load voltage. The output shown in Figure 2 (8) is derived. Note that the phase shift time T1 of the on-pulse is shorter than the phase shift time of the off-pulse, which will be described later.

The output of the first delay circuit DLI is AND game 4 and O
82 (+01) through G7. The monostable circuit 100 derives a pulse with a pulse width W1 as shown in FIG. 2 (11). This pulse width Wl c. 11th J This is for setting the time difference between the timings when the v-switch 6 is turned on and when the second relay switch 7 is turned on.

In response to the fall of the output of the first monostable circuit 100, a clock pulse is given to the second monostable circuit 103 as shown in FIG.
3 outputs a pulse width W2 (D pulse) as shown in FIG. 2 (13). This pulse width W2d is selected to be at least longer than the operating time of the second relay switch 7.
Pulse from monostable circuit 103 and first monostable circuit 100
A pulse with a pulse width (Wl + W2) is derived from the OR gate G19, as shown by the second rAθ4), and the AND gate G5. Given to G8. Thereby, a signal for turning on the first relay switch 6 is applied from the AND game 5 to the first relay drive circuit 61 as shown in FIG. 2 (15).

The pulse width (Vl+W2) of this signal -1 is longer than the operating time of the first relay switch 6, and the pulse width W2 is set so as to be so. As a result, the first relay switch is turned on as shown in FIG. 2 (17).

Then, AN to which the output of the second monostable circuit 103 is applied
As shown in FIG. 2 (16), a signal for turning on the second relay switch 7 is supplied from the D game G7 to the second relay drive circuit 63. As a result, the second relay switch 7 is turned on as shown in FIG. 2 (18). Load 2 is therefore energized.

As described above, a load current as shown in FIG. 2 (19) flows in response to power energization. Note that the portion indicated by diagonal lines in FIG. 2 (19) flows to the diode 5. This load voltage υ1i is 711T, which is applied to the primary winding 18a of the transformer 18.
Therefore, no electromotive force is generated in the secondary winding 18b. The output generated in the current transformer 25 is shown in Figure 2 (2+1)
As shown, the voltage is cut by the forward voltage drop by the diode 28.2=1 and is input to the rectangular wave shaping circuit 30. In response to the falling edge of the pulse output from the rectangular wave shaping circuit 30, the falling edge distribution circuit 33 outputs:
A clock pulse (hereinafter referred to as an off pulse) shown in FIG. 2 (21) is output and input to one side of the AND gate G2.

Assume that at time t2 in such a state, the input signal to the input terminal 76 changes from high level to low level with chatter as shown in FIG. 2 (4). In response to the falling edge of this input signal, a pulse with a pulse width W3 is output from the third nausea stabilization circuit 94 as shown in FIG. 2 (5). Therefore, from OR Gegu Gl 6, Figure 2 (6)
A high level signal as shown by is continuously outputted, inverted by the inverting circuit 95, and applied to the other input of the AND game 2.

Therefore, from the AND gate 2, a single off pulse is passed through the OR gate G5 and the AND gate G6 to the second pulse.
The output is as shown in figure (a).

The off-pulse is applied to the first delay circuit 1]L1, and is delayed by a delay time T1 as shown in FIG. 2 (9).

Here, the off-pulse is longer than the negative phase of the load current (
It is assumed that the phase is advanced by TI+T2). Therefore, in the first delay circuit DL1, the off-pulse is phase-shifted by the time T1 out of the off-pulse phase shift time (T1+T2). This delayed off-pulse is A N , D)G3. Given to G4. Here, since the input signal is at a low level and the output of the inverting circuit 95 is at a high level, the off-pulse delayed by the time T1 is applied to the second delay circuit DL2 via the AND gate 3.

In the second delay circuit 1) L2, the off-pulse phase shift time (T
1 + 'l' 2 ), the off-pulse is delayed by the remaining time T2, as shown in FIG. 2 (9), and is applied to the first monostable circuit 100.

The first monostable circuit 100 outputs a pulse with a pulse width W1 as shown in FIG. 2 (11) in response to the input of the off pulse, and the 241st monostable circuit 103 outputs a pulse with a pulse width W1 as shown in FIG. 2 (13). A pulse with a pulse width W2 is output. Further O
The R gate G19 outputs a pulse having a pulse width (W1+W2) as shown in FIG. 2 (14).

Therefore, first, the output of the AND game 8 reaches a high level as shown in FIG. 2(c), and a current flows in the relay coil 62 in the direction of the arrow 67. As a result, the second relay switch 7 is turned off and reset in the positive phase of the load current, that is, in the forward half cycle of the diode 5, as shown in FIG.

Then, the output of ANDG6 becomes high level as shown in FIG.
A current flows in the direction of . As a result, the first relay switch 6 is turned off and reset in the negative phase of the load current, that is, in the half period in the opposite direction of the diode 5, as shown in FIG. 2 (171).

By the above-described operation, it is possible to turn off the power to the load 2 without generating an arc.

In the above embodiment, the phase shift time of the on-pulse was set to T1, and the phase shift time of the off-pulse was set to (TI+T2).
As another embodiment of the present invention, the on-pulse phase shift time (T
1+T2), and the off-pulse phase shift time may be set to T1. In this case, an inverted input signal may be given to the AND gate G4, and an input signal may be given to the AND gate G4.

Furthermore, when the relay control signal is generated, the AND gate G6 receives an on pulse or an off pulse from the OR gate 2.
This is to ignore the output even if it is output, and is provided to prevent malfunction.

As described above, according to the present invention, there is no need to set a limit on the relay operating time, and even if the outputs of the first and second time limit circuits vary, malfunctions will not occur.

[Brief explanation of the drawing]

FIG. 1 is an overall circuit diagram of an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation. DESCRIPTION OF SYMBOLS 1... AC power supply, 2... Load, 5... Diode, 6... First relay switch, 7... Second relay switch, 24... OFF detection circuit, 33... On-time detection circuit, 100... first monostable circuit, 103...
Second monostable circuit, Gl, G2...AND gate, G
19...OR Gate agent Patent attorney Kei Nishi

Claims (1)

[Scope of Claims] Two first and second relay switches for switching loads inserted in a series circuit of an AC power source and a load and connected in parallel to each other, the first relay switch diodes are connected in series, and the ON operation of the relay switch is such that the voltage waveform of the AC power source is the first half cycle in the opposite direction of the diode.
The relay diode is turned on during the forward half cycle, and the relay switch is turned off.The above voltage waveform turns off the second relay switch during the forward half cycle of the diode, and after a delay, the first switch is turned off. In an AC switch circuit in which the diode is turned off during a half cycle in the opposite direction, an electrical change in the series circuit between the AC power supply and the load is detected when the first and second relay switches are turned off, and a positive or negative signal is detected. A circuit that outputs an on-pulse every half cycle,
and a circuit that outputs an off pulse every positive or negative half period of detecting an electrical change in the series circuit of the AC power source and the load when the first and second relay switches are turned on, The output of the first gate is output when the on-pulse matches the input signal for turning on the load, and the output of the second gate is output when the off-pulse matches the input signal for turning off the load. A signal from the gate is applied to a first timer circuit that outputs a first pulse with a predetermined first pulse width, and operates at the trailing edge of the first pulse to output a pulse with a predetermined second pulse width. An AC switch circuit characterized in that the trailing edge of the second time limit circuit and the OR output of the first and second time limit circuits are used as control signals for operating the first and second relay switches. .