JPH0424790Y2 - - Google Patents

Description

[Detailed explanation of the idea]

This invention relates to a pulse width modulation inverter that converts DC power into AC power by switching two pairs of switching elements using a switching pulse, and aims to remove odd harmonic components contained in the output voltage. In general, a pulse width modulation inverter that converts DC power into AC power of, for example, 60 Hz by switching two pairs of switching elements at, for example, several KHz based on a switching pulse, is configured as shown in FIG. 1, for example. In the figure, 1 is a DC power supply, 2 is a first NPN transistor whose collector is connected to the positive output terminal of the power supply 1,
3 is a second NPN type transistor whose collector and emitter are respectively connected to the emitter of the first transistor 2 and the negative output terminal of the power source 1; 4 is a third NPN type transistor whose collector is connected to the collector of the first transistor 2; transistor, 5 is collector,
a fourth NPN transistor whose emitter is connected to the emitter of the third transistor 4 and the emitter of the second transistor 3, 6, 7, 8;
Reference numeral 9 indicates first to fourth diodes connected in antiparallel to each of the transistors 2 to 5, and reference numeral 10 indicates a load whose both ends are connected to the emitter of the first transistor 2 and the collector of the fourth transistor 5, not shown. However, each of the transistors 2 to 5 is switched by a switching pulse from the pulse output section, and AC power is supplied to the load 10. From the pulse output section, FIG. 2 a to d
Switching pulses as shown in FIG. The half-cycle of the power supply 1 is alternately repeated, and the negative half-cycle in which a pulse train of several kilohertz (shaded in the figure b) is output by the operation of the second and third transistors 3 and 4 Direct current is converted to alternating current, and
A sinusoidal AC voltage of, for example, 60 Hz as shown by the solid line inside is applied to the load 10, and the load 10 is operated. At this time, by controlling the pulse width of the switching pulse, the voltage applied to the load 10, that is, the effective value of the inverter output voltage can be controlled. Furthermore, in order to prevent a period in which the first transistor 2 and the second transistor 3 or the third transistor 4 and the fourth transistor 5 are turned on at the same time and a so-called power supply short circuit occurs, conventionally, as shown in FIG. Between both switching pulses to the first and second transistors 2 and 3 shown in Fig. 2c and d
A dead time is provided between the switching pulses of the third and fourth transistors 4 and 5 shown in FIG. A dead time of Δt is provided between the switching pulse Q to the first and second transistors 3 so that the switching pulses to the first and second transistors 2 and 3 do not overlap. A dead time is provided between both switching pulses to 4 and 5 to prevent the two switching pulses from overlapping, thereby preventing the occurrence of a short circuit in the power supply. By the way, when the load 10 is a pure resistance load,
Since the phase of the voltage applied to the load 6 and the phase of the current flowing through the load 10 match, during the high level period t of the switching pulse P in FIG.
A high-level switching pulse is also output to transistor 5, and as shown by the arrow in FIG.
Current flows through the series circuit of the transistors 5, and during periods t and Δt in FIG. Since the pulse is at a low level, the first transistor 2 is turned off and the current to the load 10 is cut off, so that the inverter output voltage is not affected by the dead time Δt. On the other hand, if the load 10 is not a pure resistive load but a capacitive or inductive load, the phase of the voltage applied to the load 10 and the phase of the current flowing through the load 10 will not match, so the switch in FIG. During the high level period t of the switching pulse P, even if the first and fourth transistors 2 and 5 are on, the fourth diode 9, load 10,
A current with a delayed phase or an advanced phase flows through the series circuit of the first diode 6 and the power supply 1, and during period t' in FIG. 3, the second transistor 3 is turned on by the switching pulse Q in FIG. As shown by the arrow in FIG. 5b, a current with a delayed phase or an advanced phase flows through the series circuit of the fourth diode 9, the load 10, and the second transistor 3, and furthermore, during the period Δt, which is the dead time in FIG. As shown in FIG. 5b, the second transistor 3 which was on is turned off and the same current flows as in the case of the period t shown by the arrow in FIG. The pulse width of the pulse within the range where the polarity of the applied voltage and the electric current are different is substantially widened by the dead time Δt in FIG. Assuming that the phase of the current is delayed with respect to the voltage shown by the solid line in the figure e, the pulse widths of pulses P1, P2, P3, and P4 in which the polarities of the voltage and current are different are widened, and the inverter output The rising and falling parts of each positive or negative half-wave of the voltage waveform become distorted waveforms, and the positive and negative half-waves of the output voltage waveform become asymmetrical to the left and right, respectively. ,
Since the output voltage includes odd harmonic components, the odd harmonic components of the output voltage cannot be removed even if a switching pulse approximated to a sine wave is output to each transistor 2 to 5. There is. The present invention has been made with the above points in mind, and includes a pair of switching elements consisting of a first switching element and a second switching element connected in series to a DC power supply, and a switching element connected in series to the DC power supply. a third switching element and a fourth switching element, and one end of the load is connected between the first switching element and the second switching element. , the other end of the load is connected to the third
connected between the switching element and the fourth switching element, respectively switching the two pairs of switching elements with a switching pulse;
A pulse width modulation inverter that converts DC power from the DC power supply into AC power that is a combination of time-series output pulses and supplies the converted AC power to the load, stores a plurality of pulse pattern data that determines the pulse width of the switching pulse. a control section for reading desired pulse pattern data from the storage section; a plurality of preset counters to which data read from the control section is preset; and a control section for reading out desired pulse pattern data from the storage section; an output section that outputs a pulse signal having a pulse width based on the switching pulse as the switching pulse, and a detection section that detects the polarity of the voltage applied to the load and the polarity of the current flowing through the load, and the detected polarities are different. The present invention provides a pulse width modulation inverter comprising: a change command section that changes data read from the storage section by the control section so that the pulse width of the output pulse is shortened. Therefore, according to the pulse width modulation inverter of this invention, the power of the DC power source can be increased by combining the time-series output pulses formed by the switching operations (for example, several KHz) of two pairs of switching elements.
When converting to Hz AC power and supplying it to a load, if the voltage waveform is distorted so that the voltage and current of the AC power are out of phase due to an inductive load etc. and the dead time is shortened, the part where this distortion occurs will be Based on the mismatch between the detection polarities of the voltage and current of the detection unit, the actual waveform shift can be accurately detected using a simple method without performing complex detection such as phase difference detection. Furthermore, based on the detection results of voltage waveform distortion,
The switching pulse is corrected so that the pulse width of the output pulse is shortened, and the waveform distortion of the output voltage is accurately corrected. Therefore, it is possible to accurately correct waveform distortion of the output voltage with simple detection, and even if the load is capacitive or inductive, the pulse width of the switching pulse to each switching element can be controlled to adjust the inverter output voltage. Odd harmonic components included in the output voltage of the inverter can be removed by making the positive and negative half-wave waveforms symmetrical. Next, this invention will be explained in detail with reference to the drawings from FIG. 6 showing one embodiment thereof. First, in Fig. 6, 11 is a DC power supply, 12
is a switching element section which is composed of two pairs of switching elements such as transistors on the positive side and negative side, and constitutes the pulse width modulation inverter 13 together with the power supply;
14 is a load connected to the element section 12; 15 is a current transformer provided in the connection line between the element section 12 and the load 14 to take out the load current flowing through the load 14; and 16 is a current transformer connected to the current transformer 15. A first detection unit detects the polarity of the load current taken out by 15 and outputs a detection signal of logic “1” and “0” when the polarity is positive and negative, respectively; 17 is connected to the load 14; 18 is a pulse output section, which detects the polarity of the load voltage and outputs a detection signal of logic "1" and "0" when the polarity is positive and negative, respectively. A switching pulse having a predetermined pulse width is outputted to each switching element of the element section 12 based on the detection signals from the elements 16 and 17. Next, FIG. 7 showing the configuration of the pulse output section 18 will be explained. In the figure, 19 is a reference pulse oscillator that outputs a reference pulse signal with a frequency φ1 as an operating clock, and 20 is a first pulse oscillator that divides the frequency of the pulse signal and outputs a divided pulse signal with a carrier frequency φ2 of several KHz. A frequency divider 21 further divides the frequency of the frequency-divided pulse signal and outputs a fundamental frequency pulse signal having a fundamental frequency φ3 of 60 Hz, for example, a second frequency divider 22
23 is a monostable multivibrator that outputs an interrupt signal based on the frequency-divided pulse signal; 23 is an element section 12;
24 is a central processing unit (hereinafter referred to as CPU), which is a storage unit that stores in advance a plurality of pulse pattern data that determines the pulse width of the switching pulse to the switching element. via ROM2
3, and reads desired pulse pattern data stored at an address corresponding to the address data via the data bus 26. 27 is an address bus 25 and a data bus 26
interface circuits 28, 29, 30, which receive address data and pulse pattern data from the CPU 24 via the CPU 24, and transfer command signals from a change command unit (described later) to the CPU 24;
Reference numeral 31 designates first to fourth preset counters (hereinafter referred to as "counters") to which pulse pattern data via the interface circuit 27 is preset, and the reference pulse signal and the reference pulse signal are input to each counting input terminal and transport input terminal. The frequency-divided pulse signals are respectively input, and each pulse pattern data from the CPU 24 is preset and counted for each interrupt signal. 32 and 33 connect the first and third counters 28 and 30 to the set terminal S, respectively.
The counter signals from the second and fourth counters 29 and 31 are input to the reset terminal R of the first and second set reset flip-flops (hereinafter referred to as FF). ), 34 is an inversion circuit that inverts the fundamental frequency pulse signal from the second frequency divider 21 and outputs an inverted pulse signal, and 35 is an interface circuit 2 to which both detection signals from both detection sections 16 and 17 are input.
Exclusive or gate, 36, is a change command unit that outputs a command signal to the CPU 24 via 7.
is an output section, into which the output signals from both FFs 32 and 33, the fundamental frequency pulse signal from the second frequency divider 21, and the inverted pulse signal from the inverting circuit 34 are inputted, and are respectively applied to each switching element of the element section 12. A switching pulse having a predetermined pulse width is output, and the pulse output section 18 is constituted by a circuit surrounded by a chain line in FIG. Then, the vibrator 22 is activated by the CPU 24.
Of the pulse pattern data stored in the ROM 23 for each interrupt signal from the element section 12
one of the switching elements on the positive side of, for example, the first
A plurality of first and second data, respectively, which determine the rise time and fall time of the switching pulse to the transistor 2 in the figure, and one of the negative side switching elements of the element section 12, for example, the transistor 3 in FIG. A plurality of pieces of third and fourth data defining the fall time and rise time of the switching pulse are read out, and each of the read data is sent to each of the counters 28 to 31 via the interface circuit 27. Each preset data is counted by the reference pulse signal. Next, when each counter 28-31 finishes counting each data, each counter 28-31
The counter signals are sequentially outputted to the set terminal S and reset terminal R of the first FF 32 and the set terminal S and reset terminal R of the second FF 33, respectively, and the signals S1 and S1 are output from both FFs 32 and 33 to the output section 36, respectively.
S2 is output, and the fundamental frequency pulse signal from the second frequency divider 21 and the inverted pulse signal from the inversion circuit 34 are output as signals S3 and S4 to the output section 36, and each output terminal of the output section 36 According to the truth table shown in Table 1, the signals S5, S6, S7,
S8 is output. In addition, the signal S7,

[Table] S8 is equal to the signals S4 and S3, respectively, and in Table 1, "0" indicates the low level of the output signal, and "1" indicates the high level of the output signal. By the above operation, the pulse of the signal S5 based on certain data preset in the first and second counters 28 and 29 has a rise time within the range of the period Φ2, as shown in FIG.
ta, fall time tb, pulse width T (=tb - ta), and like the above pulse, a signal consisting of a plurality of pulses based on each data preset in the first and second counters 28 and 29. S5 is element part 1
For example, the signal S7 is outputted to one of the positive side switching elements of 2, and the signal S7 is outputted to the other of the positive side switching elements, and is preset to the third and fourth counters 30 and 31 in the same manner as above. A signal S6 consisting of a plurality of pulses based on each data is outputted to one of the negative side switching elements of the element section 12, and the signal S8 is outputted to the other of the negative side switching elements,
These operations are repeated, and a pulse signal consisting of a plurality of pulses approximated to a sine wave as shown in FIGS. 2a to d is output to each of the switching elements, and the positive side and negative side switching elements The DC power of the power source 11 is converted into AC power and supplied to the load 14 by switching alternately. Next, both the detection units 16 and 17 detect the load 14
The polarity of the load current flowing through the load 14 and the polarity of the load voltage applied to the load 14 are detected, and there is no distortion in the waveform of the load voltage, and the detection signals from both detection units 16 and 17 are both logic "1" or "0". When
That is, when the polarities are the same, the command signal output from the gate 35 becomes logic "0", and the first data and third data read from the ROM 23 by the CPU 24 are not changed and are output from the output section 36. The pulse width of the switching pulse approximated to a sine wave to each switching element of the element section 12 is not changed. On the other hand, when the waveform of the load voltage is distorted and the polarity is different, and the logic of the detection signals from both detection sections 16 and 17 is different, the command signal output from the gate 35 becomes logic "1", and the CPU 24
Among the data read from the ROM 23, the data that determines the pulse width of the pulses whose polarities are within different ranges is outputted from the output section 36 by the signals S5,
Among the pulses of S6, the rising and falling portions of the pulses having different polarities are changed to be shortened by the dead time Δt, and are outputted from the output section 36 as shown in FIG. The pulse width of each pulse of the signal S5 is shortened by the dead time 2·Δt, and the pulse width of each pulse of the signal S6 is also shortened by the dead time 2·Δt.
, the pulse widths of the pulses of the signals S5 and S6 within a range in which the polarities of the load current and the load voltage are different are controlled to be short, and the switching times of the first and second transistors 2 and 3 are controlled. Both positive and negative half waves of the load voltage, that is, the output voltage of the inverter 13, are corrected symmetrically. Therefore, according to the embodiment, the detection units 16 and 17 are provided to detect the polarity of the voltage applied to the load 14 and the polarity of the current flowing through the load 14, and when the polarities are different, the CPU 24 detects the By providing the exclusive or gate 35 that changes the pulse pattern data to be read so that the pulse width of the switching pulse from the output section 36 becomes smaller, each switching By controlling the pulse width of the switching pulse to the element, it is possible to correct the positive and negative half-wave waveforms of the inverter output voltage so that they are accurately symmetrical, thereby correcting waveform distortion. Odd harmonic components contained in can be easily removed.

[Brief explanation of drawings]

Figure 1 is a wiring diagram of the basic circuit of a conventional pulse width modulation inverter, Figures 2 a to e are timing charts for explaining the operation of Figure 1, Figure 3 is a waveform diagram of part of the switching pulse, Figures and Figures 5a, b
is an explanatory diagram of the operation of FIG. 1, FIG. 4 is a diagram showing the current flowing through the load when the load in FIG. 1 is a purely resistive load, and FIGS. Figure 6 is a diagram showing the current flowing through the load in different states when the load is an inductive load.The following drawings show an embodiment of the pulse width modulation inverter of this invention. This figure is a connection diagram of the pulse output section in FIG. 6, and FIG. 8 is a waveform diagram of a part of the switching pulse outputted from the output section in FIG. 7. 11...DC power supply, 12...Switching element section, 13...Pulse width modulation inverter, 14...
Load, 16, 17...first, second detection section, 23...
...ROM, 24...CPU, 28-31...1st-
4th counter, 35...exclusive or gate, 36...output section.

Claims (1)

[Claims for Utility Model Registration] A pair of switching elements consisting of a first switching element and a second switching element connected in series to a DC power supply, a third switching element connected in series to the DC power supply, and a fourth switching element. a pair of switching elements consisting of a switching element; and two pairs of switching elements consisting of, one end of the load is connected to the first switching element and the second switching element.
The other end of the load is connected between the third switching element and the fourth switching element, and each of the two pairs of switching elements is switched by a switching pulse to generate DC power from the DC power supply. in a pulse width modulation inverter that converts the output pulses into alternating current power that is a combination of time-series output pulses and supplies the converted alternating current power to the load, the storage unit storing a plurality of pulse pattern data that determines the pulse width of the switching pulse; a control section for reading out desired pulse pattern data from the control section; a plurality of preset counters to which the data read from the control section are preset; and a pulse signal having a pulse width based on the data preset in each of the counters. an output section that outputs the switching pulse; a detection section that detects the polarity of the voltage applied to the load and the polarity of the current flowing through the load; and a detection section that detects the polarity of the voltage applied to the load and the polarity of the current flowing through the load; A pulse width modulation inverter comprising: a change command section that changes data read from a storage section so that the pulse width of the output pulse becomes shorter.