JPS6260916B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inverter device that converts DC power to AC power, and more particularly to a control device for semiconductor switches used in the inverter.

As a device for converting DC power into AC power, there is generally an inverter device that uses semiconductor switches such as transistors and thyristors.

FIG. 1 shows a conceptual diagram of the basic circuit of a bridge type inverter. In Figure 1, X,,Y,
are switches modeled after semiconductor switches. Figure 2 explains the operation of this circuit. When signals X', ', Y', ' exist, the corresponding switches X,, Y,
is in the "on" state, and when the signal is zero, the switch is "off". The signals X′ and ′ or Y′ and ′ are complementary to each other, and the signals never exist at the same time. Therefore, the arm including the switch X and the arm including the switch Y of the bridge inverter do not form a short circuit for the DC power source E.

DC voltage E is applied to load Z during a period when signals X' and ' or ' and Y' exist simultaneously.
The period during which these signals X′ and ′ exist and the signal ′ and
During the period when Y' exists, the polarity of the voltage applied to the load Z is different. That is, an alternating current voltage is applied to the load Z. Figure 2e shows the voltage across this load. signals X′ and ′, or
By changing the period θ during which ' and Y' exist simultaneously, the effective value of the AC voltage e can be adjusted.

The disadvantage of this conventional inverter control is that the AC voltage e contains a large proportion of low-order harmonic components such as the 3rd, 5th, and 7th harmonics, so in order to sine this AC voltage, A large-scale AC filter is required. This not only increases the size and weight of the device, but also has negative electrical consequences such as deterioration of voltage temperature characteristics and reduction in efficiency.

The present invention solves these drawbacks by controlling a semiconductor switch of a bridge inverter to generate multiple pulses to eliminate lower harmonics during a half cycle of the fundamental voltage. It is.

FIG. 3 is a drawing for explaining the present invention. The signals X′, ′, Y′, ′ are the first
The semiconductor switch of the bridge inverter shown in the figure,
, Y, is "on". e is the voltage waveform applied to the load Z in the figure, that is, the AC output voltage of the bridge inverter. Output voltage e
is obtained when signals Y′ and ′ and ′ and X′ exist simultaneously, and the polarities of the pulses are different for both. The pulses within a half cycle of the output voltage e are similar to the pulses of the signals Y',', respectively.

In the present invention, the effective value of e can be adjusted and lower harmonics can be suppressed by turning the semiconductor switch Y on and off as shown in A ₁ to D ₅ and appropriately selecting the timing.

The number of commutations within a half cycle of the fundamental wave AC is 2n times, and the commutation position is symmetrical with respect to the center (π/2) within the half cycle of the fundamental wave AC. That is, each commutation position A _k , B _k , C _k , D _k
has the following relationship.

When the output AC voltage of this pulse width modulation type inverter is Fourier expanded, However, E is the amplitude of the pulse voltage, (2m-1) is the harmonic order, ω is the angular frequency of the fundamental alternating current, and t is the time. A _k is each commutation position A ₁ between 0 and π/2
~ _A4 .

In equation (2), the amplitude of the (2m-1)th harmonic voltage is as follows.

In equation (3), (n-1) low-order harmonics are 0
When the amplitude of the fundamental AC voltage is E x,
The simultaneous nonlinear equations in equation (4) are 0<A ₁ <A ₂ <……
It is possible to solve with A _o <π/2.

In this equation, E(3), E(5), and E(7) are each set to 0 when n=4, and A _k is shown in FIG. 4 when x is varied from 0.6 to 1.0.

FIG. 5 shows an embodiment in which the signals X', ', Y', ' of FIG. 3 are obtained. FIG. 6 is a time chart showing the outputs of each part of the circuit shown in FIG.

The oscillator 1 corresponds to the resolution of commutation timing, and has a frequency 2 ^N times the fundamental AC frequency F (F×
^2N ). This oscillator 1
Output a enters timing counter 2. Timing counter 2 is a 2 ^N- ary counter, so the most significant bit output b (Figure 6) is the same as in Figure 3.
It corresponds to X′, and its negation h corresponds to ′. In the storage devices 7 to 10, each commutation position {A _k (rad), k=1, 4} from 0 to π/2 and the frequency 2 ^N of the oscillator 1 corresponding to the fundamental AC frequency F are used. 2 ^N ×A _k /2π, and x in Figure 4 is the desired minimum value x _n
From _{i o} to the desired maximum value x _nax is stored with slight changes Δx. That is, each storage device 7 to 10 is
It is stored as a variable starting from 0° for a plurality of pre-calculated commutation points. Also,
The number of bits in one word of each of the above storage devices is (N-2), and the number of words W is as shown in the following equation.

W=x _nax −x _nio /Δx (5) The voltage indicating device 11 specifies the magnitude of the fundamental AC voltage. That is, the addresses of the storage devices 7 to 10 are specified by the voltage indicating device 11. As a result, the value of each commutation position 2 ^N × A _k /2π corresponding to the fundamental AC voltage is the indicated signal n ₁ to n
Output in ₄ . The data selector 6 selects a specified one of the outputted n ₁ to _{n 4} . The input designation of the data selector 6 is performed by the output signals r and s of the exclusive OR gates 12 and 13, and when r=0 and s=0, _n1 and r=
1, when s=0, use n ₂ ; when r=0, s=1, use n ₃ ; when r=1, s=1, use n ₄ , and so on. The output m of the data selector 6 enters the latch circuit 5. This latch circuit 5 is functionally divided into two periods: a data reading period and a data holding period. During the data reading period, when the output u of the comparison/judgment circuit 4 is received, or when one of the outputs t of the timing counter 2 is received, When falls, the output m from the data selector 6 is read for the time specified by the monostable circuit 16. That is, in circuit 5,
The value to be commutated is then preset. By comparing and determining this value with the count value of the timing counter 2, the comparator circuit 4 can output an output u at the commutation position as shown in FIG. In order to maintain symmetry between 0 and π/2 and between π/2 and π, the exclusive OR gates 3 ₀ to 3 _o-3 have an up count ( It operates like a down count (subtraction count) between π/2 and π.
This results in symmetry at π/2 and 3/2π. The monostable circuit 17 is included for initial start and to prevent malfunction, and operates at the falling edge of the output t to reset the flip-flop 14. The flip-flop 14 is inserted to generate the selection signal s of the data selector 6 mentioned above.
Exclusive or gates 12 and 13 are similar to exclusive or gates ₃₀ to _3o-3 ,
This was added to obtain symmetries of 0 to π/2 and 2/π to π. By performing the following logical operation on the output d of the flip-flop 14 and the value of the highest bit b of the timing counter 2, Y',' as shown in FIG. 3 can be obtained.

′=b・d+・Y′=(′) The inverters 18, 19,
23, a logic circuit composed of AND gates 20 and 21 and an OR gate 22.

As explained above, according to the present invention, optimal values at a plurality of pre-calculated commutation points suitable for reducing specific harmonics are stored as variables from an electrical angle of 0°, and Since the configuration is such that the inverter is controlled by sending a semiconductor switch control signal corresponding to the optimum value of the commutation point determined by /2, the circuit operation can be simplified, and no matter what kind of data is to be stored, it can be handled simply by rewriting the contents of the storage device.

Furthermore, the inverter device can control the output voltage of the bridge inverter and at the same time suppress the low-order harmonic components contained in it, making the device smaller and lighter, and with improved electrical characteristics such as transient characteristics and efficiency. can get.

[Brief explanation of the drawing]

Figure 1 is a model circuit diagram of a bridge inverter.
FIG. 2 is a time chart for explaining the conventional control operation of a bridge inverter. FIG. 3 is a time chart for explaining the present invention, FIG. 4 is a graph showing commutation positions implemented in the present invention, and FIG. 5 is a circuit diagram showing an embodiment of the present invention.
FIG. 6 is a time chart showing output signals of each part of the circuit shown in FIG. 1: Oscillator, 2: Counter, ₃₀ to 3 _o-3 : Exclusive OR gate, 4: Comparison circuit, 5:
latch circuit, 6: data selector, 7 to 10: memory device, 11: voltage indicating device, 12, 13: exclusive OR gate, 14: flip-flop, 15: flip-flop, 16: monostable circuit.

Claims (1)

[Claims] 1. A reference pulse oscillator that outputs a reference pulse signal, a frequency divider that divides the reference pulse into a signal of a predetermined width, and a plurality of pre-calculated commutations suitable for reducing specific harmonics. a storage device that stores the optimum value at a point in time as a variable from an electrical angle of 0°;
A voltage indicating device that indicates the ratio of the fundamental wave component of the AC output voltage to the input DC voltage of the inverter, and an optimum value at the time of commutation corresponding to the ratio of the main wave component of the AC output voltage difference indicated by the voltage indicating device. and a readout control device for controlling readout of the inverter from the storage device, and controlling the inverter by sending out a semiconductor switch control signal corresponding to the optimum value at the commutation point read by the readout control device. Invar control device.