JP2554984Y2 - Switching signal generation circuit for inverter - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-phase full-bridge type switching signal generating circuit for an inverter used in an inverter for converting DC power to AC power.

[0002]

2. Description of the Related Art Inverters for converting DC power into AC power are widely used as components of frequency converters and DC transformers of industrial equipment and electronic equipment. For example, AC power obtained from a commercial power supply is converted by a converter. The power is converted into DC power, and the DC power is converted into AC power of an arbitrary frequency by an inverter and used for rotation control of an AC motor and the like.

[0003] The above-mentioned inverters are used in a single-phase full-bridge type or a multiplex type according to the purpose of use. In the case of a single-phase full-bridge type inverter, as shown in FIG. A pair of switch members 52a and 52b such as a thyristor element connected to the positive electrode of the DC power supply 51 and a pair of switch members 52c connected to the negative electrode of the DC power supply 51.
DC power is cut off by controlling the open / close state with the switch 52d, and the length of the cut-off time makes the switch member 5
Load 53 provided between 2a, 52b, 52c, and 52d
Is converted into an AC state. And these switch members 52a, 52b, 5
A switching signal generation circuit for an inverter is usually used for opening and closing the 2c and 52d.

Generally, as shown in FIG. 7, an inverter switching signal generating circuit generates modulated wave data a and a having ideal AC waveforms and triangular wave data b and c having 180 ° phases different from each other. And switch members 52a, 52b, 52c, 52d based on these comparison results.
Open / close signals s1, s2, s3, and s4 for controlling the opening and closing of.

That is, as shown in FIG. 8, a conventional switching signal generating circuit for an inverter uses a JK flip-flop circuit 54 to which an inverted clock signal ck is input.
And a 3-bit output UP / DOWN counter circuit 55 connected to the JK flip-flop circuit 54.
And a comparison section 56 connected to the UP / DOWN counter circuit 55 and forming the open / close signals s1, s2, s3, and s4. Then, the UP / DOWN counter circuit 55
As shown in FIG. 9, the triangular wave data b is output by adding and subtracting the clock signal ck, and when the maximum value and the minimum value are reached, the switching signal rc is switched to the J terminal and the K terminal of the JK flip-flop circuit 54. And the UP / DOWN signal u from the Q terminal of the JK flip-flop circuit 54
By inverting d, the operation of subtracting and adding the clock signal ck and outputting the triangular wave data b is repeated.

[0006] Further, as shown in FIG.
As shown in Table 1, the comparison unit 56 to which the triangular wave data b is input from the N counter circuit 55 is connected to a comparator 57 to which the triangular wave data b and the modulated wave data a are input, and the phase is inverted by 180 °. And a comparator 58 to which the shifted triangular wave data c and the modulated wave data a are input.

[0007]

[Table 1]

Then, as shown in FIG. 11, the comparator 56 compares the triangular wave data b with the modulated wave data a by a comparator 57, and when the modulated wave data a is larger than the triangular wave data b, To the latch circuit 5
9 and the switching signals s1 and s2 from the latch circuit 59.
The comparator 58 compares the inverted triangular wave data c with the modulated wave data a, and latches the comparison signal c2 when the modulated wave data a is larger than the triangular wave data c. The switching circuit s3 outputs the opening / closing signals s3 and s4 from the latch circuit 60.

[0009]

However, in the above-described conventional switching signal generating circuit for an inverter, since the triangular wave data b is formed by the UP / DOWN counter circuit 55 having a complicated internal configuration, the number of gates is increased. There is a problem that the integration is greatly restricted. In particular, when the resolution of the triangular wave data b is increased,
The UP / DOWN counter circuit 55 becomes more complicated, and the restriction on integration becomes remarkable.

Therefore, in the present invention, the open / close signal s1
An object of the present invention is to provide a switching signal generation circuit for an inverter that can solve the above problem by forming s2, s3, and s4 using a normal counter having a simple internal configuration.

[0011]

SUMMARY OF THE INVENTION A switching signal generating circuit for an inverter according to the present invention is used in an inverter which converts DC power into AC power by shutting off DC power by opening and closing a switch member in order to solve the above problems. And has the following features.

That is, the switching signal generating circuit for the inverter is a comparing means for forming an opening / closing signal of the switch member on the basis of the increased sawtooth data or the reduced sawtooth data, which is the normal sawtooth data, and the modulated wave data. It has a comparing section and a normal counter circuit which is a sawtooth data forming means for outputting normal sawtooth data to the comparing means. And
The comparing means compares the normal sawtooth data with the modulated wave data and outputs a normal comparison signal, and compares the inverted sawtooth data obtained by inverting the normal sawtooth data with the modulated wave data. A comparator and a NOT circuit serving as a sawtooth data comparison unit for outputting an inversion comparison signal, and a latch signal while switching between the normal comparison signal and the inversion comparison signal when the normal sawtooth data reaches a predetermined value. It is characterized by comprising a selector circuit which is a selector section for outputting, and a latch circuit which is an open / close signal forming section for outputting an open / close signal based on the latch signal.

[0013]

According to the above arrangement, the switching signal generating circuit for the inverter can form the opening / closing signal by using the increasing sawtooth data and the decreasing sawtooth data which are the normal sawtooth data. Therefore, since the sawtooth wave data forming means can use a normal counter circuit having a simpler circuit configuration than the UP / DOWN counter circuit, restrictions on integration are small.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 3, the inverter switching signal generating circuit according to the present embodiment has a normal counter circuit 1 which is a sawtooth data forming means. The normal counter circuit 1 adds the clock signal ck to the CK terminal 1a to which the clock signal ck is input, the initial value input terminal 1b to which the n-bit initial value '1' is input, and the n-bit normal value. A sawtooth output terminal 1c for outputting increased sawtooth data d as sawtooth data, an RC terminal 1d for outputting a switching signal rc when the increased sawtooth data d reaches a predetermined maximum value, and a switching signal LOAD for setting increased sawtooth wave data d to initial value '1' when rc is input
And a terminal 1e.

The above-mentioned LOAD terminal 1e and RC terminal 1
d is connected to the J terminal 2a and the K terminal 2b of the JK flip-flop circuit 2. The JK flip-flop circuit 2 has a CK terminal 2c to which the clock signal ck inverted by the NOT circuit 3 is input, and a Q terminal 2d to output the latch switching signal q.
Switches between the H level and L level output states according to the H level switching signal rc input to the LOAD terminal 1e and the RC terminal 1d and the rising edge of the clock signal ck.

The Q terminal 2d of the JK flip-flop circuit 2 is connected to a comparing section 4 as comparing means.
The latch section switching signal q from the Q terminal 2d is input to the comparing section 4. Also, this comparison unit 4 includes:
The increased sawtooth wave data d from the above-described normal counter circuit 1 and the clock signal c inverted by the NOT circuit 3
k, and modulated wave data a which is an ideal AC waveform (see FIG. 7) are input.

As shown in FIG. 1, the comparing section 4 includes a sawtooth data comparing section including comparators 5 and 6 and a NOT circuit 7, a selector section including selector circuits 8 and 9, and a latch circuit 10. And an open / close signal forming unit 11.

That is, the comparing section 4 includes a comparator 5 having a pair of n-bit input terminals 5a and 5b and an output terminal 5c. One of the input terminals 5a of the comparator 5 has an increased sawtooth wave. Data d is input, and modulated wave data a is input to the other input terminal 5b. The comparator 5 compares the modulated wave data a with the increased sawtooth data d, and when it determines that the modulated wave data a has a larger value than the increased sawtooth data d, the comparator 5 outputs the value from the output terminal 5c. A comparison signal c1, which is an H-level normal comparison signal, is output.

The comparator 4 also has a comparator 6 similar to the comparator 5 described above, and the comparator 6 operates as an inverted sawtooth wave data obtained by inverting the increased sawtooth data d by a NOT circuit 7. Is input to one input terminal 6a, and the modulated wave data a is input to the other input terminal 6b. The comparator 6 compares the modulated wave data a with the reduced sawtooth data e. When it is determined that the modulated wave data a has a larger value than the reduced sawtooth data e, the comparator 6 outputs the signal from the output terminal 6c. A comparison signal c2, which is an H-level inverted comparison signal, is output.

The output terminal 5c of the comparator 5 is connected to an E terminal 8a of the selector circuit 8 and an F terminal 9a of the selector circuit 9.
b while the output terminal 6c of the comparator 6 is
F terminal 8b of selector circuit 8 and E terminal of selector circuit 9
It is connected to terminal 9a.

These selector circuits 8 and 9 correspond to the above E
In addition to the terminals 8a and 9a and the F terminals 8b and 9b, it has E / F terminals 8d and 9d and G terminals 8c and 9c.

The above selector circuits 8 and 9 will be described in detail. As shown in FIG.
The circuit comprises a T circuit 14, two-input AND circuits 12 and 13, and a two-input OR circuit 15.
E terminals 8a and 9a and F terminals 8b and 9b are connected to one of the input terminals. E / F terminals 8 d and 9 d are connected to the other input terminal of the AND circuit 12 via a NOT circuit 14, and the E / F terminals 8 d and 9 d are connected to the other input terminal of the AND circuit 13. Is also connected. Then, the AND circuits 12 and 13
Are connected to the input terminals of the OR circuit 15, and the output terminal of the OR circuit 15 is connected to the G terminal 8c.
9c.

As shown in FIG. 1, the selector circuits 8 and 9 output the H level latch switching signal q to the E / F terminal 8d.
When input to 9d, the same latch signals g1 and g2 as the signal states of the E terminals 8a and 9a are output from the G terminals 8c and 9c, while the L-level latch switching signal q is set to E / When input to the F terminals 8d and 9d, the latch signals g1 and g2 are the same as the signal states of the F terminals 8b and 9b.
Are output from the G terminals 8c and 9c.

The G terminals 8c of the selector circuits 8 and 9
9c is a D terminal 10a / 11a of the latch circuit 10/11.
It is connected to the. These latch circuits 10 and 11
CK terminal 10 to which inverted clock signal ck is input
Q terminals 10c and 11 that switch the output states of the open / close signals s1 and s3 according to the signal states of the latch signals g1 and g2 and the rising edge of the clock signal ck.
c, and Q terminals 10d and 11d that output opening / closing signals s2 and s4 having phases opposite to the output states of the Q terminals 10c and 11c.

The operation of the inverter switching signal generating circuit in the above configuration will be described. For convenience of explanation, the switching signal generation circuit for the inverter is
It is assumed that sawtooth wave data de and e and modulated wave data a of 3 bits are used.

As shown in FIGS. 3 and 4, the normal counter circuit 1 outputs the initial value '1' of the input terminal 1b as sawtooth wave data d from the sawtooth output terminal 1c.
When the clock signal ck is input to the CK terminal 1a of the normal counter circuit 1, the added value is output as increased sawtooth data d each time the clock signal ck is input. Then, the increased sawtooth data d is “7”, which is the highest value of 3 bits.
Is reached, a pulse-like switching signal rc is output from the RC terminal 1d.

The switching signal rc is supplied to the LOAD terminal 1e.
, And the increased sawtooth data d of the normal counter circuit 1 is reset to the initial value “1”.

The switching signal rc is also input to the J terminal 2a and the K terminal 2b of the JK flip-flop circuit 2, and the JK flip-flop circuit 2
Based on this switching signal rc and the rising edge of the clock signal ck inverted by the NOT circuit 3, the output state of the latch switching signal q is inverted.

The latch switching signal q output from the JK flip-flop circuit 2 and the increased sawtooth wave data d output from the normal counter circuit 1 are input to the comparator 4. As shown in FIGS. 1 and 2, the increased sawtooth data d of the comparator 4 is input to one input terminal 5 a of the comparator 5 and is input to the NOT circuit 7. Then, as shown in Table 2, the increased sawtooth data d input to the NOT circuit 7 is output as the reduced sawtooth data e in which each bit is inverted, and then is output to one input terminal 6a of the comparator 6. Will be entered.

[0031]

[Table 2]

The other input terminal 5b of the comparators 5 and 6
6b, modulated wave data a · a is input,
The comparators 5 and 6 compare the increasing and decreasing sawtooth data de and e input to one input terminal 5a and 6a with the modulated wave data a and a input to the other input terminals 5b and 6b. When the modulated wave data a · a is larger than the increasing and decreasing sawtooth wave data de · e, the H level comparison signal c1
While the c2 is output from the output terminals 5c and 6c, when the modulated wave data aa is less than the increasing and decreasing sawtooth data de, the L level comparison signals c1 and c2 are output from the output terminals 5c and 6c. Will be output.

The comparison signal c output from the comparator 5
1 is input to the E terminal 8a of the selector circuit 8 and the F terminal 9b of the selector circuit 9, and the comparison signal c2 output from the comparator 6 is
The signal is input to the terminal 8b and the E terminal 9a of the selector circuit 9. At this time, the E / F terminals 8d and 9d of the selector circuits 8.9 are connected to the JK flip-flop circuit 2 of FIG.
, A latch switching signal q is input from a Q terminal 2d of
The selector circuits 8 and 9 select the E terminals 8a and 9a and the F terminals 8b and 9b according to the signal state of the latch switching signal q.

That is, when the latch switching signal q is at the H level, the selector circuit 8 outputs the comparison signal c1 inputted to the E terminal 8a as the latch signal g2 from the G terminal 8c, and the selector circuit 9 outputs the latch signal g2. The comparison signal c2 input to 9a is output from the G terminal 9c as the latch signal g1. On the other hand, when the latch switching signal q is at the L level, the selector circuit 8 outputs the comparison signal c2 input to the F terminal 8b as the latch signal g2 from the G terminal 8c, and the selector circuit 9 inputs the comparison signal c2 to the F terminal 9b. The comparison signal c1 thus output is output from the G terminal 9c as the latch signal g1. As a result, the latch signals g1 and g2 output from the selector circuits 8 and 9 are, as shown in Table 2, the comparison signals c1 and c2 are alternately switched by switching the signal state of the latch switching signal q. Becomes a signal state equivalent to the signal processed by the comparators 5 and 6.

Thereafter, the latch signals g1 and g2 are
The signals are input to the D terminals 10a and 11a of the latch circuits 10 and 11, and the latch circuits 10 and 11 receive the open / close signals s1 and s1 based on the latch signals g1 and g2 and the rising edge of the inverted clock signal ck. The output states of s2, s3, and s4 are switched.

As described above, the switching signal generating circuit for the inverter according to the present embodiment can control the output states of the open / close signals s1, s2, s3, s4 using the increased sawtooth data d. It is possible to employ a normal counter circuit 1 having a simpler circuit configuration than the UP / DOWN counter circuit described above. Therefore, this inverter switching signal generation circuit has a small restriction when integrated.

In this embodiment, the comparing section 4 forms the decreasing sawtooth data e based on the increasing sawtooth data d output from the normal counter circuit 1, and further generates the open / close signal s.
1 ・ s2 ・ s3 ・ s4 are formed,
The present invention is not limited to this, and the comparing section 4 may form the open / close signals s1, s2, s3, s4 based on the reduced sawtooth data output from the normal counter circuit 1. However, in this case, the predetermined value needs to be the minimum value of the reduced sawtooth data.

[0038]

As described above, the switching signal generating circuit for an inverter according to the present invention is used for an inverter that converts DC power into AC power by opening and closing a switch member to open and close the switch member. It has a comparing means for forming the open / close signal based on the normal sawtooth data and the modulated wave data, and a sawtooth data forming means for outputting the normal sawtooth data to the comparing means. The comparing means compares the normal sawtooth data with the modulated wave data to output a normal comparison signal, and compares the inverted sawtooth data obtained by inverting the normal sawtooth data with the modulated wave data. A sawtooth wave data comparing section for outputting an inverted comparison signal, and a selector section for switching the normal comparison signal and the inverted comparison signal to each other when the normal sawtooth data reaches a predetermined value and outputting the same as a latch signal; An opening / closing signal forming section for outputting an opening / closing signal based on a latch signal is provided.

Thus, the open / close signal can be formed by using the increasing sawtooth data and the decreasing sawtooth data which are the normal sawtooth data, so that a normal counter circuit having a simpler circuit configuration than the UP / DOWN counter circuit can be provided. The present invention can be used for the sawtooth wave data forming means, and as a result, there is an effect that restrictions on integration can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a comparison unit in a switching signal generation circuit for an inverter according to the present invention.

FIG. 2 is a timing chart of a comparison unit.

FIG. 3 is a circuit diagram of a switching signal generation circuit for an inverter.

FIG. 4 is a timing chart of an inverter switching signal generation circuit.

FIG. 5 is a circuit diagram of a selector circuit.

FIG. 6 is an explanatory diagram of an inverter.

FIG. 7 is an explanatory diagram of an operation state of the inverter switching signal generation circuit.

FIG. 8 is a circuit diagram of a conventional switching signal generating circuit for an inverter.

FIG. 9 is a timing chart of a conventional switching signal generating circuit for an inverter.

FIG. 10 is a circuit diagram of a comparison unit of a conventional example.

FIG. 11 is a timing chart of the comparison unit of the conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 normal counter circuit (sawtooth data forming means) 2 JK flip-flop circuit 3 NOT circuit 4 comparing section (comparing means) 5 comparator (sawtooth data comparing section) 6 comparator (sawtooth data comparing section) 7 NOT circuit ( Sawtooth-wave data comparing section 8 selector circuit (selector section) 9 selector circuit (selector section) 10 latch circuit (opening / closing signal forming section) 11 latch circuit (opening / closing signal forming section) 12 AND circuit 13 AND circuit 14 NOT circuit 15 OR circuit a Modulated wave data d Increasing sawtooth data (normal sawtooth data) e Decreasing sawtooth data (inverting sawtooth data) c1 Comparison signal (normal comparison signal) c2 Comparison signal (inversion comparison signal) q Latch switching signal

Claims (1)

(57) [Scope of request for utility model registration] 1. An inverter switching signal generating circuit used in an inverter for converting DC power into AC power by shutting off DC power by opening and closing a switch member, wherein the switching signal of the switch member is converted into normal sawtooth data and modulated wave data. And a sawtooth data forming means for outputting normal sawtooth data to the comparing means, wherein the comparing means compares the normal sawtooth data and the modulated wave data with each other. A sawtooth-wave data comparing unit that outputs a normal comparison signal by comparing the inverted sawtooth data obtained by inverting the normal sawtooth data with the modulated wave data and outputs an inverted comparison signal; And a selector unit for switching the inverted comparison signal as a latch signal while switching the normal sawtooth data to a predetermined value, and a switching signal based on the latch signal. A switching signal generating circuit for an inverter, comprising: an open / close signal forming section for outputting a signal.