JP2022015280A - Instantaneous interruption reset pulse generating circuit suitable for level shift circuit of instantaneous interruption compensation - Google Patents

Abstract

To provide an instantaneous interruption reset pulse generating circuit suitable for high-side driver circuit without delay even when a power supply voltage VCC has instantaneous interruption.SOLUTION: An instantaneous interruption reset pulse generating circuit, which is a pulse generating circuit connected with a level shift circuit, includes a reset pulse generating circuit for outputting a reset pulse and a set pulse generating circuit for outputting a set pulse, and further includes a first power supply (VCC) and a second power supply (PreREG) for supplying a lower voltage than the first power supply voltage to the pulse generating circuit as a power supply voltage through the first power supply (VCC), a difference detector (VCC-PreREG DET) for detecting that a voltage difference between the first power supply voltage and the second power supply (PreREG) voltage is equal to or lower than a predetermined threshold value to output a voltage drop signal and an instantaneous interruption reset pulse generating circuit which receives the voltage drop signal, generates an instantaneous interruption reset pulse and transmits it to a level shift circuit.SELECTED DRAWING: Figure 1

Description

The present invention relates to a pulse generation circuit that outputs a reset pulse, a set pulse, or the like, and more particularly to a pulse generation circuit suitable for a high-side level shift circuit that drives a high-side switching element of a power device in which a switching element is bridge-connected.

In recent years, in application circuits such as PWM inverters and LLC circuits, the high of the two switching elements connected in series between the high potential (high side) and the low potential (low side), which are configured as a full bridge or a half bridge. As a circuit for driving the side, a level shift circuit using a high withstand voltage integrated circuit is used.

In this type of level shift circuit, in order to reduce power consumption, short on-pulses and off-pulses of about several hundred ns are generated only when the on-command and off-command of the high-side switching element input from the outside are switched. The pulse is transmitted to the high-side switching element drive circuit, and the on / off state is maintained by the latch circuit.
FIG. 6 shows a configuration example of the prior art.

The input circuit IP shown in FIG. 6 inputs and outputs an input signal B that switches between “H” and “L” at a predetermined timing. Here, the input signal B input to the input circuit IP is a negative logic signal, and when the input signal rises from “L” to “H”, the high-side switching element MN10 is made non-conducting, and the input signal becomes non-conducting. It is assumed that the high-side switching element MN10 is conducted when it falls from "H" to "L".
In the semiconductor circuit 1a shown in FIG. 6, a set pulse (E) and a reset pulse (F) are alternately output each time the logic of the input signal B is switched, and the on / off state of the high-side switching element MN10 is controlled.
The low-side switching element MN20 is controlled so as to be in an off / on state complementary to the on / off state of the high-side switching element MN10, and the high-side switching element MN10 and the low-side switching element MN20 are simultaneously in the on state. There is a dead time that is turned off at the same time so that there is no period.

Next, a detailed configuration example of the edge pulse generation circuit EP of FIG. 6 is shown in FIG. 7 (a). As shown in FIG. 7A, the edge pulse generation circuit EP includes a reset pulse generation circuit RP1, a set pulse generation circuit SP1, and an inverter circuit 51. (Refer to Patent Document 1. Here, Patent Document 1 is referred to as the prior art 1.)
In the reset pulse generation circuit RP1 and the set pulse generation circuit SP1, the former inputs the output signal D of the logic sum circuit 13 via the inverter circuit 51, whereas the latter outputs the output signal without passing through the inverter circuit 51. The difference is that D is input, and the other configurations are the same.

The reset pulse generation circuit RP1 is composed of an inverter circuit 52, 53, 54 and a NOR circuit 55. The inverter circuit 53 is composed of a CMOS inverter circuit composed of a epitaxial transistor MP1 and an NaCl transistor MN1 and an RC delay circuit composed of a resistor R1 and a capacitor C1 and connected to the output side of the CMOS inverter circuit.
The RC delay circuit gradually changes the output signal along the transient phenomenon curve determined by the RC time constant, and switches the logic of the output signal of the inverter circuit 54 when the threshold value of the inverter circuit 54 is reached, thereby transmitting the input signal for a predetermined time. It is to delay.
Further, the NOR circuit 55 outputs a negative value U of the logical sum of the output signal T of the inverter circuit 54 and the output signal Q of the inverter circuit 51. A series of sequences described here is shown in FIG. 8 (a).
The set pulse generation circuit SP1 also corresponds to the output signal Q of the inverter circuit 52 of the reset pulse generation circuit RP1 except that the input signal D is input without going through the inverter circuit 51. The same operation is performed to generate a set pulse.

Here, when the power supply voltage VCC of the pulse generation circuit fluctuates, for example, the input signal of the pulse generation circuit is switched from "L" to "H", and at the same time, the power supply voltage VCC becomes 0 due to the influence of external noise or the like. In some cases. FIG. 8B shows a sequence diagram when the power supply voltage VCC fluctuates. In such a case, the reset pulse F that should be output from the reset pulse generation circuit RP1 is not output, and as a result, the output signal G from the output circuit BF does not switch from "H" to "L". Occurs.

If the reset pulse F that should be output is not output in this way, the high-side switching element cannot be switched from on to off. If this state continues, the control state of the low-side driver 2a is switched from off to on, and the high-side switching element MN10 and the low-side switching element MN20 are turned on at the same time, so that a through current flows through both switching elements. There is a problem. That is, if the through current exceeds the current rating of the switching element, there is a problem that both switching elements are damaged.

In view of this problem, a pulse generation circuit that can reliably output a reset pulse even when the power supply voltage VCS of the pulse generation circuit fluctuates and prevent circuit malfunction, and a high-side driver circuit that uses it. As, Patent Document 2 is known.

In Patent Document 2 (Prior Art 2), the capacitor of the RC delay circuit that delays the input signal of the reset pulse circuit of the pulse generation circuit for a predetermined time is changed from GND to the power supply voltage VCS side as shown in FIG. 7 (b). As a result, as shown in FIG. 8D, for example, when the output signal D rises from “L” to “H” at time t1 and at the same time the power supply voltage VCS becomes 0 due to the influence of external noise or the like. Works as follows.
First, the output signal VCR instantly changes to "L" at time t1. This is because the capacitor C1'has no electric charge at this time t1. However, when the power supply voltage VCS returns to the steady value at time t5, the output signal VCR also instantly returns to “H” because the capacitor C1 ′ has no charge. Since the output signal D is “H” at this time t5, the output signal VCR follows the transient phenomenon curve determined by the time constant of the RC delay circuit composed of the resistor R1 and the capacitor C1 ′ after the time t5. And gradually approach "L".
The output signal T of the inverter circuit 54 rises from “L” to “H” at time t10 when the output signal VCR becomes equal to or less than the threshold value.
Therefore, the output signal U of the NOR circuit 55 becomes a pulse signal that rises at time t5 and falls at time t10, and this is output as a reset pulse F.
As described above, according to the embodiment of the prior art 2, the reset pulse F can be generated from the reset pulse generation circuit RP2 even when the power supply voltage VCS fluctuates, and the operation stability of the high-side driver 1a can be generated. To secure.

Japanese Unexamined Patent Publication No. 2002-124858 Japanese Patent No. 4077337

However, although it is possible to generate a reset pulse and extend the pulse width as in Patent Document 2 (conventional technique 2) by the above circuit, the reset signal D is received immediately before the momentary interruption of the power supply voltage VCS. However, the reset pulse cannot be output while the momentary interruption continues. Even if such timing is small, the reset pulse F is output at the time of recovery from the momentary interruption only by the above circuit for the reset operation at the time of the momentary interruption. That is, the output of the reset pulse F depends on the momentary interruption period. As described above, the delay of the reset pulse F causes the high-side switching element and the low-side switching element to conduct at the same time, which causes a problem that a through current flows through both switching elements.

An object of the present invention is to provide a momentary reset pulse generation circuit suitable for a high-side driver circuit that drives a high-side switching element without delay even when the power supply voltage VCC is momentarily interrupted.

In order to solve the above problems, the instantaneous interruption reset pulse generation circuit suitable for the high-side driver circuit for driving the high-side switching element of the present invention resets based on the change of the input signal from the first state to the second state. A first power supply in a pulse generating circuit having a reset pulse generating circuit that outputs a pulse and a set pulse generating circuit that outputs a set pulse based on the change of the input signal from the second state to the first state. And a second power supply that supplies a voltage lower than the first power supply voltage to the pulse generation circuit as a power supply voltage via the first power supply, the first power supply voltage and the second power supply. A difference detector that detects that the voltage difference from the voltage has dropped below a predetermined threshold and outputs a voltage drop signal, and a momentary reset pulse that receives the voltage drop signal and generates a momentary reset pulse to the level shift circuit. A pulse generation circuit characterized by being provided with a momentary reset pulse generation circuit that sends a disconnection reset pulse signal.

Further, in the instantaneous reset pulse generation circuit suitable for the high-side driver circuit for driving the high-side switching element of the present invention, the difference detector is composed of a current mirror circuit, and the first power supply voltage and the second power supply voltage are described. It is characterized by being connected between power supply voltages.

According to the present invention, it is possible to provide a momentary reset pulse to a level shift circuit that drives a high-side switching element without delay even when the power supply voltage VCC is momentarily interrupted. Further, by expanding the voltage range for outputting the momentary interruption reset pulse with respect to the power supply voltage Vcc to a low voltage at the time of momentary interruption, it becomes possible to stabilize the reset.

FIG. 1 is a configuration diagram including a level shift circuit and a high-side driver circuit of the embodiment and their surroundings. FIG. 2 is a circuit diagram showing a difference detector and a momentary reset pulse generation circuit according to an embodiment. FIG. 3 is an application circuit diagram of the difference detector and the momentary reset pulse generation circuit shown in FIG. FIG. 4 is a timing chart when the power supply voltage VCS in the embodiment is momentarily interrupted. FIG. 5 is an example showing the connection between the momentary interruption reset pulse generation circuit and the reset pulse generation circuit of the embodiment. FIG. 6 is a configuration diagram including a conventional level shift circuit, a high-side driver circuit, and their surroundings. FIG. 7 is a diagram showing edge pulse generation circuits of the prior art 1 and the prior art 2. FIG. 8 is a timing chart of the prior art 1 and the prior art 2 of FIG.

Hereinafter, embodiments of the instantaneous reset pulse generation circuit of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is a configuration diagram including a momentary interruption reset pulse generation circuit suitable for the level shift circuit of the momentary interruption compensation according to the embodiment of the present invention, a circuit of a high side driver using the circuit, and its surroundings. In the configuration of the embodiment shown in FIG. 1, what is different from the prior art is that an internal power supply PreREG 13, a difference detector (VCC-PreREG DET) 17, and a momentary reset pulse generation circuit (REST PULSE Gen.) 18 are added. There is.

The difference detector (VCC-PreREG DET) 17 detects the voltage difference between the voltage of the power supply voltage VCS and the voltage of the internal power supply PreReG, and when the voltage between the VCS voltage and the PreReG voltage becomes a predetermined voltage (for example, 2.5V), A voltage drop signal between VCC and PreReG is output to the momentary reset generation circuit 18.
When the instantaneous interruption reset pulse generation circuit 18 receives the voltage drop signal between VCC and PreReG, it generates an instantaneous interruption reset pulse signal and outputs an interrupt reset pulse to the reset pulse signal of the pulse generation circuit 11.

The major difference between the present embodiment and the prior art is that the power supplies of the signal transmission circuit systems 10 to 12, 14 to 16 and 18 including the pulse generation circuit 11 are changed from the power supply voltage VCS to the internal power supply PreReG. Due to this change, even if the power supply voltage VCS fluctuates, the signal transmission circuit system 10 to 12 including the pulse generation circuit 11 does not fall below the operable voltage of the internal power supply PreReG (about 0.3 to 1 V). , 14 to 16 and 18 can be secured for stable operation.
Further, the difference detector (VCC-PreREG DET) 17 detects a voltage drop in the power supply voltage VCS, which leads to the generation of a momentary reset pulse signal. The momentary reset pulse generation circuit 18 outputs a momentary reset pulse until the voltage of the internal power supply PreReG drops to about 0.6 V, although it depends on the configuration of the difference detector (VCC-PreREG DET) 17 described later.

FIG. 2 shows a circuit diagram showing the configurations of the difference detector (VCC-PreREG DET) 17 and the momentary reset pulse generation circuit 18. The difference detector (VCC-PreREG DET) 17 is composed of a current mirror circuit including PNP transistors TR1 and TR2. The emitters of the PNP transistors TR1 and TR2 are connected to the positive electrode of the power supply voltage VCC, the base of the PNP transistors TR1 and TR2 and the collector of the PNP transistor TR1 are connected, and the internal power supply is further connected via the series circuit of the diodes D1 to D3 and the resistor R11. It is connected to the positive electrode of PreREG13.
The collector of the PNP transistor TR2 is connected to the resistor R13 of the momentary reset pulse generation circuit 18 and the base of the NPN transistor TR5 via the resistor R12. That is, the collector of the PNP transistor TR2 outputs as a voltage drop signal between VCC and PreReG via the resistor R12.

Next, the momentary reset pulse generation circuit 18 is composed of a current mirror circuit including PNP transistors TR3 and TR4, an NPN transistor TR5, and the like. The emitters of the PNP transistors TR3 and TR4 are connected to the positive electrode of the internal power supply PreREG13, the base of the PNP transistors TR3 and TR4 and the collector of the PNP transistor TR4 are connected, and further grounded to GND via the resistor R14.
The collector of the PNP transistor TR3 is connected to the collector of the NPN transistor TR5 and is output as a momentary reset pulse signal. A resistor R13 is connected in parallel between the base and emitter of the NPN transistor TR5, and one of the emitter and the resistor R13 is grounded to GND.
The base of the NPN transistor TR5 is connected to the resistor R12 which is the voltage drop signal output between VCC and PreReG of the above-mentioned difference detector (VCC-PreREG DET) 17.

Here, FIG. 4 shows a timing chart when the power supply voltage VCS in the embodiment is momentarily interrupted.
It is assumed that a momentary interruption occurs from time t10 to t19. The power supply voltage VCS starts to decrease from time t10, and when the power supply voltage between VCS and PreREG reaches a predetermined voltage at time t11, the voltage decrease signal between VCC and PreREG from the difference detector (VCC-PreREG DET) 17 is VCC-PreREG. The DET is output, the momentary reset pulse generation circuit 18 outputs the momentary reset pulse signal, and the signal is continuously output until the time t14.
This means that when the voltage between the VCS voltage and the PreREG voltage reaches a predetermined voltage (for example, 2.5V), an interrupt signal is generated in the reset pulse output signal of the pulse generation circuit 11, and the voltage of the internal power supply PreREG drops to about 0.6V. Outputs a momentary reset pulse until That is, since the operable voltage of the instantaneous reset pulse generation circuit 18 is low, there is an advantage that a longer pulse can be output than the logic circuit configured by the C-MOS circuit.

FIG. 3 is an application circuit diagram of the difference detector and the momentary reset pulse generation circuit shown in FIG. The difference from FIG. 2 is that the diodes D1 to D3 are deleted in the circuit of the difference detector (VCC-PreREG DET) 17. By adjusting the quantity of the diodes D1 to D3, the voltage of the power supply voltage between VCS and PreREG can be adjusted, and the detection timing at the time of momentary interruption can be adjusted. It should be noted that the operable voltage of the instantaneous reset pulse generation circuit 18 is not affected.

FIG. 5 is an example showing the connection between the momentary interruption reset pulse generation circuit and the reset pulse generation circuit of the embodiment. The instantaneous interruption reset pulse signal and the reset pulse signal of the instantaneous interruption reset pulse generation circuit are connected to the reset pulse input terminal of the level shift circuit via the NAND circuit NAND2 and the inverter circuit INV2. As a result, the momentary reset pulse signal of the momentary reset pulse generation circuit 18 can be interrupted.
Depending on the configuration of the reset pulse input circuit of the level shift circuit, the output of the instantaneous reset pulse generation circuit 18 may be connected.

As described above, according to the instantaneous interruption reset pulse generation circuit suitable for the instantaneous interruption compensation level shift circuit of the embodiment, the level shift that drives the high-side switching element without delay even when the power supply voltage VCC is instantaneously interrupted. A momentary reset pulse can be provided to the circuit. Further, by expanding the voltage range for outputting the momentary interruption reset pulse with respect to the power supply voltage Vcc to a low voltage at the time of momentary interruption, it becomes possible to reliably perform the reset.

The present invention is applicable to IPMs and the like used in PWM inverters.
Code description

1, 1a Level shift circuit and high-side driver circuit 12 Pulse generation circuit 13 Internal power supply PreReG
17 Difference detector (VCC-PreREG DET)
18 Instantaneous reset pulse generation circuit D1 to D3 Diode MN10 High side switching element MN20 Low side switching element TR1 to TR4 PNP transistor TR5 NPN transistor R11 to 14 Resistor

Claims (6)

It is a pulse generation circuit connected to the level shift circuit.
A reset pulse generation circuit that outputs a reset pulse based on the change of the input signal from the first state to the second state,
In a pulse generation circuit having a set pulse generation circuit that outputs a set pulse based on a change of the input signal from the second state to the first state.
It has a first power supply and a second power supply that supplies a voltage lower than the first power supply voltage to the pulse generation circuit as a power supply voltage via the first power supply.
A difference detector that detects that the voltage difference between the first power supply voltage and the second power supply voltage has dropped below a predetermined threshold value and outputs a voltage drop signal, and a momentary interruption in response to the voltage drop signal. A pulse generation circuit including a momentary interruption reset pulse generation circuit that generates a reset pulse and sends a momentary interruption reset pulse signal to the level shift circuit. The pulse generation circuit according to claim 1, wherein the difference detector is composed of a current mirror circuit and is connected between the first power supply voltage and the second power supply voltage. The difference detector is composed of first and second PNP transistors, each emitter of the first and second PNP transistors is connected to the positive electrode of the first power supply, and the first and second PNPs are connected. Each base of the transistor is connected to the collector of the first PNP transistor, and the collector of the first PNP transistor is connected to the positive electrode of the second power supply via a series circuit of at least one diode and a first resistor. The pulse generation circuit according to claim 2, wherein the pulse generation circuit is connected and outputs a voltage drop signal from the collector of the second PNP transistor. The difference detector is characterized in that the voltage difference between the first power supply voltage and the second power supply voltage is adjusted by selecting the number of diodes connected to the collector of the first PNP transistor. 3. The pulse generation circuit according to claim 3. The difference detector is composed of first and second PNP transistors, each emitter of the first and second PNP transistors is connected to the positive electrode of the first power supply, and the first and second PNPs are connected. Each base of the transistor is connected to the collector of the first PNP transistor, the collector of the first PNP transistor is connected to the positive electrode of the second power supply via the first resistor, and the second PNP transistor is connected. The pulse generation circuit according to claim 2, wherein a voltage drop signal is output from the collector of the above. The momentary reset pulse generation circuit is composed of a third and fourth PNP transistor and a fifth NPN transistor.
Each emitter of the third and fourth PNP transistors is connected to the positive electrode of the second power supply, and each base of the third and fourth PNP transistors and the collector of the fourth PNP transistor are connected.
The collector of the fourth PNP transistor is grounded to GND via the third resistance.
The collector of the third PNP transistor is connected to the collector of the fifth NPN transistor.
2. To claim 2, wherein the emitter of the fifth NPN transistor is grounded to GND, and the base of the fifth NPN transistor is connected to the collector of the second PNP transistor via a second resistor. Item 5. The pulse generation circuit according to Item 5.

Images