JP2001168700A - Switch element driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent through current from flowing through a pair of power switch elements one of which is driven by an RS flip-flop. SOLUTION: The RS flip-flop 30 is set by the rising edge of a pulse signal and reset by the edge of the falling edge of the pulse signal, and a power MOS transistor 31 is on-driven by its output. A falling edge detection circuit 17A consists of delay circuit 17C for delaying the pulse signal and a NOR circuit 15 which inputs the inverse signal of the output signal of the circuit 17C and the pulse signal. Further, a rising edge detection circuit 17B consists of a NAND circuit 14 inputting the pulse signal and the output signal of the circuit 17C, a delay circuit 17D for delaying the output signal of the circuit 14 and a NOR circuit 16 inputting the inversion signal of the output signal of the circuit 17D and the output signal of the circuit 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch element (a high-potential switch element and a low-potential switch element) such as a MOS transistor and a bipolar transistor connected in series. The present invention relates to a switch element driving circuit for turning on / off (for example, a high-potential side switch element) according to the level of an input pulse signal.

[0002]

2. Description of the Related Art A conventional power switch element driving circuit will be described below. This power switch element driving circuit is used to turn on / off the high-potential power N-channel MOS transistor of the pair of power N-channel MOS transistors connected in series according to the level of the input pulse signal. Used.

This power switch element drive circuit has a different reference potential from a low voltage circuit that generates a pulse signal for turning on and off a power N-channel MOS transistor.
It is used to drive a high-potential power N-channel MOS transistor that cannot be directly driven by a pulse signal output from a low-voltage circuit, and detects a rising edge and a falling edge of an input pulse signal, and After the level of the reference potential of the edge detection pulse is shifted, the RS flip-flop is set / reset by each edge detection pulse, whereby a pulse equivalent to the input pulse signal is supplied to the reference of the high-potential power N-channel MOS transistor. N-channel MO for power generated on the high potential side according to the potential
This is for turning on and off the S transistor.

The above-mentioned pair of power N-channel MOS transistors is used, for example, to constitute an inverter circuit to convert DC to AC and supply power to a load. The pair of power N-channel MOS transistors are turned on alternately with a predetermined dead time by a pair of pulse signals.

FIG. 6 is a circuit diagram showing a configuration of a conventional power switch element driving circuit. In FIG. 6, reference numerals 1 and 2 denote pulse signal input terminals for inputting a pair of pulse signals;
-65 are inverters, 36,66,67 are capacitors,
68 and 69 are NOR circuits, 18 and 19 are high-breakdown-voltage N-channel MOS transistors, 20 and 21 are resistors, and 22 to 25.
Is a Zener diode, 26 and 27 are P-channel MOS
Transistors, 28 and 29 are N-channel MOS transistors, 31 and 32 are power N-channel MOS transistors, 33 is a high voltage power supply having a voltage Vb, and 34 is a voltage V
a is a low-voltage power supply having a, 35 is a diode having a forward voltage of VF, and 37 is a load.

Reference numeral 70 denotes a low-voltage circuit connected to the low-voltage power supply 34, which comprises a falling edge detection circuit 70A and a rising edge detection circuit 70B. The falling edge detection circuit 70A includes a delay circuit 70C, an inverter 62, and a NOR circuit 68. The rising edge detection circuit 70B includes a delay circuit 70D, an inverter 65, and a NOR circuit 69. The delay circuit 70C includes inverters 60 and 61 and a capacitor 66.
The delay circuit 70D includes inverters 63 and 64 and a capacitor 67.

[0007] 1A, 2A, 71 to 81 are signals. Three
In the case of 0, the lowest potential is the signal 81, and the highest potential is an RS flip-flop applied from the cathode of the diode 35.

The operation of each part of the power switch element driving circuit configured as described above will be described with reference to the timing chart of FIG.

First, the signal 1A input to the pulse signal input terminal 1 is inverted by the inverter 60, delayed by the capacitor 66, inverted by the inverter 61, and further inverted by the inverter 62, and the original signal 1A is inverted. NO with
The signal 74 is generated by the NOR operation by the R circuit 68. At the same time, based on the signal 1A input to the pulse signal input terminal 1, the signal is inverted by the inverter 63 and
7 and a signal 73 obtained by inverting the signal 1A by the inverter 65 and a signal 73 inverted by the inverter 64.
The signal 75 is generated by the NOR operation by the OR circuit 69.

Next, the signal 74 is a high voltage N channel M
After being converted into a signal 76 by a level shift circuit composed of an OS transistor 18 and a resistor 20, a P-channel MO
S transistor 26 and N channel MOS transistor 2
The signal 78 has the same polarity as the signal 74 by the inverter constituted by 8. Similarly, the signal 75 is converted into a signal 77 by a level shift circuit including the high-breakdown-voltage N-channel MOS transistor 19 and the resistor 21, and then converted to an inverter including the P-channel MOS transistor 27 and the N-channel MOS transistor 29. As a result, a signal 79 having the same polarity as the signal 75 is obtained.

The Zener diodes 22 to 25 output the signal 8
When the high voltage N channel MOS transistor 18 or the high voltage N channel MOS transistor 19 is in a conductive state, the P channel MOS transistor 2
6, 27 and the N-channel MOS transistors 28 and 29 are intended to protect the gate breakdown voltage. In this case, 2
It is necessary to set the low-voltage power supply 34 so that the cathode voltage of the diode 35 is lower than the zener voltage of the stage series.

Next, the signal 78 is input to the reset terminal of the RS flip-flop 30, the signal 79 is input to the set terminal of the RS flip-flop 30, and at substantially the same timing as the signal 1A input to the pulse signal input terminal 1. The amplified signal 80 of the amplitude level is obtained as the Q output of the RS flip-flop 30.

The purpose of a series of constructions in which a rising edge and a falling edge pulses are detected from the signal 1A input to the pulse signal input terminal 1 and the signal 80 is generated again by the RS flip-flop 30 is that resistors 20 and 21 are used. Another object of the present invention is to reduce power consumption in a level shift circuit including high voltage N-channel MOS transistors 18 and 19.

The timing of the signal 80 and the signal 2A input from the pulse signal input terminal 2 is determined by the power N-channel MO.
Input is performed such that there is no period in which both transistors are simultaneously set to the high level state so that a through current does not flow in the S transistors 31 and 32. A so-called dead time is provided.

Power N-channel MOS transistor 32
Is conductive, power N-channel MOS transistor 31
Is in a cutoff state, the forward voltage of the diode 35 is set to V
F, assuming that the voltage of the low-voltage power supply 34 is Va, the capacitor 36 is charged so that the inter-terminal voltage becomes Va-VF.

When the power N-channel MOS transistor 32 is turned off and the power N-channel MOS transistor 31 is turned on, the voltage of the high voltage power supply 33 is changed to Vb.
Then, the potential of the signal 81 becomes Vb while maintaining the voltage Va-VF between the terminals of the capacitor 36, and the diode 3
5 is in a cutoff state.

The signal 81 obtained by the above operation
As a result, the load 37 is driven.

[0018]

However, in the above-described conventional configuration, the signal 1A having a small duty or the signal 1A whose duty is gradually reduced is input to the pulse signal input terminal 1, and the signal 74 or the signal 75 is normally input. When no proper signal is transmitted, that is, when the falling edge detection circuit 70C or the rising edge detection circuit 70D cannot perform normal edge detection,
The following problems arise.

When the signal 1A as described above is input to the pulse signal input terminal 1, the input to the inverter 61 or the inverter 64 can exceed the threshold voltage due to the filtering action of the capacitor 66 or 67. And as a result signal 71 or signal 73
Disappears first or simultaneously (fixed to the high level state or the low level state).

If the signal 71 first disappears, as shown in the timing chart of FIG.
The signal 78 input to the reset terminal of the RS flip-flop 30 first disappears (is fixed to the low level state), and the signal 79 input to the set terminal of the RS flip-flop 30 remains. Therefore, R
The signal 80 output from the S flip-flop 30 is fixed at a high level. As a result, when the signal 2A is at a high level, a through current flows through the power N-channel MOS transistors 31 and 32. In FIG. 8, a broken line indicates a state where the signal 71 has not disappeared.

When the signal 73 disappears first, as shown in the timing chart of FIG. 9, the fall of the signal 79 input to the set terminal of the RS flip-flop 30 is delayed (input to the pulse signal input terminal 1). The signal 79 input to the set terminal of the RS flip-flop 30 and the signal 78 input to the reset terminal are not erased only at the same timing as the falling of the signal 1A. Further, the signal 1 input to the pulse signal input terminal 1
When the duty of A decreases, the signal 71 described above
The signal 80 which is the output of the RS flip-flop 30 is fixed to the high level state by the same operation as when the signal disappears first, and when the signal 2A is at the high level state, a through current flows in the power N-channel MOS transistors 31 and 32. Will flow. In FIG. 9, a broken line indicates a state where the signal 73 has not disappeared.

In FIGS. 8 and 9, the delay amount of the signal 71 with respect to the signal 1A (the polarity is inverted) and the delay amount of the signal 73 with respect to the signal 1A are the pulse width of the signal 1A in the high level state. Although the case where it is smaller is described, the same operation is performed when it is larger.

The present invention solves the above-mentioned conventional problems. When the signal inputted to the reset terminal of the flip-flop disappears, the signal inputted to the set terminal always disappears, and the flip-flop is connected in series. An object of the present invention is to provide a switch element drive circuit that can prevent a through current from flowing through a pair of switch elements.

[0024]

In order to achieve this object, a switching element drive circuit according to the present invention turns on or off one of a pair of switching elements connected in series according to the level of an input pulse signal. A rising edge detection circuit that detects a rising edge of the pulse signal and generates a rising edge detection pulse, and a falling edge detection circuit that detects a falling edge of the pulse signal and generates a falling edge detection pulse. And a flip-flop that turns on one of a pair of switch elements with an output by using a rising detection pulse as a set input, a falling edge detection pulse as a reset input, and an output.

In this case, the falling edge detection circuit
The first delay circuit delays the pulse signal for a predetermined time, and the first logic circuit performs a NOR operation on an inverted signal of the output signal of the first delay circuit and the pulse signal.

The rising edge detection circuit performs a NAND operation on the pulse signal and the output signal of the first delay circuit, and delays the output signal of the second logic circuit by a predetermined time. The second delay circuit includes a third logic circuit that performs a NOR operation on an inverted signal of the output signal of the second delay circuit and the output signal of the second logic circuit.

According to this configuration, the input pulse is delayed by the second delay circuit, and instead of detecting the rising edge by the logical operation of the input pulse and the output signal of the second delay circuit, the first pulse is detected. The signal obtained by the NAND operation of the output signal of the delay circuit and the input pulse is delayed by the second delay circuit, and the signal obtained by the NAND operation of the output signal of the first delay circuit and the input pulse is obtained. The rising edge is detected by the logical operation of the output signal of the second delay circuit and the output signal of the second delay circuit, so that the pulse signal input to the reset terminal of the flip-flop disappears under the condition that the duty of the input pulse signal is small. Sometimes, the pulse signal input to the set terminal of the flip-flop always disappears.

As a result, the output of the RS flip-flop is not fixed to the high level state even if the duty of the input pulse signal is reduced or gradually reduced. A configuration in which a through current does not flow during driving can be realized.

[0029] In the above configuration, the third signal for delaying the output signal of the first logic circuit by a time corresponding to the delay time of the first delay circuit at a stage subsequent to the first logic circuit of the falling edge detection circuit. May be adopted. In this case, the delay from the rising edge of the input pulse signal to the detection of the edge, and
The delay from the falling edge of the input pulse signal to the detection of the edge can be matched, and the pulse width of the input pulse signal can be the same as the pulse width of the signal output from the RS flip-flop. In addition, the switch element can be driven more faithfully with respect to the input pulse signal.

Further, the delay time of the first delay circuit can be made longer than the delay time of the second delay circuit.
By doing so, the edge detection pulse width of the rising edge of the input pulse signal can be made narrower than the edge detection pulse width of the falling edge of the input pulse signal, and the set signal input to the RS flip-flop can be set. The width becomes narrower than the width of the reset signal input to the RS flip-flop, and the width of the input pulse signal at which the output of the RS flip-flop is fixed at a low level can be made wider. Further, the lower limit of the operable pulse width of the input pulse signal can be changed.

[0031]

Embodiments of the present invention will be described below.

FIG. 1 is a circuit diagram showing a configuration of a power switch element driving circuit according to an embodiment of the present invention. In FIG. 1, reference numerals 1 and 2 denote pulse signal input terminals for inputting a pair of pulse signals, reference numerals 3 to 10 denote inverters, reference numerals 11 to 13 and 36 denote capacitors, reference numeral 14 denotes a NAND circuit, and reference numerals 15 and 16 denote NORs.
Circuits, 18 and 19 are high-breakdown-voltage N-channel MOS transistors, 20 and 21 are resistors, 22 to 25 are Zener diodes, 26 and 27 are P-channel MOS transistors, 2
8, 29 are N-channel MOS transistors, 31, 32
Is a power N-channel MOS transistor, and 33 is a voltage V
b, a low voltage power supply having a voltage Va, a diode 35 having a forward voltage of VF, 37
Is the load.

Reference numeral 17 denotes a low-voltage circuit connected to the low-voltage power supply 34, which comprises a falling edge detection circuit 17A and a rising edge detection circuit 17B. The falling edge detection circuit 17A includes delay circuits 17C and 17E, an inverter 42, and a NOR circuit 15. The rising edge detection circuit 17B includes a NAND circuit 14, a delay circuit 17D, an inverter 46, and a NOR circuit 1.
6. The delay circuit 17C is connected to the inverter 3,
4 and a capacitor 11, and the delay circuit 17D includes inverters 6, 7 and a capacitor 12. The delay circuit 17E includes inverters 9 and 10 and a capacitor 13.

1A, 2A and 41 to 53 are signals. Three
In the case of 0, the lowest potential is the signal 53 and the highest potential is an RS flip-flop applied from the cathode of the diode 35.

The operation of each part of the power switch element driving circuit configured as described above will be described with reference to the timing chart of FIG.

First, the signal 1A input to the pulse signal input terminal 1 is inverted by the inverter 3, delayed by the capacitor 11, and then inverted by the inverter 4, and the signal 41 is inverted by the inverter 5. NOR with 1A
The signal 43 is generated by the NOR operation by the circuit 15.

At the same time, the signal 1A input to the pulse signal input terminal 1 is inverted by the inverter 3 and
A signal 45 is generated by a NAND operation of the signal 41A delayed by the above and the original signal 1A by the NAND circuit 14 and the signal 41 inverted by the inverter 4. Then, the signal 45 is transmitted to the inverter 6
The signal 47 is produced by a NOR operation of the signal 45 and the signal 46 obtained by inverting the signal 46, delayed by the capacitor 12, and then inverted by the inverter 7, and the signal 45 by the NOR circuit 16.

In the above configuration, the rising edge of signal 47 is delayed from the rising edge of signal 1A by capacitor 11 by the same time as the delay time of the rising edge of signal 41 with respect to the rising edge of signal 1A. , One purpose is to match the amount of delay,
3 is inverted by an inverter 9, delayed by a capacitor 13, and inverted by an inverter 10 to obtain a signal 44. This signal 4
4 has the same delay amount as the signal 47.

Next, the signal 44 is a high voltage N channel M
After being converted into a signal 48 by a level shift circuit composed of the OS transistor 18 and the resistor 20, the P-channel MO
S transistor 26 and N channel MOS transistor 2
By the inverter constituted by 8, the signal 50 has the same polarity as the signal 44. Similarly, the signal 47 is converted into a signal 49 by a level shift circuit including the high breakdown voltage N-channel MOS transistor 19 and the resistor 21, and then converted into an inverter including the P-channel MOS transistor 27 and the N-channel MOS transistor 29. As a result, a signal 51 having the same polarity as the signal 47 is obtained.

The Zener diodes 22 to 25 output the signal 5
When the high voltage N channel MOS transistor 18 or the high voltage N channel MOS transistor 19 is conducting, the P channel MOS transistor 2
6, 27 and the N-channel MOS transistors 28 and 29 are intended to protect the gate breakdown voltage. In this case, 2
It is necessary to set the low-voltage power supply 34 so that the cathode voltage of the diode 35 is lower than the zener voltage of the stage series.

Next, the signal 50 is input to the reset terminal of the RS flip-flop 30, the signal 51 is input to the set terminal of the RS flip-flop 30, and the pulse signal input terminal 1 of the signal 52 which is the output of the RS flip-flop 30 From the signal 1A, the rising is delayed by the time required for the rising of the signal 1A to be delayed by the capacitor 11, the falling is delayed by the time required for the rising of the signal 43 to be delayed by the capacitor 13, and the amplitude level is amplified. .

It should be noted that the purpose of a series of constructions in which the rising edge and falling edge pulses are detected from the signal 1A input to the pulse signal input terminal 1 and the signal 52 is generated again by the RS flip-flop 30 is that the resistors 20 and 21 are used. Another object of the present invention is to reduce power consumption in a level shift circuit including high voltage N-channel MOS transistors 18 and 19.

The timing of the signal 52 and the signal 2A input from the pulse signal input terminal 2 is based on the power N-channel MO.
Input is performed such that there is no period in which both transistors are simultaneously set to the high level state so that a through current does not flow in the S transistors 31 and 32. A so-called dead time is provided.

Power N-channel MOS transistor 32
Is conductive, power N-channel MOS transistor 31
Is in a cutoff state, the forward voltage of the diode 35 is set to V
F, assuming that the voltage of the low-voltage power supply 34 is Va, the voltage between the terminals of the capacitor 36 is charged so as to be Va-VF.

When the power N-channel MOS transistor 32 is turned off and the power N-channel MOS transistor 31 is turned on, the voltage of the high-voltage power supply 33 is set to Vb.
Then, the potential of the signal 53 becomes Vb while maintaining the voltage Va-VF between the terminals of the capacitor 36, and the diode 3
5 is in a cutoff state.

The load 37 is basically driven by the signal 53 obtained from the above operation, and then the signal 1A having a small duty or a signal having a gradually reduced duty is supplied to the pulse signal input terminal 1. An operation in a non-standard case where 1A is input will be described.

When the signal 1A as described above is input to the pulse signal input terminal 1, either the signal 41 or the signal 46 disappears first or at the same time due to the filtering action of the capacitor 11 or 12 (high level state or high level state). Fixed at low level).

First, when the signal 41 disappears first, as shown in the timing chart of FIG. 3, the signal 50 inputted to the reset terminal of the RS flip-flop 30 is used.
When the signal disappears, the signal 51 input to the set terminal always disappears. When the duty of the signal 1A gradually decreases and is extremely small, the time difference between the signal 50 and the high-level state pulse of the signal 51 becomes extremely small. Occurs at a later time, and after the signal 50 is finally input to the reset terminal of the RS flip-flop 30, the signal 5
0 and the signal 51 both disappear. Therefore, the signal 52 output from the RS flip-flop 30 is fixed at a low level, and the power N-channel MOS transistor 31,
No through current at 32 flows. In FIG. 3, a broken line indicates a state where the signal 41 has not disappeared.

Next, in the case where the signal 46 disappears first, as shown in the timing chart of FIG. 4, the signal 5 inputted to the reset terminal of the RS flip-flop 30 is used.
Both 0 and the signal 51 input to the set terminal remain. When the duty of the signal 1A is larger than that shown in FIG. 4, only the signal 51 input to the set terminal becomes the same as the duty of the signal of the AND operation of the signal 1A and the signal 41 and becomes larger. The signal 50 input to the reset terminal of the RS flip-flop 30 and the signal 51 input to the set terminal remain. When the duty of the signal 1A further decreases, the operation becomes the same as the operation when the signal 41 disappears first. In FIG. 4, a broken line indicates a state where the signal 46 has not disappeared.

In the latter case, the duty of the signal 47 is larger than the duty of the signal 44, and the duty is reduced in the path from the signal 43 to the signal 44, so that the duty is input to the set terminal to the RS flip-flop 30. Since the signal 50 inputted to the reset terminal may disappear earlier than the signal 51 inputted to the reset terminal, the capacitor 11 may be made larger than the capacitor 12, the input threshold voltage of the inverter 4 may be increased, or the input It is also conceivable to make the delay time of the first delay circuit 17C longer than the delay time of the second delay circuit 17D by reducing the threshold voltage.

Here, from the signal 51 in the above, the signal 5
The possibility that “0” disappears first will be described. When the duty of the input signal 1A is small and the pulse width of the input signal 1A is narrow, there may be a situation where the first delay circuit 17C is operating and the second delay circuit 17D is not operating. When the second delay circuit 17D is not operating, the signal 45 passes through the NOR circuit 16, and the above phenomenon occurs.

As a countermeasure, when the delay time of the first delay circuit 17C is made longer than the delay time of the second delay circuit 17D, the edge detection pulse width of the rising edge of the input pulse signal 1A is increased. , The width of the set signal input to the RS flip-flop 30 becomes narrower than the width of the reset signal input to the RS flip-flop 30, The output of the RS flip-flop 30 is fixed at a low level. as a result,
The input pulse signal width at which the output of the RS flip-flop 30 is fixed at the low level can be made wider. Further, the lower limit of the operable pulse width of the input pulse signal can be changed.

In the present embodiment, even if the pulse width of the high level state of the signal 52 is shorter than the pulse width of the high level state of the signal 1A by the delay amount from the rise of the signal 1A to the rise of the signal 42, there is no problem. If not, the inverters 9 and 10 and the capacitor 13 can be omitted.

In this embodiment, the case where the delay amount of the signal 41 with respect to the signal 1A is smaller than the pulse width of the signal 1A in the high level state has been described.
FIG. 5 is a timing chart in the case where the delay amount of the signal 41 with respect to the signal 1A is larger than the pulse width of the signal 1A in the high level state.

In this case, since the signal 45 is fixed at the high level, the signal 51 input to the set terminal of the RS flip-flop 30 is fixed at the low level, and the signal 50 as shown in FIG. RS
The signal 52 output from the flip-flop 30 is fixed at the low level, and no through current flows in the power N-channel MOS transistors 31 and 32.

In the above embodiment, the NAN
The D circuit 14 is used for the following reason.
That is, in a configuration in which the output of the inverter 4 is simply inverted and the NOR circuit 16 and the inverter 6 are added without using the NAND circuit 14, the delay circuit 17C does not operate (the signal does not pass). When the delay circuit 17D operates, it may occur that the input pulse signal passes through and only the set signal to the RS flip-flop 30 is input. However, when the NAND circuit 14 is used, the delay circuit 1
When the signal 7C does not operate, the signal 41 becomes low level, so that the input signal from the delay circuit 17D to the RS flip-flop 30 can be prohibited.

As described above, according to the present embodiment, the signal 43 which is the inverted signal of the signal 41 obtained by delaying the signal 1A using the capacitor 11 and the signal 43 are formed by the NOR operation of the signal 1A. The signal 50 having the same timing as the signal 44 delayed by using the capacitor 13 is input to the reset terminal of the RS flip-flop 30 and the signal 41
A signal 45 is created by NAND operation of the signal 1A and the signal 46, and the signal 46 is obtained by delaying and inverting the signal 45 using the capacitor 12.
The signal 47 is formed by the NOR operation of the signal 45 and the signal 45.
7 is input to the set terminal of the RS flip-flop 30 so that the signal 1A
When the signal 50 serving as the input of the reset terminal of the RS flip-flop 30 disappears when the duty of the signal 1A gradually decreases or when the duty of the signal 1A gradually decreases, the signal 51 serving as the input of the set terminal also disappears. The signal 52, which is the output of the pump 30, is fixed to the low level state, so that no through current flows in the power N-channel MOS transistors 31, 32.

[0058]

According to the present invention, the rising edge and the falling edge of the pulse signal input to the pulse signal input terminal are detected and output by the first and second edge detection circuits, respectively. In the configuration in which a signal based on the signal output from the edge detection circuit 2 is input to the reset terminal and the set terminal of the RS flip-flop, a signal having a small duty or a signal whose duty gradually decreases is input to the pulse signal input terminal. When the signal input to the reset terminal disappears, the signal input to the set terminal always disappears, and when a signal with a small duty or a signal whose duty gradually decreases becomes input to the pulse signal input terminal, When the output of the RS flip-flop is fixed to the low level, the RS flip-flop is fixed. Realizes the superior switching element driving circuit can be connected to the output of the flop is prevented and the through current half-bridge circuit which is assumed to flow.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a power switch element driving circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart when a normal signal is input to a pulse signal input terminal in the power switch element driving circuit according to the embodiment of the present invention.

FIG. 3 is a timing chart when a signal having a small duty is input to a pulse signal input terminal and the signal 41 disappears before the signal 46 in the power switch element driving circuit according to the embodiment of the present invention.

FIG. 4 is a timing chart when a signal having a small duty is input to a pulse signal input terminal and the signal 46 disappears before the signal 41 in the power switch element driving circuit according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating a power switch element driving circuit according to an embodiment of the present invention.
5 is a timing chart when the pulse width is larger than the pulse width in the high level state.

FIG. 6 is a circuit diagram showing a configuration of a conventional RS flip-flop control circuit.

FIG. 7 shows a conventional power switch element driving circuit.
5 is a timing chart when a normal signal is input to a pulse signal input terminal.

FIG. 8 shows a conventional power switch element driving circuit.
5 is a timing chart when a signal having a small duty is input to a pulse signal input terminal and the signal 71 disappears before the signal 73.

FIG. 9 shows a conventional power switch element driving circuit.
5 is a timing chart when a signal having a small duty is input to the pulse signal input terminal and the signal 73 disappears before the signal 71.

[Explanation of symbols]

 1, 2 pulse signal input terminals 3 to 10, 60 to 65 inverters 11 to 13, 36, 66, 67 capacitors 14 NAND circuits 15, 16, 68, 69 NOR circuits 17, 70 low voltage circuits 17A, 17B, 70A, 70B Edge detection circuit 17C, 17D, 17E, 70C, 70D Delay circuit 18, 19 High breakdown voltage N-channel MOS transistor 20, 21 Resistance 22 to 25 Zener diode 26, 27 P-channel MOS transistor 28, 29 N-channel MOS transistor 30 RS flip-flop 31, 32 Power N-channel MOS transistor 33 High voltage power supply 34 Low voltage power supply 35 Diode 37 Load 41 to 53, 71 to 81 Signal

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hiroki Matsunaga 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Yasunaga Yamamoto 1006 Odaka Kadoma Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. F-term (Reference) 5J039 EE01 EE10 EE27 KK05 KK10 KK13 MM06 MM16 5J055 AX27 AX53 BX16 BX18 CX07 DX22 DX56 EX07 EY01 EY10 EY13 EY21 EZ32 EZ50 FX05 FX11 FX17 FX28 FX34 GX01 5J019 DDA DD13 DD05

Claims (3)

[Claims] 1. A switch element driving circuit for turning on or off one of a pair of switch elements connected in series in accordance with the level of an input pulse signal, wherein a rising edge of the pulse signal is detected and a rising edge is detected. A rising edge detection circuit that generates a detection pulse; a falling edge detection circuit that detects a falling edge of the pulse signal to generate a falling edge detection pulse; A flip-flop for turning on one of the pair of switch elements with an output using a detection pulse as a reset input, wherein the falling edge detection circuit delays the pulse signal by a predetermined time; and And an inverted signal of the output signal of the first delay circuit and the pulse signal. A first logic circuit that performs a constant OR operation, wherein the rising edge detection circuit performs a NAND operation of the pulse signal and an output signal of the first delay circuit; A second delay circuit for delaying an output signal of the second logic circuit for a predetermined time; and a NOR operation of an inverted signal of the output signal of the second delay circuit and an output signal of the second logic circuit. A switching element driving circuit comprising a third logic circuit to be performed. 2. A falling edge detection circuit for delaying an output signal of the first logic circuit at a stage subsequent to the first logic circuit by a time corresponding to a delay time of the first delay circuit. 2. The switch element drive circuit according to claim 1, wherein a delay circuit is inserted. 3. The switch element driving circuit according to claim 1, wherein a delay time of the first delay circuit is longer than a delay time of the second delay circuit.