JP2006191747A - Switching circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the efficiency of a switching circuit by delaying a leading edge of a switching control signal for prevention of a through current. <P>SOLUTION: This switching circuit includes first and second transistors TR1a, TR1b connected in series between power sources; first and second control circuits 1a, 1b connected between a control terminal and a source or a drain of the transistor; and first, second, third and fourth voltage clamp elements formed in the control circuit. Therefore, a threshold voltage of the transistor as a switching element is near the central level of the switching signal to make such a timing that two transistors are turned off together. Thus, the through current generated at a switching operation is prevented, thus attaining high switching speed and high efficiency of the switching circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a discharge lamp lighting circuit, and more particularly to a switching circuit for a discharge lamp lighting circuit.

  In recent years, there has been an increasing demand for improving the lighting efficiency of a discharge lamp lighting circuit from the viewpoint of power saving. A switching circuit is used in the discharge lamp lighting circuit. In this switching circuit, a switching circuit in which two transistors are connected in series is used. In the switching circuit, these two transistors are driven by rectangular waves having opposite phases. Therefore, there is a problem that the two transistors are both turned on when the control signal rises and falls, causing a through current to flow.

Patent Document 1 discloses a technique for reducing such a through current. FIG. 3 is a circuit diagram showing a switching circuit disclosed in Patent Document 1. In FIG. In the technique described in Patent Document 1, the rise of the control signal is delayed and the fall of the control signal is advanced, thereby avoiding that both transistors are turned on. FIG. 4 shows the waveform of the gate voltage and the waveform of the output voltage of the output transistor of the technique disclosed in Patent Document 1. In the circuit described in Patent Document 1, the rise of the control signal is delayed in order to avoid the simultaneous ON state of two transistors.
JP-A-10-162982

  However, in the technique described in Patent Document 1, the switching circuit efficiency may be deteriorated because the rise of the switching control signal is delayed in order to prevent a through current.

  The switching circuit of the present invention is a switching circuit having first and second output transistors connected in series between a first power source and a second power source, the control terminal of the first output transistor, and the A first control circuit connected between a source or a drain of the first output transistor and receiving a first control signal via the first and second input terminals; and the second output transistor A second control signal that is connected between the control terminal and the source or drain of the second output transistor and is opposite in phase to the first control signal is input via the third and fourth input terminals. A second control circuit, a first voltage clamp element formed in the first control circuit and connected between the second input terminal and the control terminal of the first output transistor, and 1 control times A second voltage clamp element formed between the second input terminal and the source or drain of the first output transistor, and formed in the second control circuit. A third voltage clamp element connected between the input terminal and the control terminal of the second output transistor; and the fourth input terminal and the second output transistor formed in the second control circuit. And a fourth voltage clamp element connected between the source and the drain. As a result, the threshold voltage of the transistor, which is a switching element, is set near the center level of the switching control signal, and the timing at which both transistors are turned off is created. As a result, it is possible to prevent the through current generated during the switching operation, and to increase the switching speed and increase the efficiency of the switching circuit.

  According to the switching circuit of the present invention, the efficiency of the switching circuit can be increased while preventing a through current.

  Embodiment 1

  A circuit diagram of a switching circuit according to Embodiment 1 of the present invention is shown in FIG. The switching circuit of the first embodiment has first and second output transistors TR1a and TR1b and signal control circuits 1a and 1b.

  The output transistors TR1a and TR1b are connected in series between the power supply potential and the ground potential, TR1a is connected to the power supply potential side, and TR1b is connected to the ground potential side.

  The control circuits 1a and 1b are circuits that generate voltages applied to the gates of the transistors TR1a and TR1b, respectively, from the input control signals. A first control signal Sa is supplied to the control circuit 1a via the first and second input terminals 101a and 102a. The control circuit 1b is supplied with a second control signal Sb having a phase opposite to that of the first control signal via the third and fourth input terminals 101b and 102b. The control signals Sa and Sb are signals given from the preceding circuit through a transformer or the like. The control signals Sa and Sb are rectangular waves whose phases are shifted from each other by 180 °. The control circuits 1a and 1b have the same configuration except that the control signals to be supplied are different. Therefore, in the following description, the configuration and operation will be described focusing on the control circuit 1a.

  The control circuit 1a includes a Zener diode 142a, capacitors 151a and 161a, diodes 141a, 121a and 122a, and resistors 131a, 132a and 133a.

  Resistors 131a, 132a, 133a and a diode 121a are connected to the line 111a via a coupling capacitor 161a. The resistor 131a is connected to the gate of the output transistor TR1a through the line 113a. The diode 121a is connected in the forward direction from the line 113a to the line 111a, and is connected in parallel with the resistor 131a. The resistor 132a is connected between the line 111a and the line 112a. The resistor 133a is connected to the source side of the output transistor via the diode 122a. The diode 122a is connected in the forward direction from the resistor 133a to the source direction of the output transistor. The diode 141a is connected in the forward direction from the line 112a toward the line 113a. The Zener diode 142a is connected in the forward direction from the line 112a to the source terminal direction of the output transistor TR1a. The capacitor 151a is connected in parallel with the Zener diode 142a between the line 112a and the source terminal of the output transistor TR1a.

  As shown in FIG. 1, the input terminal 101a is connected to the line 111a of the control circuit 1a, and the input terminal 102a is connected to the line 112a of the control circuit 1a. The input terminal 101b is connected to the line 111b of the control circuit 1b, and the input terminal 102b is connected to the line 112b of the control circuit 1b.

  A timing chart of the operation of the circuit of Embodiment 1 is shown in FIG. The operation of the control circuit 1a will be described below with reference to FIG. When the control signal applied between the input terminals 101a and 102a rises at timing t0, the voltage of the line 113a changes from low level to high level from timing t0 to t3 based on a predetermined time constant. When the control signal falls at the timing t4, the voltage of the line 113a becomes a low level from the timing t4 based on a predetermined time constant. The rise and fall time constants are determined based on the resistance and capacitance provided in the control circuit, and this point will be described later.

  At this time, the low level of the line 113a is determined by a voltage obtained by adding the forward voltage of the diode 141a and the Zener voltage of the Zener diode 142a, and the High level is obtained by subtracting the Zener voltage of the Zener diode 142a from the maximum level of the input voltage. The level is determined by the voltage. That is, the voltage applied to the gate of the output transistor TR1a is a signal having an amplitude on the positive side and the negative side. The diode 141a and the Zener diode 142a are used as voltage clamp elements. The resistor 132a is a load resistor for the input signal.

  The rising and falling operations of the gate voltage (voltage of the line 113a) of the output transistor TR1a will be described. First, the case where the voltage of the line 111a rises will be described. The time constant of the rise of the gate voltage of TR1a is a time constant determined by the capacitance values of the resistor 132a and the capacitor 151a.

  At this time, the capacitor 151a is charged through the resistor 133a and the diode 122a. Further, since a reverse voltage is applied to the Zener diode 142a, a Zener voltage is generated. Thereby, the line 113a becomes a voltage lower than the source terminal of the transistor TR1a by a Zener voltage. That is, a voltage obtained by subtracting the Zener voltage of the Zener diode 142a from the maximum value of the input voltage is applied between the gate and source of the transistor TR1a.

  Next, the case where the control signal of the line 111a falls will be described. Based on the fall of the line 111a, the gate voltage of the transistor TR1a (the voltage of the line 113a) also starts to fall with a predetermined time constant. When the control signal falls, the potential difference between the line 111a and the line 113a is equal to or greater than the threshold value of the forward voltage of the diode 121a, so that the resistor 131a is bypassed by the diode 121a. Therefore, the gate voltage falls rapidly without a time constant. That is, the diode 121a operates as a falling circuit that controls the falling of the gate voltage, and does not give a time constant to the falling of the gate voltage.

  At this time, the electric charge stored in the gate of the transistor TR1a is discharged through a path formed by the diode 121a, the capacitor 161a, the transformer, and the diode 141a. Further, the electric charge stored in the capacitor 161a is discharged along the same path as the electric charge stored in the gate of TR1a. In addition, the electric charge stored in the capacitor 151a flows into the Zener diode 142a and generates a Zener voltage.

  Therefore, the voltage between the gate and the source of the transistor TR1a when the control signal falls is a voltage obtained by adding the Zener voltage of the Zener diode 142a and the forward voltage of the diode 141a, which is lower than the source voltage. Become.

  In the control circuits 1a and 1b, by using the Zener diode 142a, the voltage applied to the gate electrodes of the output transistors TR1a and TR1b can have amplitudes on both the positive side and the negative side.

  In this embodiment, by providing a resistor and a diode, the time constant at the time of rising of the gate voltage (voltage of the line 113a) when the control signal rises is adjusted, and the gate voltage (line of when the control signal falls) Control is performed to reduce the time constant at the time of falling of the voltage 113a.

  The operation of the output transistors TR1a and TR1b will be described with reference to FIG. 2 showing the waveforms of the gate voltages of the transistors. First, the gate voltage on the TR1a side starts increasing at t0, and the gate voltage on TR1b starts decreasing.

  Due to the relationship between the rise and fall time constants, TR1b first changes from on to off at timing t1. Next, at timing t2, TR1a changes from the off state to the on state. That is, both the TR1a and TR1b are in the off state during the period from the timing t1 to the time t2. At timing t3, the gate voltage of TR1a is −5V + 10V, and the gate voltage of TR1b is −5V.

  At timing t4, the gate voltage of TR1a starts to decrease, and the gate voltage of TR1b starts to increase. Due to the relationship between the rise and fall time constants, TR1a first changes from the on state to the off state at timing t5. Next, at timing t6, TR1b changes from the off state to the on state. That is, both the TR1a and TR1b are in the off state during the period from the timing t5 to the time t6. At timing t7, the gate voltage of TR1a is −5V, and the gate voltage of TR1b is −5V + 10V.

  In the switching circuit of this embodiment, the voltage at the gate electrode of the output transistor has a negative amplitude by the Zener diode and the capacitor, and the time constant of the rise of the gate voltage of the output transistor can be reduced.

  According to the switching circuit of this embodiment, even when the rising speed of the control signal of the switching circuit is increased, it is possible to create a state in which both transistors are turned off. Therefore, a through current that flows when the output transistor is switched can be prevented. As a result, a high-speed switching operation is possible, so that the efficiency of the switching circuit can be improved.

  Further, the embodiment of the present invention is not limited to the above-described embodiment, and can be appropriately changed. For example, a plurality of diodes can be connected in series to determine the amplitude of the control signal.

1 is a circuit diagram of a switching circuit according to a first exemplary embodiment; 3 is a timing chart of a gate voltage waveform and an output waveform of an output transistor of the switching circuit according to the first exemplary embodiment; 2 is a circuit diagram of a switching circuit described in Patent Document 1. FIG. 6 is a timing chart of a gate voltage waveform and an output waveform of an output transistor of a switching circuit according to Patent Document 1.

Explanation of symbols

1a, 1b Control circuit 2a, 2b according to the present invention Control circuit TR1a, TR1b, TR2a, TR2b according to Patent Document 1 Output transistors 101a, 102a, 101b, 102b Input terminals 201a, 202a, 201b, 202b Input terminals 111a, 112a, 113a, 111b, 112b, 113b Wiring (line)
211a, 212a, 213a, 211b, 212b, 213b Wiring (line)
121a, 122a, 121b, 122b, 141a, 141b Diode 221a, 221b Diode 131a, 132a, 133a, 131b, 132b, 133b Resistor 231a, 231b Resistor 142a, 142b Zener diode 151a, 151b, 161a, 161b Capacitor

Claims (8)

A switching circuit having first and second output transistors connected in series between a first power supply and a second power supply,
The first output transistor is connected between the control terminal of the first output transistor and the source or drain of the first output transistor, and the first control signal is input through the first and second input terminals. A control circuit;
The second output transistor is connected between the control terminal of the second output transistor and the source or drain of the second output transistor, and has a phase opposite to that of the first control signal via the third and fourth input terminals. A second control circuit to which two control signals are input;
A first voltage clamp element formed in the first control circuit and connected between the second input terminal and the source or drain of the first output transistor;
A switching circuit having a second voltage clamp element formed in the second control circuit and connected between the fourth input terminal and the source or drain of the second output transistor. A first capacitor connected in parallel with the first voltage clamp element;
The switching circuit according to claim 1, further comprising a second capacitor connected in parallel with the second voltage clamp element.   2. A time constant circuit for controlling gate voltages of the first and second output transistors based on rising or falling edges of the first and second control signals. Switching circuit described The first control circuit further includes a first rising circuit that controls rising of a gate voltage of the first output transistor;
A first falling circuit for controlling the falling of the gate voltage of the first output transistor;
The second control circuit further includes a second rising circuit for controlling the rising of the gate voltage of the second output transistor;
2. The switching circuit according to claim 1, further comprising a second falling circuit for controlling the falling of the gate voltage of the second output transistor. The first rising circuit includes a first resistor connected between the first input terminal and a control terminal of the first output transistor;
A second resistor connected to the first input terminal;
The switching circuit according to claim 4, further comprising a first diode connected in a forward direction from the second resistor toward a source of the first output transistor.   5. The switching according to claim 4, wherein the first falling circuit includes a second diode connected in a forward direction from the control terminal of the first output transistor toward the first input terminal. circuit. The second rising circuit includes a third resistor connected between the third input terminal and a control terminal of the second output transistor;
A fourth resistor connected to the third input terminal;
The switching circuit according to claim 4, further comprising a third diode connected in a forward direction from the fourth resistor toward a source of the second output transistor.   5. The switching according to claim 4, wherein the second falling circuit includes a fourth diode connected in a forward direction from the control terminal of the second output transistor toward the third input terminal. circuit.

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