KR100238231B1 - Semiconductor device - Google Patents

Abstract

Disclosed is a semiconductor device in which a power-up operation normally occurs. The semiconductor device according to the present invention includes an input buffer, a level shift detector, a control clock signal generator, and a chip enable master clock input buffer. The input buffer is controlled by a control clock signal to input the chip enable master clock from an external system, buffer it, and output the buffered master clock. The level shift detector inputs a signal output from the input buffer and outputs a signal having a pulse duration that is active for a predetermined period only when the chip enable master clock is switched from the activation state to the non-activation state. The control clock signal generator inputs a signal output from the level shift detection unit and a power up clock so that the control clock signal generator is in a non-activation state when the power up clock is low level, and is output from the level shift detection unit when the power up clock is high level. A signal that is activated in accordance with the signal to be output is output as the control clock signal. The chip enable master clock input buffer inputs a control clock signal and a chip enable master clock to buffer and drive the chip enable master clock only when the control clock signal is in an active state, and outputs the chip enable master clock as a chip enable signal. According to the present invention, it is possible to prevent unnecessary power consumption in the standby state of the chip circuit.

Description

Semiconductor device and method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and methods, and more particularly to semiconductor devices and methods in which power-up operations normally occur.

The power-up operation of the semiconductor device operates in a standby state as required by the chip enable master clock applied when the semiconductor device is used in an external system. This operation is for switching to the active state as much as possible.

The power-up operation of the semiconductor device is determined by the level of the power supplied from the outside and the level of the chip enable master clock. That is, the power-up operation of the semiconductor device is an operation of recognizing the level of the power applied from the external system and the level of the chip enable master clock and enabling the operations of the chip circuit accordingly.

1 shows a circuit diagram of a power up adjustment device for a conventional power-up operation.

Referring to FIG. 1, a conventional power up adjustment apparatus includes an input buffer 100, a driving delay unit 110, a control clock signal generator 120, and a chip enable master clock input buffer 130.

The input buffer 100 receives the chip enable master clock CEB and the control clock signal PCEBC applied from the outside, and the control clock signal PCEBC is in a low activation state at a low (L) level. Only when present, the chip enable master clock (CEB) information is input and buffered and output.

The driving delay unit 110 delays a signal input from the input buffer 100. Therefore, the signal DICEB output from the driving delay unit 110 is the same signal as the inverted signal of the chip enable master clock CEB is delayed.

The control clock signal generator 120 inputs a signal DICEB, a current control clock signal PCEBC, and a power-up clock VCCH output from the driving delay unit 110 and accordingly, control state of the control clock signal PCEBC. Convert the output to In this case, the power up clock (VCCH) is used for a power-up operation that is enabled at a high ('H') level when the level of power supplied to the chip is equal to or greater than a value Vtarget having a predetermined target value. The associated delay clock.

The control clock signal generator 120 generates the control clock signal PCEBC in a non-activation state whenever the power up clock VCCH is at a low level ('L'), and the power up clock VCCH and the driving delay unit. When the signals DICEB output from the 110 are all high ('H') levels, the state of the control clock signal PCEBC is maintained as it is. In addition, when the power up clock VCCH is at the high ('H') level and the signal DICEB output from the driving delay unit 110 is at the low ('L') level, the control clock signal PCEBC is low ( If it is in the non-activation state at the 'L' level, it is activated to the high ('H') level and is maintained when the control clock signal PCEBC is in the high ('H') state.

The state of the control clock signal PCEBC output from the clock signal generator 120 according to the signal DICEB output from the driving delay unit 110, the current control clock signal PCEBC, and the power-up clock VCCH is shown below. It is shown in the table.

VCCH DICEB PCEBC PCEBC L L L L L L H L L H L L L H H L H L L H H L H H H H H H H H L L

The chip enable master clock input buffer 130 inputs the chip enable master clock CEB and the control clock signal PCEBC to buffer the chip enable master clock CEB according to the control clock signal PCEBC. It outputs as an enable signal PCE.

The chip enable master clock input buffer 130 inputs, buffers, drives, and outputs the chip enable master clock CEB only when the control clock signal PCEBC is activated at a high ('H') level. . Here, the chip enable signal PCE is high due to the chip enable master clock CEB of the low ('L') level when the control clock signal PCEBC is activated at the high ('H') level. 'H') signal is active at the level.

The state of the chip enable signal PCE output from the chip enable master clock input buffer 130 according to the control clock signal PCEBC and the chip enable master clock CEB is shown in the following table.

CEB PCEBC PCE L L L L H H H L L H H L

FIG. 2 is a waveform diagram of various signals for explaining a power-up operation in FIG. 1. FIG. 2 is a waveform diagram of various signals for explaining a case where the chip enable master clock CEB is switched from a low ('L') level to a high ('H') level.

Referring to FIG. 2, when the chip enable master clock CEB is switched from the low ('L') level to the high ('H') level, the control clock signal PCEBC is the chip enable master clock CEB. This high ('H') is then switched from the low ('L') level to the high ('H') level so that the chip enable signal (PCE) is in a low ('L') level of non-activation state. Will remain the same.

FIG. 3 is a waveform diagram of various signals for explaining a power-up operation of FIG. 1. 3 illustrates a power-up operation for enabling the operation of the chip circuit when the chip enable master clock CEB is switched from a high ('H') level to a low ('L') level. This is a waveform diagram of several signals to illustrate.

Referring to FIG. 3, when the chip enable master clock CEB is switched from the high ('H') level to the low ('L) level, the chip enable signal PCE goes to the high (' H ') level. Is converted.

However, as can be seen from the waveform diagrams of the various signals shown in FIG. 3, in the conventional power-up adjusting device for power-up operation, the chip enable master clock CEB is high ('H'). The control clock signal PCEBC is activated high ('H') by the power-up clock (VCCH) when it is non-activated at Therefore, unnecessary operation of the chip circuit may be caused. In addition, the control clock signal PCEBC may be used even when the chip enable master clock CEB has an incorrect unknown level other than the level defined as the high ('H') level or the low ('L') level. Is enabled to the high ('H') level to activate the chip enable signal (PCE).

FIG. 4 illustrates a waveform diagram of various signals when the chip enable master clock CEB has an unknown level.

Referring to FIG. 4, when the chip enable master clock CEB has a value 1.0V of an unknown level, control is performed according to a power-up clock VCCH switched to a high ('H') level. It can be seen that the clock signal PCEBC and the chip enable signal PCE are activated to a high ('H') level.

As described above, the conventional power-up controller for power-up operation prevents the chip circuit from unnecessary operation when the chip enable master clock CEB has an unknown level. I can't. Due to the problem caused by the malfunction of the power-up control device there is a problem that the standby power consumption of the chip circuit is increased.

Accordingly, an object of the present invention is to provide a semiconductor device that normally performs a power-up operation in a semiconductor device.

Another object of the present invention is to provide a method of a semiconductor device in which a power-up operation is normally performed in the method of a semiconductor device.

1 is a block diagram of a power-up device for adjusting a power-up operation in a conventional semiconductor device.

FIG. 2 is a waveform diagram of various signals for explaining the operation of FIG. 1.

3 is a waveform diagram of various signals for explaining another operation of FIG. 1.

FIG. 4 is a waveform diagram illustrating various signals for describing an operation according to the level of the chip enable master clock in FIG. 1.

5 is a block diagram of a device for adjusting a power-up operation in the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a circuit diagram of a circuit in accordance with a specific embodiment of the input buffer of FIG. 5.

FIG. 7 is a circuit diagram of a circuit according to a specific embodiment of the level shift detecting unit in FIG. 5.

FIG. 8 is a circuit diagram of a circuit according to a specific embodiment of the circuit for generating the power up clock in FIG. 5.

9 is a circuit diagram of a circuit according to a specific embodiment of the control clock signal generator in FIG. 5.

FIG. 10 is a circuit diagram of a circuit according to a specific embodiment of the chip enable master clock input buffer in FIG. 5.

FIG. 11 is a waveform diagram of various signals for explaining the operation of power up in FIG. 5.

12 is a waveform diagram of various signals for explaining another operation of power up in FIG. 5.

FIG. 13 is a waveform diagram illustrating various signals for explaining a power-up operation according to the level of the chip enable master clock in FIG. 5.

14 is a flowchart illustrating a method of implementing a power up operation in a method of a semiconductor device according to another embodiment of the present invention.

<Detailed Description of Symbols in Drawings>

VCC: power terminal, GND: ground terminal,

CEB: chip enable master clock, PCEBC: control clock signal,

VCCH: power up clock, PCE: chip enable signal.

In order to achieve the above object, a semiconductor device according to the present invention includes an input buffer which is controlled by a control clock signal and inputs and buffers a chip enable master clock from an external system; A level shift detector for inputting a signal output from the input buffer and outputting a signal having a pulse duration that is active for a predetermined period only when the chip enable master clock is switched from an activation state to a non-activation state; When the power up clock is at a low level by inputting a signal and a power up clock outputted from the level switching detector, the non-activation state is output. When the power up clock is at a high level, the output signal is output from the level switching detector. A control clock signal generator for outputting a signal activated according to the signal as the control clock signal; And a chip enable master clock which inputs the control clock signal and the chip enable master clock to buffer and drive the chip enable master clock only when the control clock signal is in an active state, and outputs the chip enable master clock signal as a chip enable signal. And an input buffer.

In order to achieve the above another object, a method of a semiconductor device according to the present invention,

A chip enable master clock input step of inputting a chip enable master clock from an external system; A chip enable master clock level shift detection step of sensing whether the chip enable master clock input through the chip enable master clock input step is switched from an activation state to a non-activation state; A control clock activation step of activating a control clock signal when it is detected in the chip enable master clock level detection step that the chip enable master clock is switched from an activation state to a non-activation state; And a chip enable signal activation step of activating a chip enable signal after the control clock activation step.

Next, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram of a power up adjusting device for power-up operation in the semiconductor device according to the embodiment of the present invention.

Referring to FIG. 5, in the semiconductor device according to an exemplary embodiment of the present invention, the power-up adjusting device may include an input buffer 200, a level shift detector 210, a control clock signal generator 220, and a chip enable master. And a clock input buffer 230.

The input buffer 200 is controlled by the control clock signal PCEBC to input the chip enable master clock CEB from an external system, buffer it, and output it as a signal ICEB.

The level shift detecting unit 210 inputs a signal ICEB output from the input buffer 200 and is active for a predetermined period only when the chip enable master clock CEB is switched from the activation state to the non-activation state. A signal DICEB having a pulse section is output.

The control clock signal generator 220 inputs the signal ICEB and the power up clock VCCH output from the level shift detecting unit 210 so that the power up clock VCCH is low ('L') level. When the power-up clock VCCH is in the high ('H') level, the signal activated by the signal ICEB output from the level shift detecting unit 210 is used as the control clock signal PCEBC. Output

The chip enable master clock input buffer 230 inputs the control clock signal PCEBC and the chip enable master clock CEB so that the chip enable master clock CEB only when the control clock signal PCEBC is in an active state. Buffering and driving (Driving) and outputs it as a chip enable signal (PCE).

6 illustrates a circuit diagram of a circuit in accordance with a specific embodiment of the input buffer 200 in FIG. 5.

Referring to FIG. 6, a circuit according to a specific embodiment of the input buffer 200 includes PMOS transistors 201 and 202 and NMOS transistors 203 and 204.

The PMOS transistor 201 has a source terminal connected to the power supply terminal VCC, and is gated by the value of the current state level of the control clock signal PCEBC.

The PMOS transistor 202 has a source terminal connected to the drain terminal of the PMOS transistor 201, and is gated by the chip enable master clock CEB. The signal ICEB is output from the drain terminal of the PMOS transistor 202.

The NMOS transistor 203 is connected between the source terminal of the PMOS transistor 202 and the ground terminal GND, and is gated by the chip enable master clock CEB.

The NMOS transistor 204 is connected between the source terminal of the PMOS transistor 202 and the ground terminal GND, and is gated by the value of the current state level of the control clock signal PCEBC.

As can be seen in FIG. 6, the input buffer 200 inputs and buffers the chip enable master clock CEB only when the control clock signal PCEBC is in a non-activation state at a low ('L') level. And output as signal ICEB. The states of the signal ICEB according to the control clock signal PCEBC and the chip enable master clock CEB are shown in the table below.

CEB PCEBC ICEB L L H L H L H L L H H L

FIG. 7 illustrates a circuit diagram of a circuit according to a specific embodiment of the level shift detecting unit 210 in FIG. 5.

Referring to FIG. 7, a circuit according to a specific embodiment of the level shift detecting unit 210 includes a delay unit 211, an inverter 212, and a NOR gate 213.

The delay unit 211 inputs a signal IICE output from the input buffer 200, delays it for a predetermined period of time, and outputs it.

The inverter 212 inputs an output from the delay unit 211 and inverts the output.

The NOR gate 213 inputs a signal IICE output from the input buffer 200 and a signal output from the inverter 212, and logically ORs and inverts it.

FIG. 8 is a circuit diagram of a circuit according to a specific embodiment of a circuit for generating a power up clock (VCCH) applied to one input terminal of the control clock signal generator 220 in FIG. 5. The power-up clock VCCH is a signal that is in a high ('H') level only when the level of the power applied from the outside becomes equal to or greater than a predetermined value Vtarget.

Referring to FIG. 8, a circuit according to a specific embodiment of a circuit for generating a power up clock (VCCH) includes a PMOS transistor 221, a pumping capacitor 222, a resistor 223, diodes 224, 225, and The driving unit 226 is provided.

The PMOS transistor 221 has a source terminal connected to a power supply terminal VCC. The drain terminal and the gate terminal are connected to each other. Since the drain terminal and the gate terminal are connected to each other, the PMOS transistor 221 operates in a saturation region, and the saturation current increases as the level of the voltage applied to the power supply terminal VCC from the outside increases. ) Flows through the drain terminal.

The pumping capacitor 222 is connected between the drain terminal of the PMOS transistor 221 and the ground terminal GND. The pumping capacitor 222 raises the level of the drain terminal of the PMOS transistor 221 when the voltage level of the drain terminal of the PMOS transistor 221 increases according to the voltage level applied to the power supply terminal VCC and reaches a predetermined value. Pumped up to a predetermined high ('H') level value.

The resistance element 223 is connected in parallel with the pumping capacitor 222. The resistor element 223 adjusts the voltage level boosted when the pumping capacitor 222 boosts the level of the drain terminal of the PMOS transistor 221.

The diode 224 is connected in a forward direction between the drain terminal of the PMOS transistor 221 and the power supply terminal VCC. The diode 224 is turned on when the voltage applied to the power supply terminal VCC is sufficiently increased to turn on the diode 224 to assist in charging the pumping capacitor 222 and the PMOS transistor 221. If the level of the drain terminal of the () has a value greater than the level of the power supply voltage (VCC) by the pumping capacitor 222 is turned off.

The diode 225 is connected in a reverse biased direction between the drain terminal of the PMOS transistor 221 and the ground terminal GND.

The driver 226 inputs a signal output from the drain terminal of the PMOS transistor 221, drives it, and outputs the signal as a power-up clock VCCH.

FIG. 9 illustrates a circuit diagram of a circuit according to a specific embodiment of the control clock signal (PCEBC) generator 220 in FIG. 5.

Referring to FIG. 9, a circuit according to a specific embodiment of the control clock signal generator 220 includes NAND gates 227 and 228.

The NAND gate 227 inputs signals output from the power up clock VCCH and the NAND gate 228, logically multiplies them, inverts them, and outputs them as a control clock signal PCEBC.

The NAND gate 228 inputs a signal DIECB output from the level shift detection unit 210 and a control clock signal PCEBC output from the NAND gate 227, logically multiplies them, and inverts them. .

As can be seen in FIG. 9, the control clock signal generator 220 inputs the signal DICEB and the power up clock VCCH output from the level shift detecting unit 210 so that the power up clock VCCH is low. In the case of the 'L' level, the control clock signal PCEBC in the non-activation state is output at the low level. In addition, when the power up clock VCCH is at the high ('H') level, the control clock signal generator 220 is at a high ('H') level when the signal DICEB output from the level change detector 210 is at a high level. When the state of the control clock signal PCEBC is maintained and output as it is, and the signal DICEB output from the level change detection unit 210 is at a low level (L), the control clock signal PCEBC is made high ('). H ') level is activated and output. Thus, the state of the control clock signal PCEBC output according to the power-up clock VCCH and the signal DICEB is shown in the following table.

VCCH DICEB PCEBC PCEBC L L L L L L H L L H L L L H H L H L L H H L H H H H H H H H L L

FIG. 10 illustrates a circuit diagram of a circuit according to a specific embodiment of the chip enable master clock input buffer 230 in FIG. 5.

Referring to FIG. 10, a circuit according to a specific embodiment of the chip enable master clock input buffer 230 may include an inverter 231, PMOS transistors 232 and 233, NMOS transistors 234 and 235, and a driver 236. Equipped.

The inverter 2310 receives a control clock signal PCEBC and inverts the same to output the control clock signal PCEBC.

The PMOS transistor 232 has a source terminal connected to the power supply terminal VCC, and is gated by a signal output from the inverter 231.

The PMOS transistor 233 has a source terminal connected to the drain terminal of the PMOS transistor 232 and is gated by the chip enable master clock CEB.

The NMOS transistor 234 is connected between the drain terminal of the PMOS transistor 233 and the ground terminal GND, and is gated by the chip enable master clock CEB.

The NMOS transistor 235 is connected between the drain terminal of the PMOS transistor 233 and the ground terminal GND, and is gated by a signal output from the inverter 231.

The driver 236 inputs a signal output from the drain terminal of the PMOS transistor 233, drives the signal, and outputs the signal as the chip enable signal PCEBC.

As can be seen from FIG. 10, the chip enable master clock input buffer 230 buffers the chip enable master clock CEB only when the control clock signal PCEBC is at a high ('H') level. The enable signal PCE is activated and output at a high ('H') level. Thus, the states of the chip enable signal PCE output according to the control clock signal PCEBC and the chip enable master clock CEB are shown in the following table.

CEB PCEBC PCE L L L L H H H L L H H L

FIG. 11 is a waveform diagram of various signals for explaining a power-up operation in FIG. 5. FIG. 11 is a waveform diagram of various signals for explaining a case where the chip enable master clock CEB is switched from a low ('L') level to a high ('H') level.

Referring to FIG. 11, when the chip enable master clock CEB is switched from the low ('L') level to the high ('H') level, the signal DICEB output from the level shift detecting unit 210 is output. Since the control clock signal PCEBC is switched from the low ('L') level to the high ('H') level by the pulse period in which the chip is active, the chip enable signal PCE is set to a non-low level of the low ('L') level. It keeps activation.

12 is a waveform diagram of various signals for explaining a power-up operation in FIG. 5. 12 illustrates a power-up operation when the chip enable master clock CEB is switched from a high ('H') level to a low ('L') level, that is, to enable the operation of the chip circuit. This is a waveform diagram of several signals to illustrate.

Referring to FIG. 12, the level shift detecting unit 210 may set the low level 'L' level only when the chip enable master clock CEB is switched from the low level 'L' level to the high level level 'H'. The pulse signal DICEB that is activated is output. Therefore, the control clock signal PCEBC is activated to the high ('H') level only when the signal DICEB output from the level shift detecting unit 210 is active, and thus the chip enable master clock CEB in this state. When switching from the high ('H') level to the low ('L') level, the chip enable signal PCE that is activated at the high ('H') level is output.

As can be seen from the waveform diagram of the various signals shown in Fig. 12, in the semiconductor device of the present invention, the power-up adjusting device for the power-up operation has a low chip enable master clock CEB. Only when the transition from the ('L') level to the high ('H') level is detected, the chip enable master clock (CEB) goes from the high ('H') level to the low ('L') level. When switched, the chip enable signal PCE is activated to enable normal operation of the chip circuit. Therefore, it is possible to prevent unnecessary operation of the chip circuit, which may occur when the chip enable master clock CEB is at an unknown unknown level during the power-up operation. Thus, unnecessary power consumption can be prevented when the chip circuit is in a standby state.

FIG. 13 illustrates a waveform diagram of various signals according to a case in which the chip enable master clock CEB has an unknown level.

Referring to FIG. 13, even when the chip enable master clock CEB has a value (1.0V) of an unknown level, the chip enable master clock CEB is held high from the low ('L') level. It can be seen that the control clock signal PCEBC is activated to the high ('H') level according to the power-up clock (VCCH) only after switching to the 'H') level.

As described above, the power up adjustment apparatus for the power-up operation in the semiconductor device according to the present invention may be implemented in the case where the chip enable master clock CEB has an unknown level. Unnecessary operation can be prevented.

14 is a flowchart illustrating a method of implementing a power-up operation in a method of a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 14, in the method of a semiconductor device according to another exemplary embodiment of the present disclosure, a method of implementing a power-up operation may include a chip enable master clock input step 300 and a chip enable master clock. Level switching detection step 310, control clock signal activation step 320, and chip enable signal activation step 330.

The chip enable master clock input step 300 inputs a chip enable master clock from an external system.

The chip enable master clock level switch detection step 310 detects whether the chip enable master clock input through the chip enable master clock input step 300 is switched from the activation state to the non-activation state.

The control clock activation step 320 activates the control clock signal when it is detected in the chip enable master clock level detection step 310 that the chip enable master clock is switched from the activation state to the non-activation state.

The chip enable signal activation step 330 activates the chip enable signal when the chip enable master clock is activated again after the control clock activation step 320.

The method of the semiconductor device shown in FIG. 14 powers a signal that becomes a high ('H') level only when the level of the power applied from the external system after the chip enable master clock input step 300 becomes equal to or greater than a predetermined value. A power up signal generating step of generating as an up signal and a power up signal detecting step of detecting whether the power up signal is a high ('H') level are further included. Here, the chip enable master clock level switch detection step 310 is performed after the power up signal detection step.

As such, only after sensing that the chip enable master clock is in a non-activation state, the chip enable master clock is activated to activate the chip enable signal and enable operation of the chip circuit. Accordingly, the chip circuit may be prevented from malfunctioning when the chip enable master clock is at an unknown level when the chip circuit is in a standby state. Therefore, unnecessary power consumption in the standby state of the chip circuit can be prevented.

According to the present invention, only after detecting that the chip enable master clock is in a non-activation state, the chip enable master clock is activated to enable the chip enable signal and enable the operation of the chip circuit. Accordingly, the chip circuit may be prevented from malfunctioning when the chip enable master clock is at an unknown level when the chip circuit is in a standby state. Therefore, it is possible to prevent unnecessary power consumption in the standby state of the chip circuit.

Claims (10)

In a semiconductor device, An input buffer which is controlled by a control clock signal and inputs a chip enable master clock from an external system and buffers the output signal; A level shift detector for inputting a signal output from the input buffer and outputting a signal having a pulse duration that is active for a predetermined period only when the chip enable master clock is switched from an activation state to a non-activation state; When the power up clock is at a low level by inputting a signal and a power up clock outputted from the level switching detector, the non-activation state is output. When the power up clock is at a high level, the output signal is output from the level switching detector. A control clock signal generator for outputting a signal activated according to the signal as the control clock signal; And A chip enable master clock input for inputting the control clock signal and the chip enable master clock to buffer and drive the chip enable master clock only when the control clock signal is in an active state and output the same as a chip enable signal. And a buffer. 2. The semiconductor device according to claim 1, wherein the semiconductor device further comprises a power up clock generation circuit for outputting, as a power up clock, a signal that is in a high level only when the level of power applied from the outside becomes equal to or greater than a predetermined value. A semiconductor device characterized by the above-mentioned. The circuit of claim 2, wherein the power up clock generation circuit comprises: Power terminal; A MOS transistor having one terminal connected to the power supply terminal and another terminal and a gate terminal connected to each other; A pumping capacitor connected between said other terminal of said MOS transistor and a ground terminal; A resistance element connected in parallel with the pumping capacitor; A first diode connected in a forward direction between the other terminal of the MOS transistor and the power supply terminal; A second diode connected in a reverse direction between the other terminal of the MOS transistor and the ground terminal; And And a driver which inputs a signal output from the other terminal of the MOS transistor, drives the same, and outputs the signal as the power up clock. The semiconductor device according to claim 3, wherein said MOS transistor is a PMOS transistor. The method of claim 3, wherein the input buffer, A first PMOS transistor connected to the power supply terminal and gated by the control clock signal; A second PMOS transistor connected to the other terminal of the first PMOS transistor and gated by the chip enable master clock; A first NMOS transistor connected between the other terminal of the second PMOS transistor and a ground terminal and gated by the chip enable master clock; And A second NMOS transistor connected between the other terminal of the second PMOS transistor and the ground terminal and gated by the control clock signal, And the other terminal of the second PMOS transistor is connected to an input terminal of the level shift detecting section. The method of claim 1, wherein the level shift detecting unit, A delay unit which inputs a signal output from the input buffer, delays the signal for a predetermined period, and outputs the delayed signal; An inverter that inputs an output from the delay unit and inverts the output; And And a NOR gate for inputting a signal output from the input buffer and a signal output from the inverter, ORing, inverting, and outputting the signal. The method of claim 3, wherein the control clock signal generator, A first NAND gate for inputting a signal output from the level shift detection unit and the control clock signal output from an output terminal, and performing a logical multiplication, an inverting of the control clock signal, and an output; And And a second NAND gate which inputs the power up clock and the signal output from the first NAND gate, AND multiplies them, and inverts them to output them as the control clock signal to the output terminal. The method of claim 3, wherein the chip enable master clock input buffer, An inverter for inputting the control clock signal and inverting the control clock signal to output the control clock signal; A first PMOS transistor connected to the power supply terminal and gated by a signal output from the inverter; A second PMOS transistor connected to the other terminal of the first PMOS transistor and gated by the chip enable master clock; A first NMOS transistor connected between the other terminal of the second PMOS transistor and a ground terminal and gated by the chip enable master clock; A second NMOS transistor connected between the other terminal of the second PMOS transistor and the ground terminal and gated by a signal output from the inverter; And And a driving unit configured to input a signal output from the other terminal of the second PMOS transistor, drive the signal, and output the signal as the chip enable signal. In a semiconductor device, A chip enable master clock input step of inputting a chip enable master clock from an external system; A chip enable master clock level shift detection step of sensing whether the chip enable master clock input through the chip enable master clock input step is switched from an activation state to a non-activation state; A control clock activation step of activating a control clock signal when it is detected in the chip enable master clock level detection step that the chip enable master clock is switched from an activation state to a non-activation state; And And a chip enable signal activation step of activating a chip enable signal after said control clock activation step. 10. The method of claim 9, wherein the method of the semiconductor device generates a signal that becomes a high level only as a power-up signal when the level of the power applied from the external system is greater than or equal to a predetermined value after the chip enable master clock input step. Generating a power up signal; And And a power up signal detecting step of detecting whether the power up signal is at a high level, And detecting the chip enable master clock level shift detection step after the power up signal detection step.

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