JPS59139676A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS59139676A JPS59139676A JP1298483A JP1298483A JPS59139676A JP S59139676 A JPS59139676 A JP S59139676A JP 1298483 A JP1298483 A JP 1298483A JP 1298483 A JP1298483 A JP 1298483A JP S59139676 A JPS59139676 A JP S59139676A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- oxide film
- gate oxide
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 239000010410 layer Substances 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000002356 single layer Substances 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract 1
- 230000007261 regionalization Effects 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229930194542 Keto Natural products 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000004313 glare Effects 0.000 description 1
- 125000000468 ketone group Chemical group 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
（技術分野）
この発明は安定したトランジスタ特性金谷易に得ること
のできる半導体集積回路の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor integrated circuit that can easily obtain stable transistor characteristics.
（従来技術）
従来の半導体集積回路の製造方法をＦＡＭＯ８型集積回
結集積回路法を例にして第１図に示す。まず、第１図（
ａ）に示すように、Ｐ型基板１にＬＯＣＯ８用Ｓ ｉ
、Ｎ、膜２のパターンを形成し、フィールド酸化膜３を
形成する。なお、この第１図（ａ）における１００はメ
モリセル領域２００は周辺トランジスタ領域を示す。(Prior Art) A conventional method for manufacturing a semiconductor integrated circuit is shown in FIG. 1 using the FAMO8 type integrated circuit method as an example. First, Figure 1 (
As shown in a), Si for LOCO8 is placed on the P-type substrate 1.
, N, pattern the film 2, and form the field oxide film 3. Note that 100 in FIG. 1(a) indicates the memory cell area 200 and the peripheral transistor area.
次に、第１図（ｂ）に示すように、５ｉｓＮ４膜２を除
去した後第１層ζ−ト酸化膜４、第１層ポリＳｉ５を全
面形成する。次に、第１層ポリＳｉ５の抵抗を下げるた
めにＰを比較的高濃度に拡散させる。Next, as shown in FIG. 1(b), after removing the 5isN4 film 2, a first layer ζ-oxide film 4 and a first layer poly-Si 5 are formed on the entire surface. Next, P is diffused at a relatively high concentration in order to lower the resistance of the first layer poly-Si5.
次に、第１図（ｃ）に示すように、周辺トランジスタ領
域２００の第１層ポリＳｉ５をホトリソ・エツチングに
よシ除去する。Next, as shown in FIG. 1(c), the first layer poly-Si 5 in the peripheral transistor region 200 is removed by photolithography and etching.
次に、第１図（ｄＪに示すように、９００〜１２００℃
の酸素雰囲気でケ゛−ト眩化暎６を形成し、続いて第２
層ポリＳｉ７を形成する。Next, as shown in Figure 1 (dJ),
A cathode 6 is formed in an oxygen atmosphere, followed by a second one.
A layer polySi7 is formed.
次に、第１図（ｅ）に示すように、ホトリソ・エツチン
グによシ、メモリセル領域１００と周辺トランジスタ領
域２００にケ°−ドパターンを形成する。Next, as shown in FIG. 1(e), a cade pattern is formed in the memory cell region 100 and the peripheral transistor region 200 by photolithography and etching.
しかる後、第１図（ｆ）に示すように、ソース・ドレイ
ン拡散領域８を形成し、中間絶縁膜としてＰＳＧ膜９ヘ
コンタクト領域１０をあけ、さらにＡ／配装ｌｌを形成
する。Thereafter, as shown in FIG. 1(f), a source/drain diffusion region 8 is formed, a contact region 10 is opened to the PSG film 9 as an intermediate insulating film, and an A/wiring 11 is further formed.
しかし、上述の従来の半導体集積回路の製造方法には以
下のような欠点が廟った。すなわち、第１図（ｄ）の工
程においてケ°−ト酸化膜６を形成する際、第１層ポリ
Ｓｉ５の中に含まれる不純物であるＰが外方拡散を起こ
し、周辺トランジスタ領域２００に拡散されるため、周
辺トランジスタのしきい値電圧が不安定となる欠点が有
った。However, the conventional semiconductor integrated circuit manufacturing method described above has the following drawbacks. That is, when forming the keto oxide film 6 in the step shown in FIG. Therefore, there was a drawback that the threshold voltage of the peripheral transistors became unstable.
上記外方拡散を防ぐ手段として、第１層ポリＳｉ５の中
のＰ鑓度を下ける方法が有効であるが、これは新たに以
下のような欠点が生ずる。As a means to prevent the above-mentioned outward diffusion, it is effective to lower the P content in the first poly-Si layer 5, but this new drawback arises as follows.
（１）第１層ポリＳｉ５の抵抗が高くなる。(1) The resistance of the first layer poly-Si5 increases.
（２） 第１層才ｌｉ５と第１層ポリＳｉ５間に介在す
る酸化膜のリーク１流が多くなるので、７０−チイング
ケ゛−ト型ＥＰＲＯＭの電荷保持特性が劣化する。(2) Since the amount of leakage from the oxide film interposed between the first layer Si5 and the first layer polySi5 increases, the charge retention characteristics of the 70-channel gate type EPROM deteriorate.
（発明の目的９
この発明は、上記従来の欠点を除去するためにな式れた
もので、第１層才すＳｉに篩磯度不純物を含んでいても
、外方拡散が起こらない第２ケ゛−ト酸化を形成するこ
とができ、第２層ポリＳｉ構造の１ｖｔ ＯＳ型集積回
路の製造方法に通用できる半導体集積回路の製造方法を
提供することを目的とする。(Objective of the Invention 9) The present invention was developed to eliminate the above-mentioned drawbacks of the conventional technology. It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit that can form a gate oxide and is applicable to a method for manufacturing a 1vt OS type integrated circuit having a second layer poly-Si structure.
（発明の構成）
この発明の半導体集積回路の製造方法は、２層ボＩＪＳ
ｉ構造を有する半導体集積回路の製造方法において、第
２層目のケ゛−ト酸化膜を形成する場合に第Ｉステップ
として６００〜８００℃で３０〜１５０Ａの酸化膜を形
成し、第２ステツプとして８００〜１２００℃で乃１定
のゲート酸化膜厚を得るようにしたものである。(Structure of the Invention) The method for manufacturing a semiconductor integrated circuit of the present invention includes a two-layered IJS
In a method for manufacturing a semiconductor integrated circuit having an i-structure, when forming a second layer of a gate oxide film, an oxide film of 30 to 150 A is formed at 600 to 800°C as an I step, and as a second step. A constant gate oxide film thickness is obtained at 800 to 1200°C.
（実施例）
以下、この発明の半導体集イｌｔＭ路の製造方法の実釉
例について、第１図（ａＪ〜躬１１刊（ｆ）を後月４し
て説明する。この発明の場合、第１１図（ａ）でボした
工程の佐、第１図（１）Ｊで示した半導体を形成する。(Example) Hereinafter, an actual glaze example of the method for manufacturing a semiconductor assembly of the present invention will be explained with reference to FIGS. After the step omitted in FIG. 11(a), the semiconductor shown in FIG. 1(1)J is formed.
次に、ｆ、：Ｊ濃度のＰをボッ７×１０２０Ｇ−３含ん
だ４１層ポリＳｉ５ （４３００Ａ ）をマスクにして
第１層ケ゛−ト改化ｇ４（８ｏｏλ）をパターン形ｊ’
ｍする。Next, using a 41-layer poly-Si5 (4300A) containing 7 x 1020G-3 holes of P with a density of f,:J as a mask, the first layer gate modified g4 (8ooλ) is formed into a pattern j'
m.
次に、第１図（ｄ）に下す第２増ケ゛−ト１紋化ノ換６
の製造に際し第１ステツプとして６００〜８００℃のＰ
の外方拡散が起こらない低温で３０〜１５０Ｘの第２
／＊り°−ト敵化ＢＩＡ６を形成する。Next, the second expansion case 1 pattern conversion 6 shown in FIG.
P at 600-800℃ as the first step in the production of
30-150X at a low temperature where outward diffusion of
/* Form a remote enemy BIA6.
次に、第２ステツプの第２ケ゛−ト咳化工程を通常の高
温酸化（８００〜１２０ＯＡ ）で５００Ｘ形成する。Next, in the second step, the second case is formed by conventional high temperature oxidation (800 to 120 OA) at 500X.
続いて、第１図（ｄ）に示すように、従来方法と同様に
、第２層ポｌＪ’ｓｉ７を３６００ Ａ形成し、第２層
ポリＳｉ７をエツチングマスクにしてケ゛−ドパターン
形成を行う（ケ゛−ト長ば３μ）
次に、第１図（ｆＪに示すようにソース・ドレイン拡散
領域８をＡｓインンラテーション法で仮・ａ閉さ０．５
μ程度に形成し、中間絶縁膜として、ＰＳＧ膜９を５ｏ
ｏｏＡデボし、このＰＳＧ膜９にボンタクト領域１０を
あけ、１μ程度のＡＡ配がＷｌｌのパターンを形成する
。Subsequently, as shown in FIG. 1(d), similarly to the conventional method, a second layer of polyJ'si7 is formed with a thickness of 3600 Å, and a cade pattern is formed using the second layer of polySi7 as an etching mask. (The gate length is 3μ.) Next, as shown in FIG.
The PSG film 9 is formed to have a thickness of approximately
ooA is debossed, a bond area 10 is opened in this PSG film 9, and an AA pattern of about 1 μm forms a Wll pattern.
以上、説明したように、第１の実施例では、裁２層ケ゛
−ト眩化農６の初期を６００〜８００℃の低温で行うた
め、第１虐ボ１Ｊｓｉ５内および表面に尚枳度のＰ不純
物を含んでいても外方拡故現株が起こらない。その効果
として、
（１ン 第１層ポリシリコンの抵抗を低減させること
が可能であるっ
（２］ 第２層ケ゛−ト酸化領域に非コントロールの
不純物が入らないので、トランジスタ特性が安定し、バ
ラツキが小さくなる。As explained above, in the first embodiment, since the initial stage of the cutting two-layer case dazzling process 6 is carried out at a low temperature of 600 to 800°C, the inside and surface of the first processing chamber 1Jsi5 are coated with a high degree of glare. Even if it contains P impurities, outward spread does not occur. As a result, (1) it is possible to reduce the resistance of the first layer polysilicon; (2) the transistor characteristics are stabilized because uncontrolled impurities do not enter the second layer gate oxide region; Variations become smaller.
（３） ボＩＪＳｉ層１ｄ］膜として電気的膜質の良
好なＰ濃度６〜８×１０２０ｄ３が使用できる。(3) IJSi layer 1d] A film having a P concentration of 6 to 8×10 20 d3 with good electrical film quality can be used.
などの利点がある。There are advantages such as
具体的な効果例として、第２図（１００Ｉｆｆウェーハ
でのしきい値電圧ｖＴ分布比較を示すもので、特性ａは
従来の製造方法の場合で、付任すはこの発明の製造方法
の場合である）の実験例を説明する。第１の実施例にお
いて、第１層ボ！Ｊ Ｓｉ ５４３００人中のＰの不純
９勿は７ Ｘ １０２’ ｃｒｔ：３、第２層ケ゛−ト
畝化膜は従来方法の場合１ｏｏｏ℃で５００人、この発
明方法の場合第１スデツプ７００℃で５０Ｘ、第２ステ
ップ１０００℃でトータル５００Ａ形成した。As a specific example of the effect, FIG. 2 (shows a comparison of threshold voltage vT distributions on a 100Iff wafer), where characteristic a is for the conventional manufacturing method, and characteristics a are for the manufacturing method of the present invention. ) will be explained below. In the first embodiment, the first layer Bo! J Si 54,300 P impurity 9 of course 7 x 102' crt: 3, the second layer Kate ribbed film is 500 people at 100°C in the case of the conventional method, the first step is 700°C in the case of the inventive method A total of 500A was formed at 50X and 1000°C in the second step.
この第２図の特性ａに示すように従来方法ではウェーハ
の周辺側でＰの外方拡散によシしきい値電圧■・１・が
低下しているのに比べて、特性すのように、この発明方
法はウェーハ内のｖＴのバラツキが非常に小さくなるこ
とを確認している。As shown in characteristic a in Fig. 2, in the conventional method, the threshold voltage 1. , it has been confirmed that the method of this invention greatly reduces the variation in vT within a wafer.
（発明の効果）
以上のように、この発明の半専体集積回路の製造方法に
よれ（＃：ｆ％第２層目のケ゛−ト収化膜を形成する際
に、第１ステツプとして、６００〜８００℃で３０〜１
５０人の酸化膜を形成した後、第２ステツプとして８０
０〜１２００℃でハ１定の膜厚余得るようにしたので、
第１）ｖＩホリＳｉＫ尚纜度不純物を含んでいても外方
拡散の起こらない第２ケ゛−トハ化を形成することが可
能である。これにともない、第２層ポリＳ目Ｎ造の＋ｖ
ｉ ＯＳ型集抗回路の製造方法に進用することができる
オリ点を南する。(Effects of the Invention) As described above, according to the method for manufacturing a semi-dedicated integrated circuit of the present invention (#:f%), as a first step, 30-1 at 600-800℃
After forming an oxide film of 50 people, the second step is to form an oxide film of 80 people.
Since we made it possible to obtain a certain amount of film thickness between 0 and 1200℃,
1) VII Hole SiK It is possible to form a second crystal layer in which no out-diffusion occurs even if it contains high-grade impurities. Along with this, +v of the second layer poly S mesh N structure
We will find the starting point that can be applied to the manufacturing method of iOS type resistor collector circuit.
第１凶（ａ）ないし第１図（ｆ）はそれぞれ従来および
この発明の半得体集積回路の製造方法の工程説明図、第
２図は従来およびこの発明の半専俸集槓回路の製造方法
で得られた１００ｎウエーハでのしきい値電圧ｖＴ分布
比較を示す図である。
１・・・Ｐ型基板、２・・・５ｉｓＮ＋膜、３・・・フ
ィールド敗化膜、４・・・第１層ケ゛−１ば化膜、５・
・・第１層ポリ５ｉ１６・・・第２層ケ゛−ト酸化膜、
７・・・第２ＪｔｉポリＳ１％８・・・ソース・ドレイ
ン拡散領域、９・・・ＰＳＧＭ、１０・・コンタクト鎖
酸、１１・・・Ａｌ配勝。
特許出願人 沖電気工業昧式会社
レー“」1 (a) to 1 (f) are process explanatory diagrams of the conventional method of manufacturing a semi-integrated integrated circuit and the present invention, respectively, and FIG. 2 is a process explanatory diagram of the conventional method of manufacturing a semi-integrated integrated circuit and the present invention. FIG. 3 is a diagram showing a comparison of threshold voltage vT distributions on 100n wafers obtained in FIG. DESCRIPTION OF SYMBOLS 1... P-type substrate, 2... 5isN+ film, 3... Field decomposition film, 4... First layer case-1 base film, 5...
...First layer poly 5i16...Second layer Kate oxide film,
7... 2nd Jti poly S1% 8... source/drain diffusion region, 9... PSGM, 10... contact chain acid, 11... Al distribution. Patent applicant: Oki Electric Industry Co., Ltd.
Claims (1)
導体集積回路の製造方法において、第２層目のＰ−）１
１化膜を形成する場合、第１ステツプとして６００〜８
００℃で３０〜１５０久の酸化膜を形成し、さらに第２
ステツプとして８００〜１２００℃でＷｒ定のｙ−トｙ
化膜厚を得る工程を含むことを特徴とする半導体集積回
路の製造方法。In a method for manufacturing an MOS type silicon semiconductor integrated circuit having a two-layer polycrystalline silicon structure, the second layer P-)1
When forming a monolayer, the first step is 600 to 8
An oxide film is formed for 30 to 150 years at 00°C, and then a second
Y-toy with Wr constant at 800-1200℃ as a step
1. A method for manufacturing a semiconductor integrated circuit, comprising a step of obtaining a film thickness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1298483A JPS59139676A (en) | 1983-01-31 | 1983-01-31 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1298483A JPS59139676A (en) | 1983-01-31 | 1983-01-31 | Manufacture of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59139676A true JPS59139676A (en) | 1984-08-10 |
Family
ID=11820466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1298483A Pending JPS59139676A (en) | 1983-01-31 | 1983-01-31 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59139676A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62219625A (en) * | 1986-03-20 | 1987-09-26 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
| WO2001020654A1 (en) * | 1999-09-14 | 2001-03-22 | Infineon Technologies North America Corp. | Process for improving the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication |
-
1983
- 1983-01-31 JP JP1298483A patent/JPS59139676A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62219625A (en) * | 1986-03-20 | 1987-09-26 | Seiko Instr & Electronics Ltd | Manufacture of semiconductor device |
| WO2001020654A1 (en) * | 1999-09-14 | 2001-03-22 | Infineon Technologies North America Corp. | Process for improving the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication |
| US6537926B1 (en) | 1999-09-14 | 2003-03-25 | Infineon Technologies, Ag | Process for improving the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication |
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