JPH0277149A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a stacked capacitor in high insulating breakdown strength to be formed by a method wherein polysilicon films are two-layer structured to be composed of a polysilicon layer in low electric resistance as a lower layer and another polysilicon layer doped with no impurity not to be heat- treated as an upper layer. CONSTITUTION:A CVD insulating film 1 is formed on a semiconductor substrate 13 and then a low resistant polysilicon layer 2 is formed on the CVD film 1. After formation of said polysilicon layer 2, a natural oxide film on the surface is removed by fluoric acid solution and then another polysilicon layer 3 700Angstrom thick is formed by pressure reduced CVD process again. This polysilicon layer 3 not doped with any impurity such as P or As etc., becomes a minute compact resistant layer in fine grain diameter. Next, the high resistant polysilicon layer 3 is thermal-oxidized to form a gate insulating film 4. After formation of the gate insulating film 4, polysilicon is formed by pressure reduced CVD process and doped with ordinary impurity to form a blade electrode 5 and a capacitor in high insulating breakdown strength.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device having a MIS type capacitor, particularly a so-called stacked capacitor using a polysilicon oxide film, and a method for manufacturing the same.

Conventional technology In large-scale III integrated circuit devices such as dynamic RAM, the Brehner type MIS capacitor, which has been widely used in the past, has been used to reduce the area occupied by the MIS type capacitor.
From S capacitors, there are trench capacitors in which a trench is formed in a silicon substrate and a capacitor is formed inside the trench, and polysilicon is formed in a silicon substrate with a CVD insulating film sandwiched between them, an insulating film is formed on top of the polysilicon, and an insulating film is formed on top of the polysilicon. A stacked capacitor in which a polysilicon electrode is formed on the substrate, and a trench stacked capacitor in which both of the above are combined are being considered. Among the above capacitors, stacked capacitors can, in principle, be formed in multiple layers by sandwiching CVD insulating films on a silicon substrate, so they are important in the future development of large-scale film integrated circuits. is increasing.

When forming an insulating film on polysilicon to create an It/1 [S type capacitor, a silicon oxide film obtained by thermally oxidizing polysilicon, which is the most stable film, is used as an insulating film. In addition, polysilicon is used as the capacitor electrode, but in order to increase the electrical response speed, it is necessary to lower the electrical resistance of polysilicon. It diffuses into polysilicon and lowers the resistance value.

FIG. 3 shows a cross-sectional structural view of a memory cell of a conventional dynamic RAM, and FIGS. 4(a) to (e) show structural cross-sectional views showing the manufacturing process thereof.

An element isolation insulating film 11. is formed in the semiconductor substrate 13 and on its surface by a well-known method. Source electrode 7, drain electrode 8. A transistor gate insulating film 9, a transistor gate electrode IO, and a CVD insulating film 1 are formed (fourth
Figure (a)). Next, a low resistance polysilicon layer 2 is formed on the CVD insulating film 1 (FIG. 4(b)). Next, an insulating film 4 is formed to cover the entire surface of the low resistance polysilicon layer 2 (FIG. 4(C)). Further, a plate electrode 5 is formed on the surface of the capacitor insulating film 4 (FIG. 4(d)). Finally, the surface of the plate electrode 5 and the surface of the element isolation insulating film 11 are covered with the CVD insulating film 6, a contact hole is formed in a part of the CVD insulating film 6, and the wiring electrode 1 is formed on the surface of the CVD insulating film 6.
2 to the source electrode 7 and plate electrode 5 through contact holes, a dynamic RAM memory cell as shown in FIG. 4(e) or FIG. 3 is completed. That is, in FIG. 3, a stacked capacitor is constructed in which the low resistance polysilicon layer 2 is used as one electrode, the plate electrode 5 is used as the other electrode, and the capacitor insulating film 4 between them is used as an insulating film.

Problems to be Solved by the Invention By the way, when producing a polysilicon oxide film which is the insulating film 4 of a stacked capacitor as shown in FIGS. Since the silicon film is subjected to high-temperature heat treatment in IJ, the grain size becomes large and the surface condition is rough with sharp protrusions.

Therefore, the polysilicon oxide film formed by thermally oxidizing this surface is uneven in thickness and has sharp protrusions. Because of this acute protrusion, when a voltage is applied between the electrodes, electrolytic concentration occurs and the dielectric strength deteriorates. For example, in the case of the MO8 type Kotoya pajita, which is formed by thermally oxidizing a single-crystal silicon substrate, its insulating surface (pressure) can obtain a value of IOMV/cm or more; In capacitors, the dielectric strength deteriorates to 4 to 6 M V/'am and 5
Furthermore, the frequency of initial breakdown voltage failures, that is, short circuits between capacitor electrodes increases. To solve this problem, a silicon nitride film with excellent insulating properties has been used as a capacitor insulating film, or a structure in which a silicon nitride film and a thermal silicon oxide film are stacked in layers has been used. Due to the roughness of the silicon electrode surface, the insulating film must be made thicker in order to obtain the desired dielectric strength voltage.
In order to obtain the required capacitor requirement, the capacitor area must be large (which is not suitable for reducing the capacitor area for large scale integration. Therefore, in order to form a thin insulating film with good control, it is necessary to use a polysilicon base. It is necessary to form the surface of the film into a smooth and flat surface.

The only way to solve the problem: To form a thin insulating film smoothly on polysilicon,
It is best not to subject polysilicon to high-temperature heat treatment. However, by doping polysilicon with n-type impurities,
If heat treatment is not performed at 950° C., the electrical resistance of polysilicon will increase, making it unsuitable for practical use. In order to explain these contradictory conditions, the present invention adopts a polysilicon film with a two-layer structure consisting of a highly doped low resistance layer and an undoped high resistance layer, and the capacitor insulating film is made of the high resistance polysilicon film. By forming it on silicon, it has a structure that is smooth and provides high dielectric strength. In addition, the above 2
In order to obtain a layered polysilicon structure, the base polysilicon layer is formed twice, and the upper layer is a high-resistance polysilicon layer to form a capacitor insulating film.
A method for forming a two-layer polysilicon structure in 5 in-itu by growing n 5-type doped polysilicon without adding a dopant midway, and a method for forming 11-type impurities such as P and As in the underlying polysilicon layer with high energy. The present invention provides a manufacturing method for obtaining a substantial two-layer polysilicon structure in which impurities are not distributed near the surface of polysilicon by implantation.

By forming the polysilicon electrode of the working MIS type capacitor into a two-layer structure consisting of a low resistance layer and a high resistance layer, a flat surface with low electrical resistance and a smooth surface condition can be obtained. Therefore, the capacitor insulating film formed on the polysilicon electrode also has a uniform thickness and is flat, resulting in a high dielectric strength.

By dividing the formation of the lower polysilicon electrode by low pressure CVD into two steps and doping only the lower portion with a high concentration of impurity, the polysilicon electrode having the above-mentioned two-layer structure can be obtained.

When growing doped polysilicon in 5 in situ using the CVD method, an in 5 in 2 layered polysilicon electrode can be obtained by not introducing a dopant during the growth.

By ion-implanting a dopant into the high-resistance lower polysilicon at high energy, a substantially two-layered polysilicon electrode with no impurities in the surface layer can be obtained.

Embodiment An embodiment of the semiconductor device of the present invention is shown in FIG. 1, and FIG. 2 shows the manufacturing method thereof in the order of steps. The following will explain based on FIGS. 1 and 2. In addition, in Figures 1 and 2,
Components that are substantially the same as those in FIGS. 3 and 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

A CVD insulating film 1 is formed on a semiconductor substrate 13 (second
Figure (a)). A low resistance polysilicon layer 2 is formed on the CVD insulating film 1 (FIG. 2(b)). To form this low-resistance polysilicon layer 2, normal polysilicon is heated under reduced pressure at C.
After forming by VD method, with POCl3 or PH3, 8
Diffusion and annealing are performed in a temperature range of 50°C to 950°C. Here, the temperature was 900°C. Through this heat treatment, the concentration of P in the low resistance polysilicon layer 2 is reduced to 5×
At 1020/cIj, at a temperature of 850°C to 950°C, 1020~lQ21 pieces/cJ can be obtained. Thickness 4
When formed at 000A, the sheet resistance value is 20-40Ω/
□ is obtained. Note that the thickness is limited by the desired sheet resistance value, and if it is 2000A or more, 50
It has a sheet resistance value of Ω/4 or less, and has sufficient ability to drive a semiconductor device.

A good low resistance value of about 10Ω/□ can be obtained with a thickness of 6000A, but if the thickness is increased beyond that, the step becomes large and steep, making it difficult to form electrode wiring and contact holes in the subsequent process. In this example, after forming this low-resistance polysilicon layer 2, the natural oxide film on the surface is removed with a hydrofluoric acid solution, and the polysilicon layer 3 is formed again by low-pressure CVD.
Figure 2 (C)). Since this polysilicon layer 3 is not doped with impurities such as P or As, it becomes a dense high-resistance layer with small grain size. Note that the thickness of the high-resistance polysilicon layer 3 is determined by the thickness of the gate insulating film 4 and heat treatment, which will be described later. Usually 500Å~2000
Within the thickness range of A, a capacitor with low electrode resistance, smoothness, and good dielectric strength can be obtained.

A two-layer polysilicon structure is obtained through the above steps. To form this two-layer polysilicon layer, a 1 nsitu type doped polysilicon growth apparatus is used to grow the polysilicon to a desired thickness. By stopping the introduction of dopant gas while continuing to grow polysilicon at the time when polysilicon film 2 has grown, high-resistance polysilicon film 3 can be continuously formed on low-resistance polysilicon film 2. In addition, 5000000Å~7000A anti(
After forming polysilicon (non-doped), ion implantation is performed to achieve a voltage of 130 keV or more for P.

In the case of As, by doping with an acceleration energy of 300 keV or more, the dopant does not remain and the superficial 1000A
A high-resistance polysilicon layer 3 is formed with a thickness of , and a high-concentration polysilicon layer 2 is formed in the lower layer, thereby making it possible to equivalently form a two-layer polysilicon film of low resistance and high resistance. In addition, in addition to P and As, dopants for polysilicon include sb and G.
a and B may also be used.

Next, the high-resistance polysilicon film 3 is thermally oxidized at a temperature of 850°C to 900°C in a mixed gas atmosphere containing 02 or H2 gas to form a gate insulating film 4 with a thickness of 60A to 150A. Figure 2(d)).

The thickness of this gate insulating film 4 is determined by the desired capacitance of the capacitor and the voltage applied between the electrodes. At a commonly used voltage of 5V, if the thickness is 1008 or more, a breakdown voltage of 8V can be obtained in the embodiment of the present invention, so there is no practical problem. If the applied voltage is 2V, there is no problem because the breakdown voltage can be increased by 4VE at 60A. In addition to the normal furnace treatment, the thermal oxidation method includes rapid lamp heating (R
By using TO), an insulating film with less re-diffusion of impurities and excellent dielectric strength can be obtained. In addition to the thermal oxide film, the gate insulating film 4 is made of Si with a thickness of 80 Å to 200 Å.
3N4 is formed on the high-resistance polysilicon layer 3 by the CVD method, and thermal oxidation is performed at a temperature of 850°C to 900°C in a mixed gas atmosphere containing 02 or H2 gas to form Si3N4.
It is also possible to obtain a high-performance gate insulating film 4 by increasing the strength of weak spots 4. The thickness of this Si3N4 film is determined by the capacitance of the capacitor and the applied voltage, similar to the thermal oxide film. Note that if the thermal oxidation of Si3N4 is performed by RTO (Rapid Lamp Thermal Oxidation), redistribution of impurities can be prevented as in the case of a thermal oxide film, so that a gate insulating nN4 with a high dielectric strength voltage can be obtained. Note that similar hardening can be obtained by using a high dielectric material such as tantalum oxide, hafnium oxide, titanium oxide, etc. in addition to Si3N4 as the gate insulating film 4. After forming the above gate insulator [4], polysilicon is processed by low pressure CV
The plate electrode 5 is formed by the D method and doped with ordinary impurities to form a capacitor having a high dielectric strength (FIGS. 2(e), (f) and FIG. 1).

In addition to the polysilicon used in this example, the plate electrode 5 is made of low resistance high melting point metal silicide or
A similar element can also be formed using polycide, which has a two-layer structure of polysilicon and refractory metal silicide.

Effects of the Invention According to the present invention, a stacked capacitor having a high dielectric strength voltage can be obtained, and voltage resistance defects in large-scale integrated circuits can be significantly reduced.
Reliability is also greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional structural diagram of a memory cell of a dynamic RAM which is an embodiment of the present invention, and FIGS. 2(a) to (f) illustrate the manufacturing process of a memory cell of a dynamic RAM which is an embodiment of the present invention. Figure 3 is a cross-sectional diagram of a memory cell of a conventional dynamic RAM;
Figures (a) to (e) are structural cross-sectional views showing the manufacturing process of a conventional dynamic RAM memory cell. ■, 6...CVD insulating film, 2...low resistance polysilicon layer, 3...high resistance polysilicon layer, 4...capacitor insulating film, 5...
Plate electrode, 7, old source electrode, 8...
Drain electrode, 9...Transistor gate insulating film, 10...Transistor gate electrode, 11.
...Element isolation insulating film, 12...Wiring electrode, 13...Semiconductor substrate. Name of agent: Patent attorney Shigetaka Awano 1 person -CV
D

Claims (6)

[Claims] (1) In a MIS type capacitor in which an insulating film is formed on polysilicon, the polysilicon film has a two-layer structure, and the lower layer is doped with an n-type impurity of P or As from 10^2^0 to
10^2^1 piece/cm^3 doped, 10~50Ω/□
It is characterized by having a structure in which the upper layer is a polysilicon layer that is not doped with impurities and is not subjected to heat treatment, and a capacitor insulating film is formed on the upper non-doped polysilicon layer. Semiconductor equipment. (2) A method for manufacturing an MIS type capacitor in which an insulating film is formed on polysilicon, which includes a step of forming a low-resistance polysilicon layer with a thickness of 2000 Å to 6000 Å by low-pressure CVD method, and a step of forming a low-resistance polysilicon layer with POCl_3 on the low-resistance polysilicon layer.
Or 850℃ to 95℃ in a gas atmosphere containing PH_3
A step of diffusing P at a temperature of 0° C. and removing an oxide film formed on the low-resistance polysilicon layer with a solution containing hydrofluoric acid;
forming a high-resistance polysilicon layer with a thickness of 850°C to 90°C;
H2 gas or H_2O gas or O at a temperature of 0℃
_2 Step of forming a silicon oxide film as a capacitor insulating film with a thickness of 60 Å to 150 Å in an atmosphere containing gas, and forming a silicon oxide film with a thickness of 100 Å on the silicon oxide film by low pressure CVD method.
1. A method of manufacturing a semiconductor device, comprising the step of forming polysilicon with a thickness of at least the above thickness. (3) A method for manufacturing an MIS type capacitor in which an insulating film is formed on polysilicon, a step of forming a low resistance polysilicon layer with a thickness of 2000 Å to 5000 Å by low pressure CVD method, and a step of forming a low resistance polysilicon layer with POCl_3 on the low resistance polysilicon layer.
Or 850℃ to 95℃ in a gas atmosphere containing PH_3
A step of diffusing P at a temperature of 0° C. and removing an oxide film formed on the low-resistance polysilicon layer with a solution containing hydrofluoric acid;
A process of forming high resistance polysilicon with a thickness of 2000 Å to 2000 Å, and forming an Si_3N_4 film as a capacitor insulating film on the high resistance polysilicon layer by low pressure CVD method.
A process of forming the Si_3N_4 film to a thickness of Å to 200 Å, and a step of forming the Si_3N_4 film at a temperature of 850 to 900°C with H_2
Manufacturing a semiconductor device, comprising the steps of oxidizing in an atmosphere containing gas, H_2O gas, or O_2 gas, and forming polysilicon with a thickness of 1000 Å or more on the Si_3N_4 film by low pressure CVD method. Method. (4) RTO thermal oxidation performed during formation of capacitor insulating film
4. The method of manufacturing a semiconductor device according to claim 3, wherein the method is a high-speed lamp heating oxidation method. (5) A method for manufacturing an MIS type capacitor in which an insulating film is formed on polysilicon, including a step of forming a low-resistance polysilicon layer with a thickness of 2000 Å to 6000 Å by low-pressure CVD, and adding P to the low-resistance polysilicon. 130ke
With energy higher than V or 300 keV of As
A process of implanting ions with the above energy to form a high-resistance polysilicon layer, and forming Si_3N as a capacitor insulating film on the high-resistance polysilicon layer by low pressure CVD.
A process of forming the Si_3N_4 film with a thickness of 80 Å to 200 Å, and heating the Si_3N_4 film at a temperature of 850°C to 900°C.
A method for manufacturing a semiconductor device, comprising the steps of oxidizing in an atmosphere containing 2 gas, H_2O gas, or O_2 gas, and forming polysilicon with a thickness of 1000 Å or more on the Si_3N_4 film by low pressure CVD. (6) In the method of manufacturing an MIS type capacitor in which an insulating film is formed on polysilicon, SiH_4 gas and PH_3
An n-type polysilicon layer is formed with a thickness of 2000 Å to 6000 Å by a low-pressure CVD method using a mixed gas containing gas, and then Si without PH_3 is formed in the same CVD apparatus.
High resistance polysilicon layer of 500 Å in H_4 gas atmosphere
a step of forming an insulating film with a thickness of 60 Å to 150 Å on the high-resistance polysilicon layer, and a step of forming an insulating film with a thickness of 60 Å to 150 Å on the high-resistance polysilicon layer, and a step of forming an insulating film with a thickness of 60 Å to 150 Å on the high-resistance polysilicon layer by low pressure CVD.
1. A method for manufacturing a semiconductor device, comprising the step of forming polysilicon with a thickness greater than or equal to the thickness.