JPH0461158A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a memory capacitor having large capacitance by adjusting the quantity of As ions implanted to a first silicon film and keeping the resistivity value of As ions within a specific range. CONSTITUTION:A LOCOS film 6 is formed in the element isolation region on the surface of a P-type single crystal silicon substrate 1, and an N-type MOS transistor 30 is formed in an element region. A silicon film 9a is formed onto the silicon substrate 1. After ions are doped to the silicon film 9a to bring the resistivity thereof proximate to 2X10<-2>OMEGA.cm, the film 9a is patterned to a capacitor electrode 9b. A natural oxide film is removed from the surface of the capacitor electrode 9b, and a thin silicon nitride film 10a is shaped. The surface of the nitride film 10a is oxidized and a silicon oxide film 10b is formed, thus forming an insulating film 10. A silicon film is formed onto the oxide film 10b, and patterned in the shape of a capacitor electrode 11, thus forming a memory capacitor 20. A bit wiring 13 is shaped onto an inter- layer insulating film 15 deposited on the memory capacitor 20 and an inter-layer insulating film 7. Accordingly, the memory capacitor having large capacitance can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a fine memory capacitor.

(Prior Art) In order to increase the storage (memory) capacity of a semiconductor memory device formed on one semiconductor chip, each element constituting the memory element of the semiconductor memory device is miniaturized, and each of these elements is integrated into a chip. They need to be concentrated at high density on top.

A memory capacitor, which is a main element of a semiconductor memory device, includes a pair of capacitor electrodes and a capacitor insulating film sandwiched between the electrodes.

The amount of charge that one memory capacitor can store is proportional to the area of the capacitor electrode, so if the area of the capacitor electrode is reduced too much for the purpose of miniaturizing the memory element, the amount of stored charge will decrease, and the Malfunction may occur.

Therefore, in order to increase the memory capacity of a semiconductor storage device, it is necessary to integrate a large number of memory capacitors on the same chip that have a sufficiently large effective electrode area1 and occupy a small area on the board. is required. In order to meet this demand, development of memory capacitors having three-dimensional structures such as trench structures and stack structures is actively underway.

On the other hand, the amount of charge that the Meowaki 1 vacitor can accumulate also depends on the dielectric constant and film thickness of the capacitor insulating film.

In order to increase the amount of charge that a capacitor insulating film can store per unit area, a film made of a material with a high relative dielectric constant is used as the capacitor insulating film, and the thickness of the film is increased as much as possible. Just reduce it.

For this reason, progress is being made in the development of capacitor insulating films that are resistant to dielectric breakdown even if they are thin and have a relatively high dielectric constant.

An insulating film consisting of a two-layer film of a silicon nitride film and a silicon oxide film formed by oxidizing the surface of the silicon nitride film has a relative dielectric constant of relatively 1. :It combines the advantages of silicon nitride film, which is high in cost, and the advantage of silicon oxide film, which is excellent in reliability, making it suitable for use as a capacitor insulating film.

In order to fabricate such a memory capacitor having a silicon nitride film and a silicon oxide film, first, a first polycrystalline silicon film that functions as the first electrode (lower electrode) of a pair of capacitor electrodes is formed. After that, a silicon nitride film is formed on the first polycrystalline silicon film. Thereafter, a silicon oxide film is formed on the silicon nitride film by oxidizing the surface of the silicon nitride film.

Next, a second polycrystalline silicon film, which will become the second electrode (upper electrode) of the pair of capacitor electrodes, is formed on the substrate so as to cover the silicon oxide film.

(Problem to be Solved by the Invention) When a silicon nitride film is formed, the surface of the first polycrystalline silicon film is oxidized, so that the interface between the silicon nitride film and the first silicon film is oxidized. However, there is a problem in that a natural oxide film having a thickness of 11 to 2 nm or more is formed.

As a result, the total thickness of the insulating film increases by the thickness of the natural oxide film, and the capacitance of the capacitor decreases.
This will result in

In this way, according to the conventional method, a thin silicon nitride film and a thin silicon oxide film are formed for the purpose of reducing the total film thickness of the capacitor insulating film, but this purpose is not fully achieved and large capacity memory It becomes difficult to obtain capacitors.

It is known that the growth rate of the native oxide film, which causes the above-mentioned problem, decreases as the impurity concentration near the surface of the first polycrystalline silicon film decreases. However, if the impurity concentration is reduced, the thickness of the depletion layer formed on the surface of the first polycrystalline silicon film (first electrode) becomes wider during the operation of the memory element. Another problem arises in that the capacitance of the capacitor decreases.

The present invention has been made to solve the above problems, and its purpose is to form a memory capacitor with a large capacity without increasing the total thickness of a thin capacitor insulating film during the manufacturing process. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can perform the following steps.

(Means for Solving the Problems) The present invention includes a step of forming a first silicon film on a semiconductor substrate to become a first electrode of a pair of capacitor electrodes;
implanting impurity ions into the first silicon film;
A semiconductor device comprising: forming a capacitor insulating film on the first silicon film; and forming a second silicon film, which becomes a second electrode of the capacitor electrodes, on the insulating film. The manufacturing method includes using As ions as the impurity ions and adjusting the implantation amount of the As ions,
The specific resistance value of the first silicon film is 1×10-2Ω・Cm
to 1×10”Ω·cm, thereby achieving the above object.

Further, after the step of implanting the impurity ions,
The first silicon film may be subjected to heat treatment before the step of forming the insulating film.

(Example) The present invention will be described below with reference to Examples.

1 to 6 are partial cross-sectional views of a semiconductor device for explaining the main steps of this embodiment.

First, a normal process for manufacturing a semiconductor device was carried out to obtain a semiconductor device at an intermediate stage as shown in FIG. At this stage, a LOCO3 film 6 is formed in the element isolation region on the surface of the P-type single crystal silicon substrate 1, and an N-type MOS transistor 30 is formed in the element region.

The N-type MOS transistor 30 includes a channel region 16 provided in the element region, an LDD@ region 4 formed on both sides of the channel region 16, and an LDD@ region 4 formed on both sides of the channel region 16 via the DD region 4 between them. N-type source region 3a
and an N-type drain region 3b, a gate insulating film 14 formed on the channel region 16, and a gate electrode 2 formed on the gate insulating film 14. Note that a sidewall insulating film 5 is provided on the sidewall of the gate electrode 2.
A first interlayer insulating film 7 is formed on the silicon substrate 1 so as to cover the silicon substrate 1, and a first contact is formed in a predetermined portion of the first interlayer insulating film 7 located on the drain region 3b. Hall 8 is provided.

On such a silicon substrate 1, a first silicon film (thickness: 500 nm) 9a was formed to become a first electrode (lower electrode) 9b of a pair of capacitor electrodes for a memory element.
Figure 2).

In this embodiment, the first silicon film 9a is formed by normal CVD.
The film was deposited on a silicon substrate 1 in a non-doped state by a method. Further, the crystallinity of the first silicon film 9a of this example was polycrystalline immediately after deposition. But 1. The crystallinity of the first silicon film 9a immediately after deposition may be polycrystalline or amorphous.

The first silicon film 9a immediately after deposition does not contain a sufficient amount of impurities (dopants), and as it is, even if heat treatment is performed to activate the impurities, only a high resistivity value can be obtained. I can't.

In order for the first silicon film 9a to function as a capacitor electrode, it is necessary to dope the first silicon film 9a with a sufficient amount of impurity to sufficiently reduce the specific resistance value of the first silicon film 9a. be.

For this reason, in this example, a step was performed in which As ions were used as impurity ions to dope the first silicon film by ion implantation on the 9th day (FIG. 3). The implantation acceleration energy of As ions was 100 keV, and the dose was 5 x
10 "cm-". As a result, the specific resistance value of the first silicon film 9a exhibited a value of about 2XiO-2Ω·Crn after the final process for manufacturing the memory element.

After the ion implantation process, the first silicon film 98 is formed into the first capacitor electrode 9 using a normal photolithography technique.
I want to butter it into the shape of b (Fig. 4).

Next, by immersing the silicon substrate l in a sulfuric acid solution,
After removing organic matter etc. from the surface of the first capacitor electrode 9b, etc., the first capacitor electrode 9b is
The natural oxide film was removed from the surface, and moisture was removed in a dry nitrogen atmosphere.

Alternatively, the natural oxide film may be removed from the surface of the first capacitor electrode 9b by an HF vapor phase cleaning method, and then water may be removed in a dry nitrogen atmosphere.

According to this method, the native oxide film can be removed more effectively.

After removing the native oxide film, a silicon nitride film (thickness: 6 nm) 10a, which is the thinner of the two layers constituting the Ushibashita insulating film 10, was formed on the first capacitor electrode 9b. The silicon nitride film 10a is formed by LPCVD on the silicon substrate 1.
This was carried out by inserting the substrate into a furnace, raising the substrate temperature to 770° C. in a mixed gas atmosphere of 5iH2CI2 and NH3, and maintaining that state for 4 minutes.

In this example, the first silicon l! Since the specific resistance of X9a is set to about 2xlO-2Ωcm, the problem of a thick natural oxide film growing on the surface of the first silicon film 9 during the process of forming the silicon nitride film 10a is avoided. I was able to do that. Note that the silicon film 10a at this time
The As concentration inside is IX 1021! It is on the order of cm-3.

Next, by oxidizing the surface of this thin silicon nitride film], a thin silicon oxide film (thickness 2nrn) 1Ob is formed on the silicon nitride film 10a, and a thin silicon oxide film 1Ob is formed from the silicon nitride film 10a and the silicon oxide film 10b. A capacitor insulating film 10 was fabricated.

Note that the film thickness of the silicon nitride film 10a was reduced to 5nrn because its surface was oxidized. As the oxidation method, HCl10z oxidation was performed.

After that, a second silicon film (
A process of forming a film with a thickness of 350 nrn was performed.

Next, the second silicon film was patterned into the shape of the second capacitor [pole 11] using a normal photolithography technique (FIG. 5).

The second electrode 11 and the first electrode 9b thus formed
and the capacitor insulating film 10 sandwiched between these electrodes 91) and 11, a stacked memory capacitor 2 is formed.
0 is configured.

Thereafter, a second interlayer insulating film 15 is deposited on the memory capacitor 20 and the first interlayer insulating film 7 by a normal method, and a contact hole 12 (see FIG. After forming an opening (indicated by a broken line inside), a bit wiring 13 was formed on the second interlayer insulating film 15 (FIG. 6).

first electrode 9b of memory capacitor 20 and N-type MO3)
It is in contact with the N-type drain region 3b of the transistor through a contact hole 8. Further, the bit wiring 13 and the N-type source region 3a of the N-type MOS transistor are as follows.
They are in contact through a contact hole 12.

The increase in the total film thickness of the capacitor insulating film 10 of the memory capacitor 20 thus formed was suppressed to about 1 nm (thickness equivalent to a silicon oxide film) or less from the design value. Also, during operation of the memory element, the first electrode 9b
The width of the depletion layer formed on the surface did not become wider.

In this embodiment, impurity (As) is added to the first silicon film 9a.
After doping, a capacitor insulating film 10 was formed before performing heat treatment for the purpose of activating impurities. However, before forming the capacitor insulating film 10, a heat treatment protective film covering the first silicon film 9a may be deposited on the silicon substrate 1, and then heat treatment may be performed at about 800 to 9.00°C. .

As a heat treatment method, a lamp annealing method may be used in addition to the usual electric furnace annealing method.

Immediately after ion implantation, the concentration distribution of implanted As has a peak near the surface of first silicon film 9a. If the above heat treatment is performed, the implanted As diffuses into the first silicon film 9a, so that the AS concentration near the surface of the first silicon film 9a decreases. Furthermore, damage caused by ion implantation in the first silicon film is recovered by the heat treatment.

By performing the heat treatment in this manner, the surface of the first silicon film 9a becomes less likely to be oxidized, and a decrease in the capacitance of the memory capacitor 20 can be more effectively suppressed. As a step after removing the heat treatment protective film from the silicon substrate 1, the same steps as those in the above-mentioned embodiments may be performed.

In this way, in the embodiment described above, the first silicon film 9a
Since the specific resistance of the silicon nitride film 10a is approximately 2×10′-2Ω·cm, the problem of a thick natural oxide film growing on the surface of the first silicon film 9a during the step of forming the silicon nitride film 10a is avoided. We were able to. The capacitance of the fabricated memory capacitor 20 decreases by 10% from the design value.
The decrease was suppressed to less than %.

FIG. 2 shows the relationship between the total thickness increase of the capacitor insulating film 10 due to natural oxidation of the first silicon film 9a and the specific resistance of the first silicon film 9a.

This relationship applies to the first polycrystalline silicon film (thickness: 500 nm) 9 of the plurality of memory capacitors 20.
A was obtained by implanting As ions at a dose within the range of 5×10 I4 to 5×1O” cm −2 .

The injection acceleration energy is 1 for any capacitor.
It was set to 00 keV.

Immediately after ion implantation and before the oxidation process, some capacitors were not heat-treated, other capacitors were heated to 850°C for 60 minutes, and other capacitors were heated to 900°C for 30 minutes. Heat treatment was performed after forming the protective film for heat treatment. The steps other than Step 2 are the same as those in the above-mentioned embodiment.

In Figure 7, the circle mark indicates the thickness of the capacitor's insulating film that was not heat-treated, the mark indicates the capacitor insulating film thickness that was heat-treated at 850°C for 60 minutes, and the Δ mark indicates the thickness of the capacitor insulating film that was heat-treated at 850°C for 60 minutes. This is the thickness of the capacitor insulating film after 30 minutes of heat treatment.

Note that when the total film thickness of a capacitor insulating film consisting of a silicon nitride film and a silicon oxide film, which have different iJ ratios, is expressed in relation to the capacitance, the value is simply the sum of the film thicknesses of those films. There is no real meaning in using it. Therefore,
The vertical axis in Figure 7 is calculated as the total film thickness when all silicon nitride films are silicon oxide films, taking into account the difference in dielectric constant between silicon nitride films and silicon oxide films. There is.

In addition, the mark indicates the amount of capacity decrease in the capacitor that was not heat treated, the box symbol indicates the amount of capacity decrease in the capacitor that was heat treated at 850℃ for 60 minutes, and the square symbol indicates the capacity decrease in the capacitor that was heat treated at 900℃ for 30 minutes. It's the amount. This amount of capacitance decrease is determined by applying a bias of 1.65 volts between both electrodes of the capacitor.
It was obtained from the capacitance measured in 7.

As shown in FIG. 7, the first silicon M 9 a (
D resistivity is 1×10-”Ω-cm to IXIQ-1Ω・
cm (for As concentration, 3X1019~2
X I 028 cm-3), the increase in the film thickness of the capacitor insulating film 10 is suppressed to about 1 nrn or less. In particular, the increase in the film thickness of the capacitor insulating film 10 was further suppressed in the case where the heat treatment was performed before depositing the silicon nitride film. Moreover, when the specific resistance is within the above range, the amount of decrease in capacity jljl is suppressed to about 10% or less.

However, if the specific resistance is in the range of 1×10 −2 Ω·Crrl or less, the increase in the film thickness of the capacitor insulating film 10 is 1.
It has become more than nrr+ level. Also, the specific resistance is 1
If it is in the range of ×10-'Ω·cm or more, the increase in the film thickness of the capacitor insulating film 10 is suppressed, but during the operation of the memory element, the first electrode (first silicon film) 9b Since the layer width of the depletion layer formed on the surface becomes wider, the capacitance of the memory capacitor 20 decreases by 10% or more.

In this way, A, s implanted into the first silicon film 9a
By adjusting the amount of ion implantation, the value of the resistivity of the first silicon film 9a is changed from 1×10 −2 Ω・ern to 1×10 −1 Ω・
By setting it within the range up to Cff1, a memory capacitor 20 with a large capacity could be manufactured without increasing the thickness of the capacitor insulating film 10 during the manufacturing process.

Note that in the above embodiment, a method for manufacturing a memory element having a structure of a silicon nitride film 1Oa and a silicon oxide film 10b as the structure of the capacitor insulating film 10 has been described, but a memory element having a capacitor insulating film of other structure may be used. Regarding the device, by using a method similar to the method of this embodiment, growth of a native oxide film on the first silicon film can be suppressed, and a memory device having a thin capacitor insulating film can be manufactured.

Further, the present invention is not limited to a method of manufacturing a semiconductor memory device. If the present invention is applied to a method of manufacturing other semiconductor devices having capacitors, favorable effects can be obtained for higher integration and miniaturization of the devices.

(Effects of the Invention) According to the present invention, the amount of As ions implanted into the first silicon film is adjusted, and the value of the specific resistance of the first silicon film is changed from 1xio-2Ωcm to 1x10 -'Ω・cm
By keeping it within the above range, a memory capacitor with a large capacitance having a thin capacitor insulating film can be manufactured without increasing the thickness of the capacitor insulating film during the manufacturing process.

Furthermore, if the first silicon film is heat treated after the step of implanting impurity ions and before the step of forming the capacitor insulating film, a memory capacitor with a larger capacity can be obtained.

4. Don't worry! 1 to 6 are cross-sectional views for explaining each process of an embodiment of the present invention, and FIG. 7 shows the relationship between the resistivity of the first silicon film and the ratio of capacitance of the memory capacitor. This is a graph showing.

Engineering...Silicon substrate, 2...Gate 1i pole, 3a.
...N-type source region, 3b...N-type drain region, 4
...LDD region, 5...Side wall insulating film, 6
... LOCOS film, 7... first glabellar insulating film, 8.
...First hole, 9a...First silicon film, 9b10. First electrode (lower electrode), 10...
Capacitor insulating film, 10a... silicon nitride film, Ro
b... Silicon oxide film, 11... Second electrode (upper electrode), 12... Second contact hole, 13...
・Bit wiring, 14... Gate insulating film, 15... Second interlayer insulating film, 16... Channel region, 20-...
Memory capacitor, 30...N type MOS transistor.

that's all

Claims (1)

[Claims] 1. A first electrode serving as a first electrode of a pair of capacitor electrodes.
a step of forming a silicon film on a semiconductor substrate;
a step of implanting impurity ions into the silicon film of the first silicon film;
forming a capacitor insulating film on the silicon film;
A method for manufacturing a semiconductor device, comprising: forming a second silicon film serving as a second electrode of the capacitor electrode on the insulating film, the impurity ions being As ions; A method for manufacturing a semiconductor device in which the specific resistance value of the first silicon film is within the range of 1×10^-^2 Ω·cm to 1×10^-^1 Ω·cm by adjusting the implantation amount of . 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first silicon film is subjected to heat treatment after the step of implanting the impurity ions and before the step of forming the insulating film.