JPS59139659A - Method for formation of lead for electronic circuit device - Google Patents
Method for formation of lead for electronic circuit deviceInfo
- Publication number
- JPS59139659A JPS59139659A JP58226841A JP22684183A JPS59139659A JP S59139659 A JPS59139659 A JP S59139659A JP 58226841 A JP58226841 A JP 58226841A JP 22684183 A JP22684183 A JP 22684183A JP S59139659 A JPS59139659 A JP S59139659A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- package
- envelope
- lsi
- pellet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はたとえは高密度、高速ロジック用セラミンクパ
ッケージ型ＬＳＩ（大規模集積回路）に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ceramic package type LSI (Large Scale Integrated Circuit) for high-density, high-speed logic.
従来、高密度、高速ロジック用セラミックパッケージ型
ＬＳＩ（以下単にＬＳＩパッケージと称する８ ）はＭ
Ｉ８セラミックパッケージ構造からなり、プリント基板
（プリント板）等の配線基板にリードを介して取り付け
られる、このＬＳＩバフケージはプリント板側のセラミ
ック板（セラミンク基板）からなる外囲器（ベース）内
に＃：導体素子（ベレット）を固定するとともに、プリ
ント板から離れる他のセラミック板からなる外囲器（キ
ャップ）の外面に放熱用の金属からなるヒートシンク（
フィン）が設けられている。Conventionally, ceramic package type LSIs (hereinafter simply referred to as LSI packages) for high-density, high-speed logic are M
This LSI buff cage has an I8 ceramic package structure and is attached to a wiring board such as a printed circuit board (printed board) via leads. : In addition to fixing the conductor element (bellet), a heat sink (made of metal for heat dissipation) is installed on the outer surface of the envelope (cap) made of another ceramic plate that is separated from the printed board.
fins) are provided.
しかし、従来の積層セラミ２クパツケージ構造では次の
ような欠点がある。However, the conventional laminated ceramic two-pack cage structure has the following drawbacks.
（１）積層セラミックパッケージ構造は多数枚のセラミ
１．り板な積み重ねたり、各セラミック板にスルーホー
ルを設けてこの孔に導市材を充満させ、セラミ’７り板
上下面の配線を電気的に接続させるなど抱雑となること
から製造コストが高い。(1) The laminated ceramic package structure consists of a large number of ceramics. Manufacturing costs are high due to the complicated process of stacking the ceramic plates, making through holes in each ceramic plate, filling these holes with conductive material, and electrically connecting the wiring on the top and bottom surfaces of the ceramic plates. expensive.
（２１ｙＬ咎セラミ・ンクバンケージ構造はセラミック
基板に形成するメタライズ層の加工寸法の公差を±１％
以内の値にすることがむずかしい。したがってセラミン
ク板上にメタライズされて形成されたリードの内端とベ
レットの電極とをワイヤで接続するボンディング作業に
あって、公差が太きいため自動化が困難となり、ボンデ
ィング加工時間が大きくなる。また、信頼性も悪くなる
８（３） 配線が導電性ペーストのメタライズによる
ため、抵抗が高くなりやすく、低抵抗にするためにメタ
ライズ幅を大きくとることからパッケージ全体が大きく
なり易い。(The 21yL ceramic bank cage structure has a tolerance of ±1% in the processing dimensions of the metallized layer formed on the ceramic substrate.
It is difficult to set the value within this range. Therefore, in a bonding operation in which the inner end of a lead formed by metallization on a ceramic plate is connected to an electrode of a pellet using a wire, automation is difficult due to the large tolerance, and the bonding processing time is increased. Reliability also deteriorates 8(3) Since the wiring is made of metallized conductive paste, the resistance tends to increase, and since the width of the metallization is widened in order to achieve low resistance, the entire package tends to become large.
（４） メタライズ配線間隔はスルーホールの孔径と
の関係から、スルーホール径（たとえは一般的な技術的
最小値は０．３ ｍｍφ）よりも小さくできない。(4) Due to the relationship with the diameter of the through hole, the metallized wiring spacing cannot be made smaller than the through hole diameter (for example, the general technical minimum value is 0.3 mmφ).
このためＬＳＩパッケージの小型化が図ねない。For this reason, it is not possible to downsize the LSI package.
すなわち、従来ではゲート数が１００．ＩＪ−ド数が５
０程度のものが最も大規模なものであるが、素子数９０
００個、ゲート数４００．リード数１００程度のＬＳＩ
が要求される現在にあっては、従来の稍層パッケージ構
造で作ると極めて大きなものとなってしまい好ま１．＜
ない。In other words, conventionally the number of gates is 100. IJ-number is 5
The largest one is about 0, but the number of elements is 90.
00 pieces, number of gates 400. LSI with about 100 leads
In today's world where packaging is required, it is preferable to use the conventional multi-layer package structure because it would be extremely large. <
do not have.
（５）放熱板はペレットを取り付けたベースに直接固定
さｔず、キャップに固定さハている。（、たがって、熱
の大部分はベース、ベースとキャップとの接合枠部、キ
ャップ、放熱板の順序で伝わるため、放熱性が低い８ま
た、セラミック自体は金属等に較べて熱伝導度が低いと
いう欠点もある。(5) The heat sink is not directly fixed to the base to which the pellet is attached, but is fixed to the cap. (Thus, most of the heat is transmitted in this order: the base, the joint frame between the base and the cap, the cap, and the heat sink, resulting in low heat dissipation.8 Also, ceramic itself has a lower thermal conductivity than metals, etc.) It also has the disadvantage of being low.
本発明はこのような欠点を解消するもσ）であって、そ
の目的は低床なＬＳＩパンケージを提供すまた、本発明
の他の目的は、自動ワイヤボンディングの可能な構造の
ＬＳＩパンケージを提供することにある。The present invention solves these drawbacks (σ), and its object is to provide a low-floor LSI pancake.Another object of the present invention is to provide an LSI pancake with a structure that allows automatic wire bonding. It's about doing.
また、本発明の他の目的は、ＬＳＩパ、ケージの小型化
を図ることにある。Another object of the present invention is to reduce the size of an LSI package.
また、本発明のさらに他の目的は気密性等の信頼度の高
いＬＳＩパンケージを提供することにある。Still another object of the present invention is to provide an LSI package with high reliability such as airtightness.
また、本発明の他の目的は配線の低抵抗化を図ることに
ある。Another object of the present invention is to reduce the resistance of wiring.
さらに、本発明の他の目的は熱抵抗を可及的に低く１″
ることによって放熱性の良好なＬＳＩパッケージを提供
することにある。Furthermore, another object of the present invention is to reduce the thermal resistance to 1" as much as possible.
The object of the present invention is to provide an LSI package with good heat dissipation.
このような目的を達ｅ′ｆ′るために本発明の一実施例
は、支持用または電極用リードσ）一部によりパッケー
ジを外枠に支持（、た状態で残りのリードの整形を行な
うものである。In order to achieve this purpose, one embodiment of the present invention is to support the package to the outer frame by a part of the support or electrode lead σ, and then shape the remaining leads. It is something.
第１図は本発明適用ＥまたＬＳＩパ、ケージのを示す。FIG. 1 shows an LSI package to which the present invention is applied.
同図において１は例えば矩形のセラミ、り板からなる第
１外囲器である。この第１外凹器１けプリント板などか
らなる配線板（図示せず）Ｋ対面（図では上面がフリン
ト板に対面１−る。）する。そして、その反対面（必中
下面）の中央部は窪み２を有１−ている。３は前記第１
外囲器１と同じ大きさのセラミック板からなる第２外囲
器であって、その中央部は円形又は角形に抜けている８
そ（、て、この円形部又は角形は２段の段付孔となって
いて、下面の広径部には熱伝導度の良好なモリブデン、
タングステンなどがちなる金槁板（支持板）４がカラス
５を介し、て固定さ才′Ｉている。また、金属とガラス
は接合強度が弱いことから、補強板６を用い、この補強
板６と第２外囲器３とで前記支持板４を挾み込むように
している。ｆなわち、補強板６は外周は第２外囲器３と
同じ形状をし、内周は第２外囲器３の内径部と同じ大き
さになっていて、ガラス７で第２外囲器３および支持板
４に接着１ている。In the figure, reference numeral 1 denotes a first envelope made of, for example, a rectangular ceramic plate. A wiring board (not shown) consisting of a single printed board or the like faces K (in the figure, the upper surface faces the flint board). The center part of the opposite surface (lower surface) has a depression 2. 3 is the first
A second envelope made of a ceramic plate of the same size as the envelope 1, the central part of which is cut out in a circular or square shape 8
Well, this circular or square part has a two-step stepped hole, and the wide diameter part on the bottom is made of molybdenum, which has good thermal conductivity.
A metal plate (support plate) 4 made of tungsten or the like is fixed via a crow 5. Further, since the bonding strength between metal and glass is weak, a reinforcing plate 6 is used, and the supporting plate 4 is sandwiched between the reinforcing plate 6 and the second envelope 3. f That is, the reinforcing plate 6 has an outer periphery having the same shape as the second envelope 3, an inner periphery having the same size as the inner diameter of the second envelope 3, and a glass 7 that forms the second outer envelope. The container 3 and the support plate 4 are glued together.
また、８は前記第１外囲器ｌと第２外囲器３と力量πガ
ラス９を介［て挾持固着さＪする複数のリードである。Further, reference numeral 8 denotes a plurality of leads that are clamped and fixed to the first envelope 1, the second envelope 3, and the force π glass 9.
このリード８はコバール、鉄−ニノケル４２合金等の薄
板をエツチングやプレスによって形成されたものであり
、第１外囲器１と第２外囲器３とからなるパンケージ部
１０の内にあっては、第２外囲器３の上面に沿って延ひ
るとともに、パンケージ部１０の外にあっては２箇所で
屈曲し、その先端部は第１外囲器Ｊの上面とほぼ同一の
平面上あるいに前記上面よりわずかに突出〔た面に沿う
ように延びている。そして、これらのリード８の外端部
はプリント配線基板（図示せず）の端子部に重なり合う
ようになっている、また、１１は素子数か／ことえは９
０００個を有するシリコン板からなるＬＳＩ素子（ペレ
ット）であって、前記支持板４のパッケージ部１０の内
面に例えば金−シリコン共晶合金ハ☆ｊ２を介［て固定
されている。１３は金線あるいはアルミニウム線等から
なるワイヤであって、超音波ボンディング方法や熱圧着
方法でペレットの電極とリード８の内端を繋いでいる。This lead 8 is formed by etching or pressing a thin plate of Kovar, iron-Ninokel 42 alloy, etc., and is located inside a pan cage section 10 consisting of a first envelope 1 and a second envelope 3. extends along the upper surface of the second envelope 3 and is bent at two places outside the pan cage part 10, and its tip is on the same plane as the upper surface of the first envelope J. Alternatively, it extends along a surface slightly protruding from the upper surface. The outer ends of these leads 8 overlap the terminals of a printed wiring board (not shown), and 11 is the number of elements.
The device is an LSI device (pellet) made of a silicon plate having over 1,000 pieces, and is fixed to the inner surface of the package portion 10 of the support plate 4 via, for example, a gold-silicon eutectic alloy. A wire 13 is made of a gold wire, an aluminum wire, or the like, and connects the electrode of the pellet to the inner end of the lead 8 using an ultrasonic bonding method or a thermocompression bonding method.
ｊ４は銅、アルミニウム等の熱伝導度の艮好な金属等か
らなる柱状のヒートシンクであり、圧接又は鑞付けによ
って前記支持板４の外面（図中下面）に固定さねている
。なお、このヒートシンクπは第５図に示すように、放
熱フィンを取り付け、放熱性をさらに高めて本よい。j4 is a columnar heat sink made of a metal with excellent thermal conductivity such as copper or aluminum, and is fixed to the outer surface (lower surface in the figure) of the support plate 4 by pressure welding or brazing. As shown in FIG. 5, this heat sink π may be equipped with heat dissipation fins to further improve heat dissipation.
つぎに、このようなＬＳＩパ、ケージの製造工程につい
て第２図を用いて簡単に説明する。（ａｔ、第３図で示
すようなリードフレーム１５を用意する。このリードフ
レーム１５はシリコンの熱膨張係数と近似するコバール
や４２合金等からなる薄い板、たとえば０．１ ｍｍの
厚さの板をエツチング技術や精密プレス技術を用いて形
成する。この場合、各リード８間の距離は板厚とほぼ同
じ程度まで狭く形成できる。また寸法公差は±０．２〜
０３％にすることができる。各リード８は矩形枠からな
るリム１６の各辺から枠中央に向かって延びている。Next, the manufacturing process of such an LSI package will be briefly explained using FIG. 2. (at, a lead frame 15 as shown in FIG. 3 is prepared. This lead frame 15 is a thin plate made of Kovar, 42 alloy, etc. whose coefficient of thermal expansion is similar to that of silicon, for example, a plate with a thickness of 0.1 mm. is formed using etching technology or precision press technology. In this case, the distance between each lead 8 can be formed as narrow as almost the same as the plate thickness. Also, the dimensional tolerance is ±0.2 ~
It can be set to 0.3%. Each lead 8 extends from each side of a rim 16 made of a rectangular frame toward the center of the frame.
また、矩形枠の四隅は幅広に形５Ｖさねており、該部Ｉ
Ｑｊ円形あるいは長孔からなるハンドリングおよび位値
決め用のカイト孔１７が設Ｈ１−）ねでいる。In addition, the four corners of the rectangular frame are wide and 5V shaped, and the part I
A kite hole 17 for handling and positioning consisting of a Qj circular or elongated hole is provided H1-).
また、矩形枠の四隅にはダミーリードＪ８が設けられて
いる。このダミーリード１８１／（は凹部１９が設けら
４、外力を加えると簡単に四部１９で破断するようＫな
っている。この凹部１９は紀１゜第２外囲器１，３の外
周縁部上に位置する部分に設けられている。Furthermore, dummy leads J8 are provided at the four corners of the rectangular frame. This dummy lead 181/( is provided with a recess 19 4, and is designed so that it will easily break at the four parts 19 when an external force is applied. It is located in the upper part.
（ｂ）、このようなリードフレーム１５の各リード８の
先端ｔ）ワイヤ取付部に蒸着法あるいはめっき法によっ
てアルミニウム被膜あるいは金披膜を形成する。（ｃｌ
、ヒートシンク１４を固定した支持板４を補強板６およ
び高信頼度σ）低融点フリットガラスを用いて第２外囲
器３に固定１−る、（ｃｌｌ、ペレット］１を支持板の
ペレットを掴り付ける部分に部分的に形成し７たＡｕ層
を介（て支持板４に固定−′ｔ７−０（ｅｌ、ペレット
の菫、極とリードとび）間をワイヤボンディングにより
電気的に接続する。（ｆｌ、第１外囲器１を第２外囲器
３に低融点カラスフリットを介して重ね合せ、第４図に
示すように、加熱溶融により一体的に気密封止する。(b) An aluminum film or a gold film is formed on the tip of each lead 8 of such a lead frame 15 (t) at the wire attachment portion by vapor deposition or plating. (cl.
, fix the support plate 4 on which the heat sink 14 is fixed to the second envelope 3 using the reinforcing plate 6 and high-reliability σ) low melting point frit glass, (cll, pellet) 1 and fix the pellet of the support plate. It is fixed to the support plate 4 through the Au layer formed partially on the part to be gripped - 't7-0 (el, violet of pellet, pole and lead jump) is electrically connected by wire bonding. (fl) The first envelope 1 is stacked on the second envelope 3 via a low-melting glass frit, and as shown in FIG. 4, they are hermetically sealed integrally by heating and melting.
（ｇ）、パ、ケージ部１０から突出するり一ド８の表面
ＫＸＰ田をめっきする。（ｈｌ、リード８のみをリム１
６の付は根部分で切＠する。この状態では、各リードは
電気的に独立］、ていることから、（１）、リードフレ
ームのまま取り扱って各パッケージの特性測定を行ない
、選別分類する。（ｊ）、前記測定の結果、良品けり一
ドを折り曲は成形する。（ｋｌ、リム部をダミーリード
１８の凹部１９から破断させて、第１図で示すＬＳＩパ
、ケージを得る。(g) Plating the surface of the glue 8 protruding from the cage part 10 with KXP. (hl, lead 8 only rim 1
Cut the number 6 at the root. In this state, each lead is electrically independent], so (1) the lead frame is handled as is, the characteristics of each package are measured, and the packages are sorted and sorted. (j) As a result of the above measurement, bend and form a good piece. (kl) The rim portion is broken from the recess 19 of the dummy lead 18 to obtain the LSI cage shown in FIG.
こσ）ようにして製造さハたＬＳＩパッケージσつぎの
ような効果を奏する。The LSI package σ manufactured in this way has the following effects.
（１） 金属板からリードフレームを形成し７、この
リードフし・−ムを第１・第２外囲器で挾持接着するだ
けであり、従来のように、スルーホール部等を有するセ
ラミンク板の和１層などにくらベニ数が不妊くなるはめ
、製造コストが軽減される。(1) A lead frame is formed from a metal plate 7, and this lead frame is simply sandwiched and bonded between the first and second envelopes. The manufacturing cost is reduced because the number of layers becomes infertile in the case of one layer.
（２） リードはリードフレームの状態で第１・第２
外囲器で挾持接着することから、各リードの間隔は加工
時の寸法が保持さＪまた状態で第１・第２外囲器に固定
される。このため、ワイヤボンティングにあっては、自
動ボンダーを用いても正確なワイヤボンディングかでき
る。したがって、ワイヤボンディングの作業性が著しく
向上する。(2) Connect the first and second leads in the lead frame state.
Since the leads are sandwiched and bonded by the envelope, the intervals between the leads are fixed to the first and second envelopes while maintaining the dimensions at the time of processing. Therefore, in wire bonding, accurate wire bonding can be performed even if an automatic bonder is used. Therefore, the workability of wire bonding is significantly improved.
（３） η−ドは従来のメタライズに代わり、コバー
ル、鉄−ニッケル４２合金等の金属で形作れるため、抵
抗が低くなる。(3) Since the η-de can be formed from metals such as Kovar and iron-nickel 42 alloy instead of conventional metallization, the resistance is lower.
（４） 金属板からリードフレームを作るため、各リ
ード間の距離は０．１ ｍｍ程度にまで狭くすることが
できる、このため、従来の接層セラミンクバフケージ構
造に較べて製品の小型化を図ることができる。(4) Since the lead frame is made from a metal plate, the distance between each lead can be narrowed to about 0.1 mm, which makes the product smaller compared to the conventional bonded ceramic buff cage structure. can be achieved.
（５）放熱板（″ヒートシンク）に回路累子を取付けた
第２外囲器側に固定されている。し７たがって、伝熱抵
抗が軽減され、放熱効果が向上する。(5) It is fixed to the second envelope side to which the circuit resistor is attached to the heat sink (heat sink). Therefore, the heat transfer resistance is reduced and the heat dissipation effect is improved.
（６）第１・第２外囲器、支持板各部の接着は低融点ガ
ラスシール方式と（でいるため、気密性等の信頼度が高
い。(6) The first and second envelopes and each part of the support plate are bonded using a low melting point glass seal method, so the reliability of airtightness etc. is high.
（７）第１・第２外囲器はアルミナからなる絶縁物で形
＋１ｉＶされ−ｒいるため、容址ケ低減できる。(7) Since the first and second envelopes are made of insulators made of alumina and have a voltage of +1 iV, the volume can be reduced.
（８） 従来の積層セラミ、クバ、ケージ構造に較べ
て材質組合せを単純化できる。また、この−例走して、
第２外囲器へＱ）支持板の取り付けを銀鑞等で行なうと
、セラミックにメタライズ、メッキ等が必要となるが、
封止用ガラスで取付けることにより工程を簡略化できる
。(8) Material combinations can be simplified compared to conventional laminated ceramic, wall, and cage structures. Also, with this example run,
Q) If the support plate is attached to the second envelope using silver solder, etc., metallization, plating, etc. will be required on the ceramic.
The process can be simplified by attaching with sealing glass.
（９） リードはプリント基板（プリント配線基板）
に重ね合せる構造となっている。 １．、、たかって、
プリント基板においては、リードを挿し込む孔を設けな
くともよい・ことから、プリント基板の配線ノくターン
の微細化を図ることができ、実装密度σ巾」上を図るこ
とができる。ｔた、各リードにプリント基板に半田等を
介して固定さＪＩるか、この際、パッケージ部に外力が
加わっても、リードの屈曲部が弾力的に作用するため、
リードがプリント基板から剥離することがない。(9) Leads are printed circuit boards (printed wiring boards)
It has a structure in which it is superimposed on the 1. ,,Takate,
Since there is no need to provide a hole for inserting a lead in a printed circuit board, the wiring nozzle on the printed circuit board can be made finer, and the packaging density σ width can be increased. In addition, each lead is fixed to the printed circuit board via solder or the like, and in this case, even if an external force is applied to the package part, the bent part of the lead acts elastically.
The leads will not peel off from the printed circuit board.
第５図にｄダミーリード１８によりリム１６に支持さｆ
ｑ＊ＬｓＩパッケージ２０をプリント基板（プリント配
線基板）２２に取付けた。ＬＳＩノぐンケージ２０のヒ
ートシンク］４ｖＣ１ｄ７１Ａフィン２１が取り付けら
ねでいる。ＬＳＩノ・ノケージはダミーリード１８ＶＣ
よりリム１６π支持ａｈた状態で市販することもできる
。その場合、市販されたＬＳＩパッケージは使用者側で
プリント基板に取付けることになるが取付けにあたって
は、前記リードフレーム１５のリム１６の隅部のガイド
孔１７を利用してプリント基板２２ Ｋ位置決めを行な
い、リード８を半田でプリント基板２２０４重層に固定
（５、その稜、リム１６を把んでプリント基板２２から
遠ざかるように引＠離すことにより。In FIG. 5, d is supported on the rim 16 by dummy leads
The q*LsI package 20 was attached to a printed circuit board (printed wiring board) 22. Heat sink of LSI gun cage 20] 4vC1d71A fin 21 is attached. LSI no cage is dummy lead 18VC
It can also be commercially available in a state where the rim is supported more than 16π. In that case, the commercially available LSI package must be attached to the printed circuit board by the user, but during attachment, the printed circuit board 22K is positioned using guide holes 17 at the corners of the rim 16 of the lead frame 15. , Fix the lead 8 to the printed circuit board 2204 layer with solder (5. By grasping its edge and rim 16 and pulling it away from the printed circuit board 22.
ダミーリード１８の凹部１９を破断１２、パッケージを
リム］６から分＃することができる。このように、ダミ
ーリード１８によりリム１６に支持接続さねた状態でＬ
ＳＩパ・ノケージを販売しても前記カイト孔１７を利用
（、てプリント基板への取り付けを正確に行うことがで
き、捷た凹部１９の部分から簡単Ｗパッケージをリム１
６から分離イることができる。By breaking the recess 19 of the dummy lead 18, the package can be separated from the rim 6. In this way, the L is supported and connected to the rim 16 by the dummy lead 18.
Even if the SI package is sold, the kite hole 17 can be used to accurately attach the W package to the printed circuit board.
It can be separated from 6.
なお、本発明は前記実施例に限定さねない。たとλは、
前記第２外囲器中央の支持板とヒートシンク等の放熱部
を例えばＭｏ、酸化べＩＪ ＩＪウム等の同一材料で一
体的に形成（−５でもよい。オた、第２外囲器を金属板
で作り、第１外囲器と接する周縁部に絶縁物を被着させ
る構造でもよい。また、第６図に示すように、第２外囲
器３０への支持板３１の取り付けは補強板を用いること
なく、カラス３２で固定するようにしてもよい。こＩり
際、支持板３１の周縁を被うようにカラスを耐着させる
。Note that the present invention is not limited to the above embodiments. and λ is
The support plate at the center of the second envelope and the heat dissipation part such as a heat sink are integrally formed of the same material such as Mo, aluminum oxide, aluminum oxide, etc. (-5 is also acceptable. It may be made of a plate and an insulator is applied to the peripheral edge in contact with the first envelope.Furthermore, as shown in FIG. 6, the support plate 31 is attached to the second envelope 30 using a reinforcement plate It is also possible to fix it with a crow 32 without using the crow.When it is finished, the crow is attached so as to cover the periphery of the support plate 31.
以上のように、本発明のＬＳＩパッケージによりば、リ
ードを金属を用いて形成することから、従来のようにメ
タライズしたもσ）よりも電気抵抗が低くなる。（たが
って、リードの幅を狭くできる。捷たリード間隔を狭く
することができるσ）で、ＬＳＩパッケージの小型化を
図ることができる。As described above, according to the LSI package of the present invention, since the leads are formed using metal, the electrical resistance is lower than that of the conventional metallized package (σ). (Thus, the width of the leads can be narrowed. The gap between the twisted leads can be narrowed.) Accordingly, the LSI package can be made smaller.
また、ベレントを固定（、た外囲器側に、しかも熱伝導
度σ）良好な板に放熱体を固定する構造することにより
、従来の批棹ｔｓｒノく、ケージに較べて極めて放熱性
が良好となる。、
また、本発明によｔｌげ、金属板からリードフレームを
作るため、各部の位置関係が正しく保たれる。また、リ
ードフレームに設けたカイト孔等を用いることにより、
各種の組立、取り付けの自動化な図ることができる。In addition, by fixing the heat dissipation body to a plate with good thermal conductivity σ on the side of the envelope, the heat dissipation performance is extremely high compared to the conventional cage. Becomes good. Furthermore, since the lead frame is made from a metal plate according to the present invention, the positional relationship of each part can be maintained correctly. In addition, by using a kite hole etc. provided in the lead frame,
Various types of assembly and installation can be automated.
また、ガラス封止構造とすることにより、気密性が優れ
、信頼度の高いＬＳＩパ、ン夛−ジを提供することがで
きる。Further, by using a glass-sealed structure, it is possible to provide an LSI package with excellent airtightness and high reliability.
さらに、この発明によれは、各部の構造が単純化できる
ため、材料軽減１組立σ）容易性等の理由から、安価な
ＬＳＩパッケージを提供イることかできるなど多くの効
果を奏する１、Furthermore, the present invention has many effects such as being able to provide an inexpensive LSI package due to the simplicity of the structure of each part, material reduction, ease of assembly, etc.1.
第１図は本発明を適用したセラミックパンケージ型半導
体装１〃の酊１１Ａ’ｉ ｔ￥１．第２図ｄ本発明の実
施例の製造工程を示す工程図、第３図１ｉ１使用する１
）−ドフレームの平面図、第４図は封止工程後の組立状
態を示す平面図、第５図はダミーリードによりリム１６
に支持接続さ７またＬＳＩパ、ケージをプリント基板に
取り付けた状態を示す断面図、第６図は他のパッケージ
構造の一部断面図である、１・・・第１外囲器、２・・
・窪み、３・・・第２外囲器、４・・・金属板（支持板
）、５・・・カラス、６・・・補強板、７・・・ガラス
、８・・・リード、９・・・ガラス、】０・・・パッケ
ージ部、１１・・・回路素子、１２・・・金−シリコン
共晶合金層、１３・・・ワイヤ、ｊ４・・・ヒートシン
ク、１５・・・リードフレーム、１６・・・リム、１７
・・・ガイド孔、１８・・・ダミーリード、１９・・・
凹部、２０・・・ＬＳＩパッケージ、２１・・・放熱フ
ィン、２２・・・プリント基板、３０・・・第２外囲器
、３】・・・支持枦、３２・・・ガラス。
２、”、 ｉ Ｉｌ
第 ３ 渕 ７７ 、、、、／ａ
′ ／
６１°９２ 図FIG. 1 shows a ceramic pancage type semiconductor device 1 to which the present invention is applied. Fig. 2 d A process diagram showing the manufacturing process of an embodiment of the present invention, Fig. 3 1i1 Used 1
) - A plan view of the frame, Fig. 4 is a plan view showing the assembled state after the sealing process, Fig. 5 is a plan view of the rim 16 with dummy leads.
7 is a cross-sectional view showing a state in which the LSI package is attached to a printed circuit board, and FIG. 6 is a partial cross-sectional view of another package structure.・
- Hollow, 3... Second envelope, 4... Metal plate (support plate), 5... Crow, 6... Reinforcement plate, 7... Glass, 8... Lead, 9 ... Glass, ]0 ... Package part, 11 ... Circuit element, 12 ... Gold-silicon eutectic alloy layer, 13 ... Wire, j4 ... Heat sink, 15 ... Lead frame , 16... rim, 17
...Guide hole, 18...Dummy lead, 19...
Recessed portion, 20...LSI package, 21...Radiation fin, 22...Printed circuit board, 30...Second envelope, 3]...Support lever, 32...Glass. 2,”, i Il 3rd buchi 77,,,,/a
' / 61°92 Figure
Claims (1)
または支持用リードにより外枠に支持さｆまた状態で、
上記複数のリードのうち所望のものを所定の形状に形成
することを特徴とする電子回路装置のリード形成法。1. In a state in which a plurality of leads protrude from the sealing body and are supported by the outer frame by a plurality of leads or supporting leads,
A method for forming leads for an electronic circuit device, characterized in that a desired one of the plurality of leads is formed into a predetermined shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58226841A JPS59139659A (en) | 1983-12-02 | 1983-12-02 | Method for formation of lead for electronic circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58226841A JPS59139659A (en) | 1983-12-02 | 1983-12-02 | Method for formation of lead for electronic circuit device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2477377A Division JPS53110371A (en) | 1977-03-09 | 1977-03-09 | Ceramic package type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59139659A true JPS59139659A (en) | 1984-08-10 |
Family
ID=16851404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58226841A Pending JPS59139659A (en) | 1983-12-02 | 1983-12-02 | Method for formation of lead for electronic circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59139659A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6364077U (en) * | 1986-06-02 | 1988-04-27 |
-
1983
- 1983-12-02 JP JP58226841A patent/JPS59139659A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6364077U (en) * | 1986-06-02 | 1988-04-27 |
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