JPS60258944A - Ic device - Google Patents
Ic deviceInfo
- Publication number
- JPS60258944A JPS60258944A JP60026201A JP2620185A JPS60258944A JP S60258944 A JPS60258944 A JP S60258944A JP 60026201 A JP60026201 A JP 60026201A JP 2620185 A JP2620185 A JP 2620185A JP S60258944 A JPS60258944 A JP S60258944A
- Authority
- JP
- Japan
- Prior art keywords
- package
- leads
- fixed
- plate
- envelope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は高密度、高速ロジック用セラミックパッケージ
型ＬＳＩ（大規模集積回路）に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ceramic package type LSI (Large Scale Integrated Circuit) for high-density, high-speed logic.
放熱型のパッケージ構造については、例えば、特開昭４
９−６２０８４号公報にセラミック・パッケージの一外
面にフィン付き放熱スタッドを取りつけたものが示され
ている。Regarding the heat dissipation type package structure, for example,
No. 9-62084 discloses a ceramic package in which a finned heat dissipation stud is attached to one outer surface.
従来、高密度、高速ロジック用セラミックパッケージ型
ＬＳＩ（以下単にＬＳＩパッケージと称する。）は積層
セラミックパッケージ構造からなり、プリント基板（プ
リント板）等の配線基板にリードを介して取り付けられ
る。このＬＳＩパッケージはプリント板側のセラミック
板（セラミック基板）からなる外囲器（ベース）内に半
導体素子（ペレット）を固定するとともに、プリント板
から離れる他のセラミック板からなる外囲器（キャップ
）の外面に放熱用の全域からなるヒートシンク（フィン
）が設けられている。Conventionally, high-density, high-speed logic ceramic package type LSIs (hereinafter simply referred to as LSI packages) have a multilayer ceramic package structure, and are attached to a wiring board such as a printed circuit board via leads. In this LSI package, a semiconductor element (pellet) is fixed in an envelope (base) made of a ceramic board (ceramic board) on the printed board side, and an envelope (cap) made of another ceramic board separate from the printed board. A heat sink (fin) consisting of an entire area for heat dissipation is provided on the outer surface of the fin.
しかし、従来の積層セラミックパッケージ構造では次の
ような欠点がある。However, the conventional laminated ceramic package structure has the following drawbacks.
＋１１ 積層セラミックパッケージ構造は多数枚のセラ
ミック板を積み重ねたり、各セラミック板にスルーホー
ルを設けてこの孔に導電材を充満させ、セラミック板上
下面の配線を電気的に接続させるなど複雑となることか
ら製造コストが高い。+11 The structure of a multilayer ceramic package is complicated by stacking many ceramic plates, providing through holes in each ceramic plate, filling the holes with conductive material, and electrically connecting the wiring on the top and bottom surfaces of the ceramic plates. Manufacturing costs are high.
（２１積層セラミックパッケージ構造はセラミック基板
に形成するメタライズ層の加工寸法の公差を±１％以内
の値にすることがむずかしい。したがってセラミック板
上にメタライズされて形成されたリードの内端とペレッ
トの電極とをワイヤで接続するボンディング作業にあっ
て、公差が太きいため自動化が困難となり、ポンディン
グ加工時間が太ぎくなる。また、信頼性も悪くなる。(21) In the multilayer ceramic package structure, it is difficult to keep the processing dimension tolerance of the metallized layer formed on the ceramic substrate within ±1%. Therefore, it is difficult to maintain the tolerance of the processing dimensions of the metallized layer formed on the ceramic substrate within ±1%. In the bonding process, in which electrodes are connected with wires, automation is difficult due to large tolerances, which increases the bonding process time and also reduces reliability.
（３１配線が導電性ペーストのメタライズによるため、
抵抗が高くなりやすく、低抵抗にするために。(31 wiring is based on metallization of conductive paste,
To make it easier for the resistance to become high and to make it low resistance.
メタライズ幅を大きくとることからパッケージ全体が大
きくなり易い。Since the metallization width is large, the entire package tends to become large.
（４１ツタライズ配線間隔はスルーホールの孔径との関
係から、スルーホール径（たとえば一般的な技術的最小
値は０．３ ｗφ）よりも小さくできない。(Due to its relationship with the diameter of the through-hole, the pitch between the 41 twin wires cannot be made smaller than the diameter of the through-hole (for example, the general technical minimum value is 0.3 wφ).
このためＬＳＩパンケージの小型化が図ねない。For this reason, it is impossible to reduce the size of the LSI pancake.
すなわち、従来ではゲート数が１００ 、 ＩＪ−ド数
が５０程度のものが最も大規模なものであるが、素子数
９０００個、ゲート数４００．リード数１００程度のＬ
ＳＩが要求される現在にあっては、従来の積層パッケー
ジ構造で作ると極めて大きなものとなってしまい好まし
くない。That is, conventionally, the largest scale device has about 100 gates and 50 IJ-dodes, but the largest one has 9000 elements and 400 gates. L with about 100 leads
In today's world where SI is required, making it using the conventional stacked package structure would result in an extremely large package, which is undesirable.
（５）放熱板はペレットを取り付けたベースに直接固定
されず、キャンプに固定されている。したがって、熱の
大部分はベース、ベースとキャップとの接合枠部、キャ
ップ、放熱板の順序で伝わるため、放熱性が低い。また
、セラミック自体は金属等に較べて熱伝導度が低いとい
う欠点もある。(5) The heat sink is not directly fixed to the base to which the pellets are attached, but is fixed to the camp. Therefore, most of the heat is transmitted in this order: the base, the joint frame between the base and the cap, the cap, and the heat sink, resulting in poor heat dissipation. Additionally, ceramic itself has a drawback of having lower thermal conductivity than metals and the like.
本発明はこのような欠点を解消するものであって、その
目的は低廉なＬＳＩパッケージを提供することにある。The present invention is intended to eliminate such drawbacks, and its purpose is to provide an inexpensive LSI package.
また、本発明の他の目的は、ＬＳＩパッケージの小型化
を図ることにある。Another object of the present invention is to reduce the size of an LSI package.
また、本発明のさらに他の目的は気密性等の信頼度の高
いＬＳＩパッケージを提供することにある。Still another object of the present invention is to provide an LSI package with high reliability such as airtightness.
さらに、本発明の他の目的は熱抵抗を可及的に低くする
ことによって放熱性の良好なＬＳＩパッケージを提供す
ることにある。Furthermore, another object of the present invention is to provide an LSI package with good heat dissipation by lowering the thermal resistance as much as possible.
このような目的を達成するために本発明は、一チツプを
セラミックではなく、熱伝導性の良好なメタル板に固着
することにより、チップより発生する熱をパッケージ外
部に効率的に取り出し、更に放熱フィンにより外界に放
出するようにしたものである。In order to achieve these objectives, the present invention aims to efficiently extract the heat generated by the chip to the outside of the package by fixing one chip to a metal plate with good thermal conductivity instead of ceramic, and further improves heat dissipation. The fins are used to emit it to the outside world.
第１図は本発明のＬＳＩパッケージの一実施例を示す。FIG. 1 shows an embodiment of an LSI package of the present invention.
同図において１は例えば矩形のセラミック板からなる第
１外囲器である。この第１外囲器ｌはプリント板などか
らなる配線板（図示せず）に対面（図では上面がプリン
ト板に対面する。）する。そして、その反対面（図中下
面）の中央部は窪み２を有している。３け前記第１外囲
器１と同じ大きさのセラミック板からなる第２外囲器で
あ−で、その中央部は円形又は角形に抜けている。In the figure, reference numeral 1 denotes a first envelope made of, for example, a rectangular ceramic plate. This first envelope l faces a wiring board (not shown) made of a printed board or the like (in the figure, the upper surface faces the printed board). The center portion of the opposite surface (lower surface in the figure) has a depression 2. The second envelope is made of three ceramic plates of the same size as the first envelope 1, and has a circular or square hole in the center.
そして、この円形部又は角形は２段の段付孔となってい
て、下面の広径部には熱伝導度の良好なモリブデン、タ
ングステンなどからなる金属板（支持板）４がガラス５
を介して固定されている。また、金属とガラスは接合強
度が弱いことから、補強板６を用い、この補強板６と第
２外囲器３とで前記支持板４を挾み込むようにしている
。すなわち、補強板６は外周は第２外囲器３と同じ形状
をし、内周は第２外囲器３の内径部と同じ大きさになっ
ていて、ガラス７で第２外囲器３および支持板４に接着
している。This circular or square part has a two-stage stepped hole, and a metal plate (supporting plate) 4 made of molybdenum, tungsten, etc., which has good thermal conductivity, is attached to the glass 5 in the wide diameter part on the bottom surface.
has been fixed through. Further, since the bonding strength between metal and glass is weak, a reinforcing plate 6 is used, and the supporting plate 4 is sandwiched between the reinforcing plate 6 and the second envelope 3. That is, the reinforcing plate 6 has an outer periphery that has the same shape as the second envelope 3, an inner periphery that has the same size as the inner diameter of the second envelope 3, and a glass 7 that is connected to the second envelope 3. and is adhered to the support plate 4.
また、８は前記第１外囲器１と第２外囲器３との間にガ
ラス９を介して挾持固着さハる複数のリードである。こ
のリード８はコバール、鉄−ニッケル４２合金等の薄板
をエツチングやプレスによって形成されたものであり、
第１外囲器１と第２外囲器３とからなるパッケージ部１
０の内にあっては、第２外囲器３の上面に沿って延びる
とともに、パッケージ部１０の外にあっては２箇所で屈
曲し、その先端部は第１外囲器１の上面とほぼ同一の平
面上あるいは前記上面よりわずかに突出した面に沿うよ
うに延びている。そして、こわらのり一ド８の外端部は
プリント配線基板（図示せず）の端子部に重なり合うよ
うになっている。Further, reference numeral 8 denotes a plurality of leads which are sandwiched and fixed between the first envelope 1 and the second envelope 3 with a glass 9 interposed therebetween. This lead 8 is formed by etching or pressing a thin plate of Kovar, iron-nickel 42 alloy, etc.
Package part 1 consisting of a first envelope 1 and a second envelope 3
0, it extends along the top surface of the second envelope 3, and is bent at two places outside the package part 10, with its tip end meeting the top surface of the first envelope 1. They extend along substantially the same plane or along a surface slightly protruding from the upper surface. The outer end of the stiff glue 8 overlaps a terminal portion of a printed wiring board (not shown).
また、１１は素子数がたとえば９０００個を有するシリ
コン板からなるＬＳＩ素子（ペレット）であって、前記
支持板４のパッケージ部１０の内面に例えば金−シリコ
ン共晶合金層】２を介して固定されている。１３は金線
あるいはアルミニウム線等からなるワイヤであって、超
音波ボンディング方法や熱圧着方法でペレットの電極と
り一ド８の内端を繋いでいる。１４は銅、アルミニウム
等の熱伝導度の良好な金属等からなる柱状のヒ−トシン
クであり、圧接又は鑞付けによって前記支持板４の外面
（図中下面）に固定されている。なお、このヒートシン
クには第５図に示すように、放熱フィンを取り付け、放
熱性をさらに高めてもよい。Reference numeral 11 denotes an LSI element (pellet) made of a silicon plate having, for example, 9,000 elements, and is fixed to the inner surface of the package portion 10 of the support plate 4 via, for example, a gold-silicon eutectic alloy layer 2. has been done. Reference numeral 13 denotes a wire made of gold wire, aluminum wire, or the like, which connects the inner ends of the electrode sections 8 of the pellet by ultrasonic bonding or thermocompression bonding. Reference numeral 14 denotes a columnar heat sink made of a metal with good thermal conductivity such as copper or aluminum, and is fixed to the outer surface (lower surface in the figure) of the support plate 4 by pressure welding or brazing. Incidentally, as shown in FIG. 5, heat dissipation fins may be attached to this heat sink to further improve heat dissipation.
つぎに、このよりなＴ、 Ｓ Ｉパッケージの製造工程
について第２図を用いて簡単に説明する。ｔａ＋、第３
図で示すようなリードフレーム１５を用意する。このリ
ードフレーム１５はシリコンの熱膨張係数と近似するコ
バールや４２合金等からなる薄い板、たとえば０．１龍
の厚さの板をエツチング技術や精密プレス技術を用いて
形成する。この場合、各リード８間の距離は板厚とほぼ
同じ程度まで狭く形成できる。また寸法公差は±０．２
〜０．３％にすることができる。各リード８は矩形枠か
らなるリム１６の各辺から枠中央に向かって延びている
。Next, the manufacturing process of this flexible T, SI package will be briefly explained using FIG. 2. ta+, 3rd
A lead frame 15 as shown in the figure is prepared. The lead frame 15 is formed from a thin plate made of Kovar or 42 alloy, which has a coefficient of thermal expansion similar to that of silicon, for example, a plate having a thickness of 0.1 mm, using etching technology or precision pressing technology. In this case, the distance between each lead 8 can be narrowed to approximately the same extent as the plate thickness. Also, the dimensional tolerance is ±0.2
~0.3%. Each lead 8 extends from each side of a rim 16 made of a rectangular frame toward the center of the frame.
また、矩形枠の四隅は幅広に形成されており、該： 部
には円形あるいは長孔からなるハンドリングおよび位置
決め用のガイド孔１７が設けられている。Further, the four corners of the rectangular frame are formed wide, and guide holes 17 for handling and positioning, which are circular or elongated holes, are provided in these corners.
また、矩形枠の四隅にはダミーリード１８が設けられて
いる。このダミーリード１８には凹部１９が設けられ、
外力を加えると簡単に凹部１９で破断するようになって
いる。この凹部１９は第１０第２外囲器１．３の外周縁
部上に位置する部分に設けられている。Furthermore, dummy leads 18 are provided at the four corners of the rectangular frame. This dummy lead 18 is provided with a recess 19,
It is designed to easily break at the recess 19 when external force is applied. This recess 19 is provided in a portion located on the outer peripheral edge of the tenth second envelope 1.3.
（ｂ）、このようなリードフレーム１５の各リード８の
先端のワイヤ取付部に蒸着法あるいはめつき法によって
アルミニウム被膜あるいは金被膜を形成する。ｌｅｔ、
ヒートシンク１４を固定した支持板４を補強板６および
高信頼度の低融点フリットガラスを用いて第２外囲器３
に固定する。ｌｄｌ、ベレット１１を支持板のベレット
を取り付ける部分に部分的に形成したＡｕ層を介して支
持板４に固定する。ｌｅｌ、ベレットの電極とリードと
の間をワイヤボンディングにより電気的に接続する。ｌ
ｆ＋、第１外囲器ｌを第２外囲器３に低融点ガラスフリ
ットを介して重ね合せ、第４図に示すように、加熱溶融
により一体的に気密封止する。(b) An aluminum film or a gold film is formed on the wire attachment portion at the tip of each lead 8 of the lead frame 15 by vapor deposition or plating. Let,
The support plate 4 to which the heat sink 14 is fixed is attached to the second envelope 3 using a reinforcing plate 6 and highly reliable low melting point frit glass.
Fixed to. ldl, the pellet 11 is fixed to the support plate 4 via an Au layer partially formed on the part of the support plate where the pellet is attached. The electrodes of the pellet and the lead are electrically connected by wire bonding. l
f+, the first envelope 1 is stacked on the second envelope 3 via a low-melting glass frit, and as shown in FIG. 4, the first envelope 1 is hermetically sealed integrally by heating and melting.
Ｉｇ＋、パッケージ部１０から突出するり一ド８の表面
に半田をめっきする。（川、リード８のみをリーム１６
の付は根部分で切断する。この状態では、各リードは電
気的に独立していることから、＋１＋、リードフレーム
のまま取り扱うて各パッケージの特性測定を行ない、選
別分類する。（ｊｌ、前記測定の結果、良品はリードを
折り曲げ成形する。（ｋ）、リム部をダミーリード１８
の凹部１９から破断させて、第１図で示すＬＳＩパッケ
ージを得る。Solder is plated on the surface of the adhesive 8 protruding from the Ig+ package part 10. (River, lead 8 only ream 16
Cut the nosuke at the root. In this state, since each lead is electrically independent, each package is treated as a lead frame, the characteristics of each package are measured, and the packages are sorted and sorted. (jl, As a result of the above measurement, if the product is good, the lead is bent and formed. (k), The rim part is formed by dummy lead 18.
The LSI package shown in FIG. 1 is obtained by breaking the package from the recess 19.
このようにして製造されたＬＳＩパッケージはつぎのよ
うな効果を奏する。The LSI package manufactured in this manner has the following effects.
（１）金属板からリードフレームを形成し、このリード
フレームを第１・第２外囲器で挟持接着するだけであり
、従来のように、スルーホール部等を有するセラミック
板の積層などにくらベニ数が小さくなるため、製造コス
トが軽減される。(1) Simply form a lead frame from a metal plate and sandwich and bond this lead frame between the first and second envelopes. Manufacturing costs are reduced because the number of strips is smaller.
（２） リードはリードフレームの状態で第１・第２外
囲器で挟持接着することから、各リードの間隔は加工時
の寸法が保持された状態で第１・第２外囲器に固定され
る。このため、ワイヤボンディングにあっては、自動ボ
ンター−を用いても正確なワイヤボンディングができる
。したがって、ワイヤボンディングの作業性が著しく向
上する。(2) Since the leads are sandwiched and bonded between the first and second envelopes in the lead frame state, the intervals between each lead are fixed to the first and second envelopes while maintaining the dimensions at the time of processing. be done. Therefore, in wire bonding, accurate wire bonding can be performed even if an automatic bonder is used. Therefore, the workability of wire bonding is significantly improved.
（３１リードは従来のメタライズに代わり、コバール、
鉄−ニッケル４２合金等の金属で形作られるため、抵抗
が低くなる。(31 leads are made of Kovar, instead of conventional metallization.
Since it is made of metal such as iron-nickel 42 alloy, it has low resistance.
（４１金属板からリードフレームを作るため、各リード
間の距離は０．１ ｍｔｘ程度にまで狭くすることがで
きる。このため、従来の積層セラミックパッケージ構造
に較べて製品の小型化を図ることができる。(Since the lead frame is made from a 41 metal plate, the distance between each lead can be reduced to about 0.1 mtx. Therefore, compared to the conventional laminated ceramic package structure, the product can be made smaller. can.
（５）放熱板（ヒートシンク）は回路素子を取付けた第
２外囲器側に固定されている。したがって、伝熱抵抗が
軽減され、放熱効果が向上する。(5) A heat sink is fixed to the second envelope side to which the circuit elements are attached. Therefore, heat transfer resistance is reduced and heat dissipation effect is improved.
（６）第１・第２外囲器、支持板各部の接着は低融点ガ
ラスシール方式としているため、気密性等の信頼度が高
い。(6) Since the first and second envelopes and each part of the support plate are bonded using a low melting point glass sealing method, the reliability of airtightness etc. is high.
（７１第１−第２外囲器はアルミナからなる絶縁物で形
成されているため、容量を低減できる。(71 Since the first and second envelopes are formed of an insulator made of alumina, the capacitance can be reduced.
（８１従来の積層セラミックパッケージ構造に較べて材
質組合せを単純化できる。また、この−例として、第２
外囲器への支持板の取り付けを鋏鑞等で行なうと、セラ
ミックにメタライズ、メッキ等が必要となるが、封止用
ガラスで取付けることにより工程を簡略化できる。(81) The combination of materials can be simplified compared to the conventional laminated ceramic package structure.
If the support plate is attached to the envelope using scissors or the like, metallization, plating, etc. will be required on the ceramic, but the process can be simplified by attaching it with sealing glass.
（９） リードはプリント基板（プリント配線基板）に
重ね合せる構造となっている。したがって、プリント基
板においては、リードを挿し込む孔を設けなくともよい
ことから、プリント基板の配線パターンの微細化を図る
ことができ、実装密度の向上を図ることができる。また
、各リードはプリント基板に半田等を介して固定される
が、この際、パッケージ部に外力が加わっても、リード
の屈曲部が弾力的に作用するため、リードがプリント基
板から剥離することがない。(9) The lead is structured to be superimposed on a printed circuit board (printed wiring board). Therefore, since there is no need to provide holes for inserting leads in the printed circuit board, the wiring pattern of the printed circuit board can be made finer, and the packaging density can be improved. In addition, each lead is fixed to the printed circuit board via solder, etc., but at this time, even if external force is applied to the package part, the bent part of the lead acts elastically, so the lead may peel off from the printed circuit board. There is no.
第５図にはダミーリード１８によりリム１６に支持され
たＬＳＩパッケージ２０をプリント基板（プリント配線
基板）２２に取付けた。ＬＳＩパッケージ２０のヒート
シンク１４には放熱フィン２１が取り付けられている。In FIG. 5, an LSI package 20 supported on a rim 16 by dummy leads 18 is attached to a printed circuit board (printed wiring board) 22. A radiation fin 21 is attached to the heat sink 14 of the LSI package 20.
ＬＳＩパッケージはダミーリード１８によりリム１６に
支持された状態で市販することもできる。その場合、市
販されたＬＳＩパッケージは使用者側でプリント基板に
取付けることになるが取付けにあたっては、前記リード
フレーム１５のリム１６の隅部のガイド孔１７を利用し
てプリント基板２２に位置決めを行ない、リード８を半
田でプリント基板２２の導電層に固定し、その後、リム
１６を把んでプリント基板２２から遠ざかるように引き
離すことにより、ダミーリード１８の凹部１９を破断し
、パッケージをリム１６から分離することができる。こ
のように、ダミーリード１８によりリム１６に支持接続
された状態でＬＳＩパッケージを販売しても前記ガイド
孔】７を利用してプリント基板への取り付けを正確に行
うことができ、また四部１９０部分から簡単にパッケー
ジをリム１６から分離することができる。The LSI package can also be sold on the market in a state where it is supported on the rim 16 by dummy leads 18. In that case, the commercially available LSI package will be attached to the printed circuit board by the user, but during attachment, the guide holes 17 at the corners of the rim 16 of the lead frame 15 are used to position the package on the printed circuit board 22. , the leads 8 are fixed to the conductive layer of the printed circuit board 22 with solder, and then the rim 16 is grasped and pulled away from the printed circuit board 22 to break the recess 19 of the dummy lead 18 and separate the package from the rim 16. can do. In this way, even if the LSI package is sold in a state where it is supported and connected to the rim 16 by the dummy leads 18, it can be accurately attached to the printed circuit board by using the guide hole 7, and the four parts 190 The package can be easily separated from the rim 16.
なお、本発明は前記実施例に限定されない。たとえば、
前記第２外囲器中央の支持板とヒートシンク等の放熱部
を例えばＭｏ＋酸化ぺＩＪ ＩＪウム等の同一材料で一
体的に形成してもよい。また、第２外囲器を金属板で作
り、第１外囲器と接する周縁部に絶縁物を被着させる構
造でもよい。また、第６図に示すように、第２外押器３
０への支持板３１の取り付けは補強板を用いることなく
、ガラス３２で固定するようにしてもよい。この際、支
持板３１の周縁を被うようにガラスを耐着させる。Note that the present invention is not limited to the above embodiments. for example,
The support plate at the center of the second envelope and the heat dissipation portion such as a heat sink may be integrally formed of the same material, such as Mo+peIJIJium oxide. Alternatively, the second envelope may be made of a metal plate, and an insulating material may be applied to the peripheral edge in contact with the first envelope. In addition, as shown in FIG. 6, the second external pusher 3
The support plate 31 may be fixed to the glass 32 without using a reinforcing plate. At this time, the glass is made to adhere so as to cover the peripheral edge of the support plate 31.
以上のように、本発明によれば、ペレットを固定した外
囲器側に、しかも熱伝導度の良好な板に放熱体を固定す
る構造となることから、従来の此種ＬＳＩパンケージに
較べて極めて放熱性が良好となる。As described above, according to the present invention, the heat dissipation body is fixed to the side of the envelope to which the pellets are fixed, and also to a plate with good thermal conductivity, so compared to the conventional LSI pancage of this type. Heat dissipation becomes extremely good.
さらに、この発明によれば、各部の構造が単純化できる
ため、材料軽減２組立の容易性等の理由から、安価なＬ
ＳＩパッケージを提供することができるなど多くの効果
を奏する。Furthermore, according to the present invention, since the structure of each part can be simplified, it is possible to reduce the cost of L
This has many effects such as being able to provide an SI package.
第１図は本発明のセラミックパッケージ型半導体装置の
一笑施例による断面図、第２図１ａｌ〜（ｋ＋は同じく
製造工程を示す工程図、第３図は使用するリードフレー
ムの平面図、第４図は封止工程後の組立状態を示す平面
図、第５図はダミーリードによりリム１６に支持接続さ
れたＬＳＩパッケージをプリント基板に取り付けた状態
を示す断面図、第６図は本発明の他の実施例を示す一部
断面図である。
１・・・第１外囲器、２・・・窪み、３・・・第２外囲
器、４・・・金属板（支持板）、５・・・ガラス、６・
・・補強板、７・・・ガラス、８・・・リード、９・・
・ガラス、１０・・・パッケージ部、１１・・・回路素
子、１２・・・金−シリコン共晶合金層、１３・・・ワ
イヤ、１４・・・ヒートシンク、１５・・・リードフレ
ーム、１６・・・リム、１７・・・ガイド孔、１８・・
・ダミーリード、１９・・・凹部、２０・・・ＬＳＩパ
ッケージ、２１・・・放熱フィン、２２・・・プリント
基板、３０・・・第２外囲器、３１・・・支持板、３２
・・・ガラス。
第 １ 図
第 ２ 図FIG. 1 is a sectional view of an embodiment of the ceramic packaged semiconductor device of the present invention, FIG. 2 is a process diagram showing the manufacturing process, FIG. The figure is a plan view showing the assembled state after the sealing process, FIG. 5 is a sectional view showing the state in which the LSI package supported and connected to the rim 16 by dummy leads is attached to the printed circuit board, and FIG. 6 is a plan view showing the assembled state after the sealing process. It is a partial cross-sectional view showing an example of the following. 1... First envelope, 2... Hollow, 3... Second envelope, 4... Metal plate (support plate), 5 ...Glass, 6.
...Reinforcement plate, 7...Glass, 8...Lead, 9...
- Glass, 10... Package part, 11... Circuit element, 12... Gold-silicon eutectic alloy layer, 13... Wire, 14... Heat sink, 15... Lead frame, 16. ...Rim, 17...Guide hole, 18...
- Dummy lead, 19... recess, 20... LSI package, 21... radiation fin, 22... printed circuit board, 30... second envelope, 31... support plate, 32
...Glass. Figure 1 Figure 2
Claims (1)
回路装置であって、前記チップをその内面に固着したメ
タル板と、前記メタル板の外面に載置された複数のフィ
ンを有する放熱体よりなることを特徴とする集積回路装
置。1. An integrated circuit device having an integrated circuit chip hermetically sealed inside, comprising a metal plate with the chip fixed to its inner surface, and a plurality of fins placed on the outer surface of the metal plate. An integrated circuit device characterized by comprising a body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60026201A JPS60258944A (en) | 1985-02-15 | 1985-02-15 | Ic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60026201A JPS60258944A (en) | 1985-02-15 | 1985-02-15 | Ic device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2477377A Division JPS53110371A (en) | 1977-03-09 | 1977-03-09 | Ceramic package type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60258944A true JPS60258944A (en) | 1985-12-20 |
Family
ID=12186855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60026201A Pending JPS60258944A (en) | 1985-02-15 | 1985-02-15 | Ic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60258944A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2398181A (en) * | 2003-02-04 | 2004-08-11 | Transparent Engineering Ltd | Nonplanar lead-frame; mounting magnetic components and a circuit board; lead-frame and heat sink |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS492449U (en) * | 1972-04-08 | 1974-01-10 | ||
| JPS4946943U (en) * | 1972-07-31 | 1974-04-24 | ||
| JPS529378A (en) * | 1975-07-11 | 1977-01-24 | Nippon Telegr & Teleph Corp <Ntt> | Integrated circuit package |
| JPS5917542A (en) * | 1982-07-22 | 1984-01-28 | Canon Inc | Compensation system of correction amount of aperture of camera |
-
1985
- 1985-02-15 JP JP60026201A patent/JPS60258944A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS492449U (en) * | 1972-04-08 | 1974-01-10 | ||
| JPS4946943U (en) * | 1972-07-31 | 1974-04-24 | ||
| JPS529378A (en) * | 1975-07-11 | 1977-01-24 | Nippon Telegr & Teleph Corp <Ntt> | Integrated circuit package |
| JPS5917542A (en) * | 1982-07-22 | 1984-01-28 | Canon Inc | Compensation system of correction amount of aperture of camera |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2398181A (en) * | 2003-02-04 | 2004-08-11 | Transparent Engineering Ltd | Nonplanar lead-frame; mounting magnetic components and a circuit board; lead-frame and heat sink |
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