JPS6120143B2 - - Google Patents
Info
- Publication number
- JPS6120143B2 JPS6120143B2 JP58226839A JP22683983A JPS6120143B2 JP S6120143 B2 JPS6120143 B2 JP S6120143B2 JP 58226839 A JP58226839 A JP 58226839A JP 22683983 A JP22683983 A JP 22683983A JP S6120143 B2 JPS6120143 B2 JP S6120143B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- envelope
- leads
- package
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000008188 pellet Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000007789 sealing Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000005452 bending Methods 0.000 claims 1
- 239000000919 ceramic Substances 0.000 description 21
- 239000011521 glass Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 230000017525 heat dissipation Effects 0.000 description 10
- 238000001465 metallisation Methods 0.000 description 5
- 230000003014 reinforcing effect Effects 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000002844 melting Methods 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910000833 kovar Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000006023 eutectic alloy Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- UGKDIUIOSMUOAW-UHFFFAOYSA-N iron nickel Chemical compound [Fe].[Ni] UGKDIUIOSMUOAW-UHFFFAOYSA-N 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 239000005394 sealing glass Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は高密度、高速ロジツク用セラミツクパ
ツケージ型LSI（大規模集積回路）に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ceramic package type LSI (Large Scale Integrated Circuit) for high-density, high-speed logic.
従来、高密度、高速ロジツク用セラミツクパツ
ケージ型LSI（以下単にLSIパツケージと称す
る。）は積層セラミツクパツケージ構造からな
り、プリント基板（プリント板）等の配線基板に
リードを介して取り付けられる。このLSIパツケ
ージはプリント板側のセラミツク板（セラミツク
基板）からなる外囲器（ベース）内に半導体素子
（ペレツト）を固定するとともに、プリント板か
ら離れる他のセラミツク板からなる外囲器（キヤ
ツプ）の外面に放熱用の金属からなるヒートシン
ク（フイン）が設けられている。 Conventionally, high-density, high-speed logic ceramic package type LSIs (hereinafter simply referred to as LSI packages) have a laminated ceramic package structure, and are attached to a wiring board such as a printed circuit board (printed board) via leads. This LSI package fixes a semiconductor element (pellet) in an envelope (base) made of a ceramic board (ceramic substrate) on the printed board side, and also has an envelope (cap) made of another ceramic board separated from the printed board. A heat sink (fin) made of metal for heat dissipation is provided on the outer surface of the device.
しかし、従来の積層セラミツクパツケージ構造
では次のような欠点がある。 However, the conventional laminated ceramic package structure has the following drawbacks.
(1) 積層セラミツクパツケージ構造は多数枚のセ
ラミツク板を積み重ねたり、各セラミツク板に
スルーホールを設けてこの孔に導電材を充満さ
せ、セラミツク板上下面の配線を電気的に接続
させるなど複雑となることから製造コストが高
い。(1) The laminated ceramic package structure is complicated by stacking many ceramic plates, providing through holes in each ceramic plate, filling the holes with a conductive material, and electrically connecting the wiring on the top and bottom surfaces of the ceramic plates. Therefore, manufacturing costs are high.
(2) 積層セラミツクパツケージ構造はセラミツク
基板に形成するメタライズ層の加工寸法の公差
を±１％以内の値にすることがむずかしい。し
たがつてセラミツク板上にメタライズされて形
成されたリードの内端とペレツトの電極とをワ
イヤで接続するボンデイング作業にあつて、公
差が大きいため自動化が困難となり、ボンデイ
ング加工時間が大きくなる。また、信頼性も悪
くなる。(2) In the case of a laminated ceramic package structure, it is difficult to keep the tolerance of the processing dimensions of the metallized layer formed on the ceramic substrate within ±1%. Therefore, in the bonding process in which the inner end of the lead formed by metallization on the ceramic plate is connected with the electrode of the pellet using a wire, automation is difficult due to the large tolerance, and the bonding process takes a long time. Moreover, reliability also deteriorates.
(3) 配線が導電性ペーストのメタライズによるた
め、抵抗が高くなりやすく、低抵抗にするため
にメタライズ幅を大きくとることからパツケー
ジ全体が大きくなり易い。(3) Since the wiring is made of metallized conductive paste, the resistance tends to be high, and since the width of the metallization is widened in order to achieve low resistance, the overall package tends to become large.
(4) メタライズ配線間隔はスルーホールの孔径と
の関係から、スルーホール経（たとえば一般的
な技術的最小値は0.3mm〓）よりも小さくでき
ない。このためLSIパツケージの小型化が図れ
ない。すなわち、従来ではゲート数が100、リ
ード数が50程度のものが最も大規模なものであ
るが、素子数9000個、ゲート数400、リード数
100程度のLSIが要求される現在にあつては、
従来の積層パツケージ構造で作ると極めて大き
なものとなつてしまい好ましくない。(4) Due to the relationship with the diameter of the through-hole, the metallization wiring spacing cannot be made smaller than the through-hole diameter (for example, the general technical minimum value is 0.3 mm). For this reason, it is not possible to downsize the LSI package. In other words, conventionally, the largest scale is one with about 100 gates and 50 leads;
Nowadays, around 100 LSIs are required.
If made using the conventional laminated package structure, it would be extremely large, which is not desirable.
(5) 放熱板はペレツトを取り付けたベースに直接
固定されず、キヤツプに固定されている。した
がつて、熱の大部分はベース、ベースとキヤツ
プとの接合枠部、キヤツプ、放熱板の順序で伝
わるため、放熱性が低い。また、セラミツク自
体は金属等に較べて熱伝導度が低いという欠点
もある。(5) The heat sink is not directly fixed to the base on which the pellets are attached, but is fixed to the cap. Therefore, most of the heat is transmitted in this order: the base, the joint frame between the base and the cap, the cap, and the heat sink, resulting in poor heat dissipation. Furthermore, ceramic itself also has the disadvantage of having lower thermal conductivity than metals and the like.
本発明はこのような欠点を解消するものであつ
て、その目的は低廉なLSIパツケージを提供する
ことにある。 The present invention is intended to eliminate these drawbacks, and its purpose is to provide an inexpensive LSI package.
また、本発明の他の目的は、自動ワイヤボンデ
イングの可能な構造のLSIパツケージを提供する
ことにある。 Another object of the present invention is to provide an LSI package with a structure that allows automatic wire bonding.
また、本発明の他の目的は、LSIパツケージの
小型化を図ることにある。 Another object of the present invention is to reduce the size of an LSI package.
また、本発明のさらに他の目的は気密性等の信
頼度の高いLSIパツケージを提供することにあ
る。 Still another object of the present invention is to provide an LSI package with high reliability such as airtightness.
また、本発明の他の目的は配線の低抵抗化を図
ることにある。 Another object of the present invention is to reduce the resistance of wiring.
さらに、本発明の他の目的は熱抵抗を可及的に
低くすることによつて放熱性の良好なLSIパツケ
ージを提供することにある。 Furthermore, another object of the present invention is to provide an LSI package with good heat dissipation by lowering the thermal resistance as much as possible.
上記目的を達成するための本発明の一実施例
は、ダミーリードを封止体中に封入した状態でリ
ードと外枠を分離する半導体装置の製造方法とす
るものである。 An embodiment of the present invention to achieve the above object is a method for manufacturing a semiconductor device in which the leads and the outer frame are separated while the dummy leads are sealed in a sealing body.
第１図は本発明のLSIパツケージの一実施例を
示す。同図において１は例えば矩形のセラミツク
板からなる第１外囲器である。この第１外囲器１
はプリント板などからなる配線板（図示せず）に
対面（図では上面がプリント板に対面する。）す
る。そして、その反対面（図中下面）の中央部は
窪み２を有している。３は前記第１外囲器１と同
じ大きさのセラミツク板からなる第２外囲器であ
つて、その中央部は円形又は角形に抜けている。
そして、この円形部又は角形は２段の段付孔とな
つていて、下面の広径部には熱伝導度の良好なモ
リブデン、タングステンなどからなる金属板（支
持板）４がガラス５を介して固定されている。ま
た、金属とガラスは接合強度が弱いことから、補
強板６を用い、この補強板６と第２外囲器３とで
前記支持板４を挾み込むようにしている。すなわ
ち、補強板６は外周は第２外囲器３と同じ形状を
し、内周は第２外囲器３の内径部と同じ大きさに
なつていて、ガラス７で第２外囲器３および支持
板４に接着している。 FIG. 1 shows an embodiment of the LSI package of the present invention. In the figure, reference numeral 1 denotes a first envelope made of, for example, a rectangular ceramic plate. This first envelope 1
faces a wiring board (not shown) made of a printed board or the like (in the figure, the top surface faces the printed board). The center portion of the opposite surface (lower surface in the figure) has a depression 2. Reference numeral 3 denotes a second envelope made of a ceramic plate having the same size as the first envelope 1, and the center portion of the second envelope is cut out in a circular or square shape.
This circular part or square shape has a two-stage stepped hole, and a metal plate (supporting plate) 4 made of molybdenum, tungsten, etc. with good thermal conductivity is inserted through a glass 5 in the wide diameter part of the lower surface. Fixed. Further, since the bonding strength between metal and glass is weak, a reinforcing plate 6 is used, and the supporting plate 4 is sandwiched between the reinforcing plate 6 and the second envelope 3. That is, the reinforcing plate 6 has an outer periphery that has the same shape as the second envelope 3, an inner periphery that has the same size as the inner diameter of the second envelope 3, and a glass 7 that is connected to the second envelope 3. and is adhered to the support plate 4.
また、８は前記第１外囲器１と第２外囲器３と
の間にガラス９を介して挾持固着される複数のリ
ードである。このリード８はコバール、鉄−ニツ
ケル42合金等の薄板をエツチングやプレスによつ
て形成されたものであり、第１外囲器１と第２外
囲器３とからなるパツケージ部１０の内にあつて
は、第２外囲器３の上面に沿つて延びるととも
に、パツケージ部１０の外にあつては２箇所で屈
曲し、その先端部は第１外囲器１の上面とほぼ同
一の平面上あるいは前記上面よりわずかに突出し
た面に沿うように延びている。そして、これらの
リード８の外端部はプリント配線基板（図示せ
ず）の端子部に重なり合うようになつている。 Further, reference numeral 8 denotes a plurality of leads which are sandwiched and fixed between the first envelope 1 and the second envelope 3 with a glass 9 interposed therebetween. This lead 8 is formed by etching or pressing a thin plate of Kovar, iron-nickel 42 alloy, etc., and is placed inside the package part 10 consisting of the first envelope 1 and the second envelope 3. It extends along the top surface of the second envelope 3, and is bent at two places outside the package part 10, with its tip end being on a plane that is substantially the same as the top surface of the first envelope 1. It extends along the upper surface or a surface slightly protruding from the upper surface. The outer ends of these leads 8 are arranged to overlap terminal portions of a printed wiring board (not shown).
また、１１は素子数がたとえば9000個を有する
シリコン板からなるLSI素子（ペレツト）であつ
て、前記支持板４のパツケージ部１０の内面に例
えば金−シリコン共晶合金層１２を介して固定さ
れている。１３は金線あるいはアルミニウム線等
からなるワイヤであつて、超音波ボンデイング方
法や熱圧着方法でペレツトの電極とリード８の内
端を繋いでいる。１４は銅、アルミニウム等の熱
伝導度の良好な金属等からなる柱状のヒートシン
クであり、圧接又は鑞付けによつて前記支持板４
の外面（図中下面）に固定されている。なお、こ
のヒートシンクには第５図に示すように、放熱フ
インを取り付け、放熱性をさらに高めてもよい。 Reference numeral 11 denotes an LSI element (pellet) made of a silicon plate having, for example, 9,000 elements, and is fixed to the inner surface of the package portion 10 of the support plate 4 via, for example, a gold-silicon eutectic alloy layer 12. ing. Reference numeral 13 denotes a wire made of gold wire, aluminum wire, or the like, which connects the electrode of the pellet to the inner end of the lead 8 by ultrasonic bonding or thermocompression bonding. 14 is a columnar heat sink made of a metal with good thermal conductivity such as copper or aluminum, and is attached to the support plate 4 by pressure welding or brazing.
It is fixed to the outer surface (lower surface in the figure). Incidentally, as shown in FIG. 5, heat dissipation fins may be attached to this heat sink to further improve heat dissipation.
つぎに、このようなLSIパツケージの製造工程
について第２図を用いて簡単に説明する。(a)、第
３図で示すようなリードフレーム１５を用意す
る。このリードフレーム１５はシリコンの熱膨張
係数と近似するコバールや42合金等からなる薄い
板、たとえば0.1mmの厚さの板をエツチング技術
や精密プレス技術を用いて形成する。この場合、
各リード８間の距離は板厚とほぼ同じ程度まで狭
く形成できる。また寸法公差は±0.2〜0.3％にす
ることができる。各リード８は矩形枠からなるリ
ム１６の各辺から枠中央に向かつて延びている。
また、矩形枠の四隅は幅広に形成されており、該
部には円形あるいは長孔からなるハンドリングお
よび位置決め用のガイド孔１７が設けられてい
る。また、矩形枠の四隅にはダミーリード１８が
設けられている。このダミーリード１８には凹部
１９が設けられ、外力を加えると簡単に凹部１９
で破断するようになつている。この凹部１９は第
１、第２外囲器１，３の外周縁部上に位置する部
分に設けられている。 Next, the manufacturing process of such an LSI package will be briefly explained using FIG. 2. (a) A lead frame 15 as shown in FIG. 3 is prepared. This lead frame 15 is formed from a thin plate made of Kovar, 42 alloy, or the like, which has a thermal expansion coefficient similar to that of silicon, for example, a plate having a thickness of 0.1 mm, using etching technology or precision pressing technology. in this case,
The distance between each lead 8 can be made as narrow as approximately the thickness of the plate. Further, the dimensional tolerance can be set to ±0.2 to 0.3%. Each lead 8 extends from each side of a rim 16 made of a rectangular frame toward the center of the frame.
Further, the four corners of the rectangular frame are formed wide, and guide holes 17 for handling and positioning, which are circular or elongated holes, are provided in these parts. Furthermore, dummy leads 18 are provided at the four corners of the rectangular frame. This dummy lead 18 is provided with a recess 19, and when an external force is applied, the recess 19 can be easily opened.
It is starting to break. This recess 19 is provided at a portion located on the outer peripheral edge of the first and second envelopes 1 and 3.
(b)、このようなリードフレーム１５の各リード
８の先端のワイヤ取付部に蒸着法あるいはめつき
法によつてアルミニウム被膜あるいは金被膜を形
成する。(c)、ヒートシンク１４を固定した支持板
４を補強板６および高信頼度の低融点フリツトガ
ラスを用いて第２外囲器３に固定する。(d)、ペレ
ツト１１を支持板のペレツトを取り付ける部分に
部分的に形成したAu層を介して支持板４に固定
する。(e)、ペレツトの電極とリードとの間をワイ
ヤボンデイングにより電気的に接続する。(f)、第
１外囲器１を第２外囲器３に低融点ガラスフリツ
トを介して重ね合せ、第４図に示すように、加熱
溶融により一体的に気密封止する。 (b) An aluminum film or a gold film is formed on the wire attachment portion at the tip of each lead 8 of the lead frame 15 by vapor deposition or plating. (c) The support plate 4 to which the heat sink 14 is fixed is fixed to the second envelope 3 using the reinforcing plate 6 and highly reliable low melting point frit glass. (d) The pellet 11 is fixed to the support plate 4 via an Au layer partially formed on the part of the support plate where the pellet is attached. (e) Electrically connect the electrodes of the pellet and the leads by wire bonding. (f) The first envelope 1 is stacked on the second envelope 3 via a low-melting glass frit, and as shown in FIG. 4, the first envelope 1 and the second envelope 3 are integrally hermetically sealed by heating and melting.
(g)、パツケージ部１０から突出するリード８の
表面に半田をめつきする。(h)、リード８のみをリ
ム１６の付け根部分で切断する。この状態では、
各リードは電気的に独立していることから、(i)リ
ードフレームのまま取り扱つて各パツケージの特
性測定を行ない、選別分類する。(j)前記測定の結
果、良品はリードを折り曲げ成形する。(k)リム部
をダミーリード１８の凹部１９から破断させて、
第１図で示すLSIパツケージを得る。 (g) The surface of the lead 8 protruding from the package portion 10 is plated with solder. (h) Cut only the lead 8 at the base of the rim 16. In this state,
Since each lead is electrically independent, (i) the lead frame is handled as is, the characteristics of each package are measured, and the packages are sorted and classified; (j) As a result of the above measurement, if the product is non-defective, the lead will be bent and molded. (k) Breaking the rim portion from the recess 19 of the dummy lead 18,
The LSI package shown in FIG. 1 is obtained.
このようにして製造されたLSIパツケージはつ
ぎのような効果を奏する。 The LSI package manufactured in this manner has the following effects.
(1) 金属板からリードフレームを形成し、このリ
ードフレームを第１・第２外囲器で挾持接着す
るだけであり、従来のように、スルーホール部
等を有するセラミツク板の積層などにくらべ工
数が小さくなるため、製造コストが軽減され
る。(1) A lead frame is formed from a metal plate, and this lead frame is simply sandwiched and bonded between the first and second envelopes. Since the number of man-hours is reduced, manufacturing costs are reduced.
(2) リードはリードフレームの状態で第１・第２
外囲器で挾持接着することから、各リードの間
隔は加工時の寸法が保持された状態で第１・第
２外囲器に固定される。このため、ワイヤボン
デイングにあつては、自動ボンダーを用いても
正確なワイヤボンデイングができる。したがつ
て、ワイヤボンデイングの作業性が著しく向上
する。(2) Connect the first and second leads in the lead frame state.
Since the leads are sandwiched and bonded by the envelope, the intervals between the leads are fixed to the first and second envelopes while maintaining the dimensions at the time of processing. Therefore, in wire bonding, accurate wire bonding can be performed even if an automatic bonder is used. Therefore, the workability of wire bonding is significantly improved.
(3) リードは従来のメタライズに代わり、コバー
ル、鉄−ニツケル42合金等の金属で形作られる
ため、抵抗が低くなる。(3) Leads are formed from metals such as Kovar and iron-nickel 42 alloy instead of conventional metallization, resulting in lower resistance.
(4) 金属板からリードフレームを作るため、各リ
ード間の距離は0.1mm程度にまで狭くすること
ができる。このため、従来の積層セラミツクパ
ツケージ構造に較べて製品の小型化を図ること
ができる。(4) Since the lead frame is made from a metal plate, the distance between each lead can be reduced to about 0.1mm. Therefore, the product can be made more compact than the conventional laminated ceramic package structure.
(5) 放熱板（ヒートシンク）は回路素子を取付け
た第２外囲器側に固定されている。したがつ
て、伝熱抵抗が軽減され、放熱効果が向上す
る。(5) A heat sink is fixed to the second envelope side to which the circuit elements are attached. Therefore, heat transfer resistance is reduced and heat dissipation effect is improved.
(6) 第１・第２外囲器、支持板各部の接着は低融
点ガラスシール方式としているため、気密性等
の信頼度が高い。(6) Each part of the first and second envelopes and support plate is bonded using a low melting point glass sealing method, so the reliability of airtightness etc. is high.
(7) 第１・第２外囲器はアルミナからなる絶縁物
で形成されているため、容量を低減できる。(7) Since the first and second envelopes are made of an insulator made of alumina, the capacitance can be reduced.
(8) 従来の積層セラミツクパツケージ構造に較べ
て材質組合せを単純化できる。また、この一例
として、第２外囲器への支持板の取り付けを銀
鑞等で行なうと、セラミツクにメタライズ、メ
ツキ等が必要となるが、封止用ガラスで取付け
ることにより工程を簡略化できる。(8) Material combinations can be simplified compared to conventional laminated ceramic package structures. Also, as an example of this, if the support plate is attached to the second envelope using silver solder, etc., metallization, plating, etc. will be required on the ceramic, but the process can be simplified by attaching it with sealing glass. .
(9) リードはプリント基板（プリント配線基板）
に重ね合せる構成となつている。したがつて、
プリント基板においては、リードを挿し込む孔
を設けなくともよいことから、プリント基板の
配線パターンの微細化を図ることができ、実装
密度の向上を図ることができる。また、各リー
ドはプリント基板に半田等を介して固定される
が、この際、パツケージ部に外力が加わつて
も、リードの屈曲部が弾力的に作用するため、
リードがプリント基板から剥離することがな
い。(9) Leads are printed circuit boards (printed wiring boards)
The structure is such that they are superimposed on each other. Therefore,
Since it is not necessary to provide a hole for inserting a lead in a printed circuit board, the wiring pattern of the printed circuit board can be made finer, and the packaging density can be improved. In addition, each lead is fixed to the printed circuit board via solder, etc., but at this time, even if an external force is applied to the package part, the bent part of the lead acts elastically.
The leads will not peel off from the printed circuit board.
第５図にはダミーリード１８によりリム１６に
支持されたLSIパツケージ２０をプリント基板
（プリント配線基板）２２に取付けた。LSIパツ
ケージ２０のヒートシンク１４には放熱フイン２
１が取り付けられている。LSIパツケージはダミ
ーリード１８によりリム１６に支持された状態で
市販することもできる。その場合、市販された
LSIパツケージは使用者側でプリント基板に取付
けることになるが取付けにあたつては、前記リー
ドフレーム１５のリム１６の隅部のガイド孔１７
を利用してプリント基板２２に位置決めを行な
い、リード８を半田でプリント基板２２の導電層
に固定し、その後、リム１６を把んでプリント基
板２２から遠ざかるように引き離すことにより、
ダミーリード１８の凹部１９を破断し、パツケー
ジをリム１６から分離することができる。このよ
うに、ダミーリード１８によりリム１６に支持接
続された状態でLSIパツケージを販売しても前記
ガイド孔１７を利用してプリント基板への取り付
けを正確に行うことができ、また凹部１９の部分
から簡単にパツケージをリム１６から分離するこ
とができる。 In FIG. 5, an LSI package 20 supported on a rim 16 by dummy leads 18 is attached to a printed circuit board (printed wiring board) 22. The heat sink 14 of the LSI package 20 has a heat dissipation fin 2.
1 is attached. The LSI package can also be sold commercially in a state where it is supported on the rim 16 by dummy leads 18. In that case, commercially available
The LSI package will be attached to the printed circuit board by the user, and when attaching it, the guide hole 17 in the corner of the rim 16 of the lead frame 15 must be installed.
By positioning the lead 8 on the printed circuit board 22 using solder, fixing the lead 8 to the conductive layer of the printed circuit board 22 with solder, and then grasping the rim 16 and pulling it away from the printed circuit board 22,
The recess 19 of the dummy lead 18 can be broken to separate the package from the rim 16. In this way, even if the LSI package is sold in a state where it is supported and connected to the rim 16 by the dummy leads 18, it can be accurately attached to the printed circuit board using the guide hole 17, and the part of the recess 19 can be The package can be easily separated from the rim 16.
なお、本発明は前記実施例に限定されない。た
とえば、前記第２外囲器中央の支持板とヒートシ
ンク等の放熱部を例えばMo、酸化ベリリウム等
の同一材料で一体的に形成してもよい。また、第
２外囲器を金属板で作り、第１外囲器と接する周
縁部に絶縁物を被着させる構造でもよい。また、
第６図に示すように、第２外囲器３０への支持板
３１の取り付けは補強板を用いることなく、ガラ
ス３２で固定するようにしてもよい。この際、支
持板３１の周縁を被うようにガラスを附着させ
る。 Note that the present invention is not limited to the above embodiments. For example, the support plate at the center of the second envelope and a heat sink such as a heat sink may be integrally formed of the same material, such as Mo or beryllium oxide. Alternatively, the second envelope may be made of a metal plate, and an insulating material may be applied to the peripheral edge in contact with the first envelope. Also,
As shown in FIG. 6, the support plate 31 may be attached to the second envelope 30 by fixing it with a glass 32 without using a reinforcing plate. At this time, glass is attached so as to cover the peripheral edge of the support plate 31.
以上のように、本発明のLSIパツケージ方法に
よれば、リードを金属を用いて形成することか
ら、従来のようにメタライズしたものよりも電気
抵抗が低くなる。したがつて、リードの幅を狭く
できる。またリード間隔を狭くすることができる
ので、LSIパツケージの小型化を図ることができ
る。 As described above, according to the LSI packaging method of the present invention, since the leads are formed using metal, the electrical resistance is lower than that of conventional metallized leads. Therefore, the width of the lead can be made narrower. Furthermore, since the lead spacing can be narrowed, the LSI package can be made smaller.
また、ペレツトを固定した外囲器側に、しかも
熱伝導度の良好な板に放熱体を固定する構造とす
ることによつて、従来の此種LSIパツケージに較
べて極めて放熱性が良好となる。 In addition, by fixing the heat dissipation body on the side of the envelope to which the pellets are fixed, and on a plate with good thermal conductivity, the heat dissipation performance is extremely good compared to conventional LSI packages of this type. .
また、本発明によれば、金属板からリードフレ
ームを作るため、各部の位置関係が正しく保たれ
る。また、リードフレームに設けたガイド孔等を
用いることにより、各種の組立、取り付けの自動
化を図ることができる。 Further, according to the present invention, since the lead frame is made from a metal plate, the positional relationship of each part can be maintained correctly. Further, by using guide holes etc. provided in the lead frame, various assemblies and attachments can be automated.
また、本願発明によれば、パツケージを４方向
から支持した状態でリードの折り曲げ成形をする
ため、パツケージを回転させるような力が加わつ
ても、その回転を防止することができる。 Further, according to the present invention, since the leads are bent and formed while the package is supported from four directions, even if a force that would cause the package to rotate is applied, the rotation can be prevented.
また、ガラス封止構造とすることによつて、気
密性が優れ、信頼度の高いLSIパツケージを提供
することができる。 Further, by using a glass-sealed structure, it is possible to provide an LSI package with excellent airtightness and high reliability.
さらに、この発明によれば、各部の構造が単純
化できるため、材料軽減、組立の容易性等の理由
から、安価なLSIパツケージを提供することがで
きるなど多くの効果を奏する。 Further, according to the present invention, since the structure of each part can be simplified, it is possible to provide an inexpensive LSI package due to the reduction in materials, ease of assembly, etc., and many other effects can be achieved.
第１図は本発明によるセラミツクパツケージ型
半導体装置の一実施例による断面図、第２図は本
発明の製造工程を示す工程図、第３図は使用する
リードフレームの平面図、第４図は封止工程後の
組立状態を示す平面図、第５図はダミーリードに
よりリム１６に支持接続されたLSIパツケージを
プリント基板に取り付けた状態を示す断面図、第
６図は他のパツケージ構造を示す一部断面図であ
る。
１……第１外囲器、２……窪み、３……第２外
囲器、４……金属板（支持板）、５……ガラス、
６……補強板、７……ガラス、８……リード、９
……ガラス、１０……パツケージ部、１１……回
路素子、１２……金−シリコン共晶合金層、１３
……ワイヤ、１４……ヒートシンク、１５……リ
ードフレーム、１６……リム、１７……ガイド
孔、１８……ダミーリード、１９……凹部、２０
……LSIパツケージ、２１……放熱フイン、２２
……プリント基板、３０……第２外囲器、３１…
…支持板、３２……ガラス。
FIG. 1 is a cross-sectional view of one embodiment of the ceramic package type semiconductor device according to the present invention, FIG. 2 is a process diagram showing the manufacturing process of the present invention, FIG. 3 is a plan view of the lead frame used, and FIG. A plan view showing the assembled state after the sealing process, FIG. 5 is a cross-sectional view showing the state in which the LSI package supported and connected to the rim 16 by dummy leads is attached to the printed circuit board, and FIG. 6 shows another package structure. It is a partially sectional view. 1... First envelope, 2... Hollow, 3... Second envelope, 4... Metal plate (support plate), 5... Glass,
6... Reinforcement plate, 7... Glass, 8... Lead, 9
... Glass, 10 ... Package part, 11 ... Circuit element, 12 ... Gold-silicon eutectic alloy layer, 13
... wire, 14 ... heat sink, 15 ... lead frame, 16 ... rim, 17 ... guide hole, 18 ... dummy lead, 19 ... recess, 20
... LSI package, 21 ... Heat dissipation fin, 22
...Printed circuit board, 30...Second envelope, 31...
...Support plate, 32...Glass.
Claims (1)
中心方向に延びる複数のリードからなる４つの
リード群と、前記枠体に接続され各リード群の
間に位置する４本のダミーリードとを有するリ
ードフレームを準備する工程 (b) 前記枠体の中心部分にペレツトを載置する工
程 (c) 前記ペレツトの電極と前記リードとを電気的
に接続する工程 (d) 少なくとも前記ペレツト及び前記複数のリー
ドの自由端を封止する工程 (e) 前記枠体と前記複数のリードとの間を切断す
る工程 (f) 前記複数のリードを折り曲げ成形する工程 (g) 前記ダミーリードと前記枠体とを切断する工
程 を有することを特徴とする半導体装置の製造方
法。[Claims] 1 (a) Four lead groups consisting of a plurality of leads extending from each side of a rectangular frame toward the center of the rectangular frame, and a wire connected to the frame between each lead group. Step (b) of preparing a lead frame having four dummy leads located in the frame body; Step (c) of placing a pellet in the center of the frame; and (c) electrically connecting the electrode of the pellet and the lead. (d) sealing at least the free ends of the pellet and the plurality of leads; (e) cutting between the frame and the plurality of leads; (f) bending and forming the plurality of leads. (g) A method for manufacturing a semiconductor device, comprising the step of cutting the dummy lead and the frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58226839A JPS59139650A (en) | 1983-12-02 | 1983-12-02 | Sealing method of electronic element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58226839A JPS59139650A (en) | 1983-12-02 | 1983-12-02 | Sealing method of electronic element |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2477377A Division JPS53110371A (en) | 1977-03-09 | 1977-03-09 | Ceramic package type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59139650A JPS59139650A (en) | 1984-08-10 |
| JPS6120143B2 true JPS6120143B2 (en) | 1986-05-21 |
Family
ID=16851373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58226839A Granted JPS59139650A (en) | 1983-12-02 | 1983-12-02 | Sealing method of electronic element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59139650A (en) |
-
1983
- 1983-12-02 JP JP58226839A patent/JPS59139650A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59139650A (en) | 1984-08-10 |
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