JPS59138359A - Multilayer element - Google Patents

Multilayer element

Info

Publication number
JPS59138359A
JPS59138359A JP59006389A JP638984A JPS59138359A JP S59138359 A JPS59138359 A JP S59138359A JP 59006389 A JP59006389 A JP 59006389A JP 638984 A JP638984 A JP 638984A JP S59138359 A JPS59138359 A JP S59138359A
Authority
JP
Japan
Prior art keywords
capacitor
multilayer
resistor
substrate
trimming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59006389A
Other languages
Japanese (ja)
Inventor
ヘルマン・ビルンブライアー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BBC Brown Boveri France SA
Original Assignee
BBC Brown Boveri France SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BBC Brown Boveri France SA filed Critical BBC Brown Boveri France SA
Publication of JPS59138359A publication Critical patent/JPS59138359A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0317—Thin film conductor layer; Thin film passive component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09763—Printed component having superposed conductors, but integrated in one circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10045—Mounted network component having plural terminals
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17—Post-manufacturing processes
    • H05K2203/171—Tuning, e.g. by trimming of printed components or high frequency circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17—Post-manufacturing processes
    • H05K2203/175—Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 この発明は特許請求の範囲第１項のプレアンブル部に記
載の多層素子に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer device according to the preamble of claim 1.

このような多層素子は、例えば、随ｇｃｈｗｉｔｚｅｒ
＋Ｌｕｎｚｅによる「半導体技術（Ｈａｌｂｌｅｉｔｅ
ｒｅｌｅｃｔｒｏｎｉｋ）ＪＨｕ　ｔｈ　ｉ　ｇ　　出
版（ハイデルベルグ）、１９８０年の４３３頁〜４３７
頁に記載されている。素膜技術または厚膜技術において
、例えば、抵抗、コンデンサ、ダイオード、トランジス
タが製造される。その際、各素子は、一般に、基板の上
に並列して設けられる。集積度を昼めるために例えばコ
ンデンサの上に抵抗を設ける等のように、多数の素子を
上下に重ねて設けることも勿論可能である。上に設けた
素子を調整（トリミング）する際、例えば、上に設けた
抵抗をレーザを用いてトリミングする際、その下に設け
た素子を損傷するという危険がある。Such a multilayer device can be used, for example, in
“Semiconductor technology (Halbleite)” by +Lunze
433-437, J Huth i g Publishing (Heidelberg), 1980.
It is written on the page. In bare film or thick film technology, for example, resistors, capacitors, diodes, transistors are manufactured. In this case, each element is generally provided in parallel on the substrate. Of course, it is also possible to provide a large number of elements one above the other in order to reduce the degree of integration, for example by providing a resistor on top of a capacitor. When trimming an overlying element, for example when trimming an overlying resistor using a laser, there is a risk of damaging the underlying element.

この発明の目的は他の素子を損傷することなしに多層構
造の各素子を調整することが可能な冒頭で述べたような
多層素子を提供することである。The object of the invention is to provide a multilayer element as mentioned at the outset, in which each element of the multilayer structure can be adjusted without damaging other elements.

この目的は特許請求の範囲第１項の特徴部によって解決
される。This object is solved by the features of patent claim 1.

この発明によシ得られる効果は、特に、重なシ合ってい
る領域以外で簡単な方法で、かつ、多層構造の他の素子
を破壊または損傷す勺ことなく各素子の調整が可能であ
るということである。多層素子は高集積化が可能である
利点を有する。The advantage obtained by the present invention is that each element can be adjusted in a simple manner in areas other than the overlapping areas, and without destroying or damaging other elements of the multilayer structure. That's what it means. Multilayer devices have the advantage of being highly integrated.

以下、図面を参照してこの発明による多層素子の一実施
例を説明する。Hereinafter, one embodiment of a multilayer element according to the present invention will be described with reference to the drawings.

第１図にこの発明による多層素子の一実施例の平面図を
示す。基板（例えばＡ／＝２０．　）、　Ｚの上に平板
形状のコンデンサ２が薄膜技術によ多形成される。これ
は、マスクによシ真空中で成型される。接触面を有する
コンデンサ２の両端子は参照数字３．４によって示され
る。FIG. 1 shows a plan view of an embodiment of a multilayer element according to the present invention. A flat plate-shaped capacitor 2 is formed on a substrate (for example, A/=20.) by thin film technology. This is molded in vacuum using a mask. Both terminals of the capacitor 2 with contact surfaces are indicated by the reference numeral 3.4.

コンデンサ２の上に蛇行したパターンを有する抵抗５が
形成される。接触面を有する抵抗５０両端子は参照数字
６．７で示される。抵抗５のトリミングのためにコンデ
ンサ２の横の近くに多くのトリミング用アーム８が基板
１の上に、直に、蒸気で成型される。A resistor 5 having a serpentine pattern is formed on top of the capacitor 2 . The resistor 50 terminals with contact surfaces are designated by the reference numeral 6.7. A number of trimming arms 8 are steam molded directly onto the substrate 1 near the sides of the capacitor 2 for trimming the resistor 5 .

抵抗５のトリミングの際には、１つまたは多数のトリミ
ング用アーム８がレーザ光を用いて切断され、抵抗値を
所望値に設定する。レーデ光を用いることによシ、コン
デンサ２　’ｆｒ’ｆ１４ｆｌｉ−ｆること々く、対応
するトリミング用アーム８のみを破壊することができる
。When trimming the resistor 5, one or more trimming arms 8 are cut using a laser beam to set the resistance value to a desired value. By using the radar light, it is possible to destroy the capacitors 2'fr'f14fli-f and only the corresponding trimming arm 8.

第２図に第１図に示した多層素子の断面図を示す。第２
図は、基板１の上に蒸着されたコンデンサ２の構成を詳
細に示す。コンデンサ２は、金属基板２ａ、誘電体から
なる絶縁層２ｂ、金属デツキ２ｃと、コンデンサ２と、
コンデンサ２上に蒸着された抵抗５とを分離するための
外側絶縁層２ｄからなる。FIG. 2 shows a cross-sectional view of the multilayer element shown in FIG. 1. Second
The figure shows in detail the construction of a capacitor 2 deposited on a substrate 1. The capacitor 2 includes a metal substrate 2a, an insulating layer 2b made of a dielectric, a metal deck 2c, and the capacitor 2.
It consists of an outer insulating layer 2d for separating the resistor 5 deposited on the capacitor 2.

コンデンサ２と抵抗５からなる上述した構造の代わシに
トランジスタと抵抗、ダイオードと抵抗、トランジスタ
とコンデンサ等の構造においても破壊を生じないトリミ
ングが可能である。Instead of the above-described structure consisting of the capacitor 2 and resistor 5, trimming without causing damage is also possible in structures such as a transistor and a resistor, a diode and a resistor, a transistor and a capacitor, and the like.

トリミングは抵抗のみに限らずコンデンサについても上
述した方法によシ行なえる。Trimming can be performed not only on resistors but also on capacitors by the method described above.

重ね合わせる緊子数は２つに限らず３つまたはそれ９上
でも構わない。その際、少なくとも１つの素子の一部分
は他の素子の上に重ねず基板の上に直に形成する必要が
ある。The number of strings to be overlapped is not limited to two, but may be three or nine. In this case, a portion of at least one element needs to be formed directly on the substrate without overlapping other elements.

この発明による多層素子は、実施例として説明した薄膜
技術以外にも、厚膜技術やノ・イブリット技術によって
も実現可能である。The multilayer device according to the present invention can be realized not only by the thin film technology described in the embodiments but also by thick film technology and no-brit technology.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明による多層素子の一実施例の平面図、
第２図は第１図の断面図である。 １・・・基板、２・・・コンデンサ、２ａ・・・金属基
板２ｂ・・・絶縁層、２ｃ・・・金属デツキ、２ｄ・・
・外側絶縁層、５・・・抵抗、８・・・トリミング用ア
ーム。 出願人代理人　　弁理士　鈴　江　武　彦Ｆ　ｉ　ｇ、
１FIG. 1 is a plan view of an embodiment of a multilayer element according to the present invention;
FIG. 2 is a sectional view of FIG. 1. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Capacitor, 2a...Metal substrate 2b...Insulating layer, 2c...Metal deck, 2d...
-Outer insulating layer, 5...resistance, 8...trimming arm. Applicant's agent Patent attorney Takehiko Suzue,
1

Claims (2)

【特許請求の範囲】[Claims] （１）薄膜技術、厚膜技術またはハイブリッド技術によ
り抵抗、コンデンサ、ダイオード、トランジスタ等の素
子を基板上に多数形成してなる多層素子において、多数
の各素子＜２．５）を形成する際に、少なくとも１つの
素子（５）の一部分（８）を他の素子（２）と重ねずに
基板（１）の上に形成することを特徴とする多層素子。(1) In a multilayer device formed by forming a large number of elements such as resistors, capacitors, diodes, transistors, etc. on a substrate using thin film technology, thick film technology, or hybrid technology, when forming a large number of each element <2.5) , a multilayer element characterized in that a portion (8) of at least one element (5) is formed on a substrate (1) without overlapping with other elements (2). （２）　　抵抗（５）　ト、コンデンサ（２）の形成の
際に抵抗値を動整するためのトリミング用了−ム（８）
をコンデンサ（２）の近くの基板（１）の上に、直に、
形成することを特徴とする特許請求の範囲第１項に記載
の多層素子。(2) Resistor (5) Trimming end (8) for adjusting the resistance value when forming the capacitor (2)
directly on the board (1) near the capacitor (2),
A multilayer element according to claim 1, characterized in that the multilayer element is formed.
JP59006389A 1983-01-20 1984-01-19 Multilayer element Pending JPS59138359A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19833301673 DE3301673A1 (en) 1983-01-20 1983-01-20 ELECTRICAL OR ELECTRONIC MULTILAYER COMPONENT

Publications (1)

Publication Number Publication Date
JPS59138359A true JPS59138359A (en) 1984-08-08

Family

ID=6188658

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59006389A Pending JPS59138359A (en) 1983-01-20 1984-01-19 Multilayer element

Country Status (4)

Country Link
JP (1) JPS59138359A (en)
DE (1) DE3301673A1 (en)
FR (1) FR2539915A1 (en)
GB (1) GB2133933B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8413323B2 (en) 2003-03-11 2013-04-09 Adc Gmbh Method for high-frequency tuning an electrical device
CN107734848A (en) * 2017-11-16 2018-02-23 珠海市魅族科技有限公司 Printed circuit board encapsulating structure, preparation method, pcb board and terminal

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2231728A (en) * 1989-05-16 1990-11-21 Lucas Ind Plc Trimming a variable resistor
DE4031289A1 (en) * 1990-10-04 1992-04-09 Telefunken Electronic Gmbh Oscillator with amplifier, and feedback elements - has flat capacitor as frequency determining and equalising element
DE4304437A1 (en) * 1993-02-13 1994-08-18 Ego Elektro Blanc & Fischer Integrated circuit, in particular for contact switches, and method for producing an integrated circuit
WO1996006459A1 (en) * 1994-08-25 1996-02-29 National Semiconductor Corporation Component stacking in multi-chip semiconductor packages
RU2190284C2 (en) 1998-07-07 2002-09-27 Закрытое акционерное общество "Техно-ТМ" Two-sided electronic device
SE516152C2 (en) 1999-03-17 2001-11-26 Ericsson Telefon Ab L M Apparatus for allowing trimming on a substrate and method for making a substrate for trimming
US6188295B1 (en) * 1999-04-13 2001-02-13 Delta Electronics, Inc. Frequency adjustments by patterning micro-strips to form serially connected capacitors or inductor-capacitor (LC) Circuit
DE10004649A1 (en) * 2000-02-03 2001-08-09 Infineon Technologies Ag Tuning method for signal delays on bus systems or networks between quick memory modules, involves selectively separating strip conductor run from certain capacitive load structures of printed circuit board
US8202128B2 (en) 2008-11-25 2012-06-19 Adc Gmbh Telecommunications jack with adjustable crosstalk compensation

Family Cites Families (9)

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Publication number Priority date Publication date Assignee Title
US3268773A (en) * 1963-11-21 1966-08-23 Union Carbide Corp Laminate of alternate conductive and dielectric layers
DE2222546C3 (en) * 1972-05-08 1979-10-31 Siemens Ag, 1000 Berlin Und 8000 Muenchen Electrical RC component
US3988824A (en) * 1972-05-22 1976-11-02 Hewlett-Packard Company Method for manufacturing thin film circuits
DE2247279A1 (en) * 1972-09-27 1974-04-04 Siemens Ag PROCEDURES FOR CONTACTING AND / OR WIRING ELECTRICAL COMPONENTS
CH589996A5 (en) * 1974-08-30 1977-07-29 Ebauches Sa
DE7602001U1 (en) * 1976-01-26 1978-05-24 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt COMPARABLE RESISTANCE
DE2622324C3 (en) * 1976-05-19 1980-10-02 Siemens Ag, 1000 Berlin Und 8000 Muenchen Process for the production of a precisely balanced electrical network
US4301439A (en) * 1978-12-26 1981-11-17 Electro Materials Corp. Of America Film type resistor and method of producing same
DE2903025C2 (en) * 1979-01-26 1983-05-05 Siemens AG, 1000 Berlin und 8000 München Rc network

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8413323B2 (en) 2003-03-11 2013-04-09 Adc Gmbh Method for high-frequency tuning an electrical device
CN107734848A (en) * 2017-11-16 2018-02-23 珠海市魅族科技有限公司 Printed circuit board encapsulating structure, preparation method, pcb board and terminal
CN107734848B (en) * 2017-11-16 2020-03-13 珠海市魅族科技有限公司 Printed circuit board packaging structure, manufacturing method, PCB and terminal

Also Published As

Publication number Publication date
GB2133933A (en) 1984-08-01
FR2539915B3 (en) 1985-05-17
FR2539915A1 (en) 1984-07-27
DE3301673A1 (en) 1984-07-26
GB2133933B (en) 1987-01-28
GB8400678D0 (en) 1984-02-15

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