JPS59136963A - 記憶装置の多層実装構造 - Google Patents

記憶装置の多層実装構造

Info

Publication number
JPS59136963A
JPS59136963A JP58011047A JP1104783A JPS59136963A JP S59136963 A JPS59136963 A JP S59136963A JP 58011047 A JP58011047 A JP 58011047A JP 1104783 A JP1104783 A JP 1104783A JP S59136963 A JPS59136963 A JP S59136963A
Authority
JP
Japan
Prior art keywords
substrate
mounting structure
multilayer mounting
memory storage
present
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58011047A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0481332B2 (enExample
Inventor
Hiroshi Yoshino
博 吉野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP58011047A priority Critical patent/JPS59136963A/ja
Publication of JPS59136963A publication Critical patent/JPS59136963A/ja
Publication of JPH0481332B2 publication Critical patent/JPH0481332B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Credit Cards Or The Like (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP58011047A 1983-01-25 1983-01-25 記憶装置の多層実装構造 Granted JPS59136963A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58011047A JPS59136963A (ja) 1983-01-25 1983-01-25 記憶装置の多層実装構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58011047A JPS59136963A (ja) 1983-01-25 1983-01-25 記憶装置の多層実装構造

Publications (2)

Publication Number Publication Date
JPS59136963A true JPS59136963A (ja) 1984-08-06
JPH0481332B2 JPH0481332B2 (enExample) 1992-12-22

Family

ID=11767115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58011047A Granted JPS59136963A (ja) 1983-01-25 1983-01-25 記憶装置の多層実装構造

Country Status (1)

Country Link
JP (1) JPS59136963A (enExample)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996583A (en) * 1989-02-15 1991-02-26 Matsushita Electric Industrial Co., Ltd. Stack type semiconductor package
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices
US5191404A (en) * 1989-12-20 1993-03-02 Digital Equipment Corporation High density memory array packaging
US5198888A (en) * 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
US5587341A (en) * 1987-06-24 1996-12-24 Hitachi, Ltd. Process for manufacturing a stacked integrated circuit package
US5633530A (en) * 1995-10-24 1997-05-27 United Microelectronics Corporation Multichip module having a multi-level configuration
JP2002360132A (ja) * 2001-06-07 2002-12-17 Shimano Inc 釣 竿
US6570249B1 (en) * 2001-12-24 2003-05-27 Siliconware Precision Industries Co., Ltd. Semiconductor package
US7935572B2 (en) 2002-09-17 2011-05-03 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US8143100B2 (en) * 2002-09-17 2012-03-27 Chippac, Inc. Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929974A (enExample) * 1972-07-19 1974-03-16
JPS5141864A (ja) * 1974-10-08 1976-04-08 Hitachi Ltd Denshikairosochi
JPS55165661A (en) * 1979-06-12 1980-12-24 Fujitsu Ltd Semiconductor device
JPS5688341A (en) * 1979-12-21 1981-07-17 Hitachi Ltd Laminated semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929974A (enExample) * 1972-07-19 1974-03-16
JPS5141864A (ja) * 1974-10-08 1976-04-08 Hitachi Ltd Denshikairosochi
JPS55165661A (en) * 1979-06-12 1980-12-24 Fujitsu Ltd Semiconductor device
JPS5688341A (en) * 1979-12-21 1981-07-17 Hitachi Ltd Laminated semiconductor device

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521993B2 (en) 1987-06-24 2003-02-18 Hitachi, Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US6424030B2 (en) 1987-06-24 2002-07-23 Hitachi, Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US6693346B2 (en) * 1987-06-24 2004-02-17 Hitachi, Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US6262488B1 (en) 1987-06-24 2001-07-17 Hitachi Ltd. Semiconductor memory module having double-sided memory chip layout
US5910685A (en) * 1987-06-24 1999-06-08 Hitachi Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US5587341A (en) * 1987-06-24 1996-12-24 Hitachi, Ltd. Process for manufacturing a stacked integrated circuit package
US5708298A (en) * 1987-06-24 1998-01-13 Hitachi Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices
US5334875A (en) * 1987-12-28 1994-08-02 Hitachi, Ltd. Stacked semiconductor memory device and semiconductor memory module containing the same
US5198888A (en) * 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
US4996583A (en) * 1989-02-15 1991-02-26 Matsushita Electric Industrial Co., Ltd. Stack type semiconductor package
US5191404A (en) * 1989-12-20 1993-03-02 Digital Equipment Corporation High density memory array packaging
US5633530A (en) * 1995-10-24 1997-05-27 United Microelectronics Corporation Multichip module having a multi-level configuration
JP2002360132A (ja) * 2001-06-07 2002-12-17 Shimano Inc 釣 竿
US6570249B1 (en) * 2001-12-24 2003-05-27 Siliconware Precision Industries Co., Ltd. Semiconductor package
US6689636B2 (en) 2001-12-24 2004-02-10 Siliconware Precision Industries Co., Ltd. Semiconductor device and fabrication method of the same
US7935572B2 (en) 2002-09-17 2011-05-03 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US8143100B2 (en) * 2002-09-17 2012-03-27 Chippac, Inc. Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages

Also Published As

Publication number Publication date
JPH0481332B2 (enExample) 1992-12-22

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