JPS59136963A - Multilayer mounting structure of memory storage - Google Patents

Multilayer mounting structure of memory storage

Info

Publication number
JPS59136963A
JPS59136963A JP1104783A JP1104783A JPS59136963A JP S59136963 A JPS59136963 A JP S59136963A JP 1104783 A JP1104783 A JP 1104783A JP 1104783 A JP1104783 A JP 1104783A JP S59136963 A JPS59136963 A JP S59136963A
Authority
JP
Japan
Prior art keywords
substrate
substrates
memory
memory storage
mounting structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1104783A
Other languages
Japanese (ja)
Other versions
JPH0481332B2 (en
Inventor
Hiroshi Yoshino
博 吉野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP1104783A priority Critical patent/JPS59136963A/en
Publication of JPS59136963A publication Critical patent/JPS59136963A/en
Publication of JPH0481332B2 publication Critical patent/JPH0481332B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Credit Cards Or The Like (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To realize the multilayer mounting structure of a memory storage, and to increase mounting density by arranging the memory storage in three dimensions by superposing a plurality of second substrates, mounting them on a first substrate and connecting a common projecting electrode to a conducting path in the first substrate. CONSTITUTION:Semiconductor elements 3 for memory are fixed to fixing pads 5 in second substrates 11, and connected electrically to the noses of leads 6 extended from projecting electrodes 4 by bonding wires. The semiconductor elements 3 for memory are surrounded by resin frame bodies 7 with fixed height, and a sealing resin 8 such as epoxy resin is injected to seal the semiconductor elements. Each projecting electrode 4...4 in the second substrates 11 is soldered with a conducting path 2 extended from a bus line on a first substrate 1, and the second substrates 11 are supported and fixed and connected electrically. Second substrates 11 are arranged superposed on the second substrates, and their projecting electrodes 4 are superposed to realize multilayer mounting.

Description

【発明の詳細な説明】 （イ）産業上の利用分野 本発明は記憶装置の多層実装構造に関する。特に共通基
板に組込んだ記憶装置の多層実装構造に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a multilayer mounting structure of a storage device. In particular, the present invention relates to a multilayer mounting structure of a memory device built into a common substrate.

（ロ）従来技術 従来記憶装置は一枚の基板に記憶用半導体素子を平面的
に配列して実装していた。この構造では共通のパスライ
ンから多層配線により導電路を延在させ、この導電路に
個別の記憶用半導体素子を実装していた。(B) Prior Art In a conventional memory device, memory semiconductor elements are arranged and mounted in a two-dimensional array on a single substrate. In this structure, conductive paths are extended from a common path line by multilayer wiring, and individual memory semiconductor elements are mounted on these conductive paths.

しかしながら押上の実装方法では平面的配置では実装密
度が向上されず、パスライン等の引き回し等による実装
面積の減少を伴う。However, in the push-up mounting method, the mounting density cannot be improved in a planar arrangement, and the mounting area is reduced due to routing of pass lines and the like.

（ハ）発明の目的 本発明は押上した欠点に鑑みてなされ、従来の欠点を完
全に除去した記憶装置の多層実装構造を提供するもので
ある。(c) Object of the Invention The present invention has been made in view of the disadvantages that have arisen, and it is an object of the present invention to provide a multilayer mounting structure for a storage device that completely eliminates the conventional disadvantages.

に）発明の構成 本発明に依る記憶装置の多層実装構造は第１図に示す如
く、所望のパターンの導電路を有する第１の基板（１）
と、記憶用半導体素子（３）を組み込み共通の突出電極
（４）を設けた第２の基板Ｑｌ）とを具備し、第２の基
板０１）を複数個重畳して第１の基板（１）上に実装し
、共通の突出電極（４）を第１の基板（１）の導電路（
２）に接続する様に構成される。B) Structure of the Invention As shown in FIG. 1, the multilayer mounting structure of a storage device according to the present invention includes a first substrate (1) having a desired pattern of conductive paths.
and a second substrate Ql) in which a memory semiconductor element (3) is incorporated and a common protruding electrode (4) is provided, and a plurality of second substrates 01) are superimposed to form a first substrate (Ql). ), and the common protruding electrode (4) is mounted on the conductive path (
2).

（ホ）実施例 第１図および第２図を参照して本発明の一実施例を詳述
する。第１および第２の基板（１）Ｑ］）はエポキシ樹
脂ガラス板等で形成される。第１カ基板（１）の片面に
は銅箔をエツチングして所望のパターンに形成し、た導
電路（２）が設けられている。第２の基板（１１）は第
１の基板（１）に実装されるので第１の基板（１）より
小さく共通の統一した形状に形成される。(e) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2. The first and second substrates (1)Q]) are formed of epoxy resin glass plates or the like. A conductive path (2) is provided on one side of the first substrate (1) by etching a copper foil into a desired pattern. Since the second substrate (11) is mounted on the first substrate (1), it is smaller than the first substrate (1) and is formed into a common, uniform shape.

第２の基板（１１）の片面には基板より太き目の銅箔を
貼り、Ｐノ［梁形状にエツチングして中央にＱ↓固着バ
ンド（５）を基板（ＩＩの周端には多数の突出電極（４
）・・・（４）を′形成する。なお８１！２０基板ＯＤ
の突出電極（４）は同じ位置に形成され、且つ第１の基
板（１）の固着する導電路（２）と対応して形成される
。Paste a thicker copper foil than the board on one side of the second board (11), and etch it in the shape of a beam, and place a Q↓ fixing band (5) in the center on the peripheral edge of the board (II). protruding electrodes (4
)...(4) is formed. In addition, 81!20 board OD
The protruding electrodes (4) are formed at the same position and corresponding to the conductive paths (2) to which the first substrate (1) is fixed.

第２図に示す如（、第２の基板０１）の同右パッド（５
）には記憶用半導体素子（３）を固着し、突出電極（４
）から延在されたリード（６）先端にボンゲイングワイ
ヤーで電気的に接続される。記憶用半導体素子（３）は
一定の高さを有する樹脂枠体（７）で囲み、エポキシ樹
脂等の封止樹脂（８）を注入して封止する。The same right pad (5) of the second board 01 as shown in FIG.
), a memory semiconductor element (3) is fixed to the protruding electrode (4).
) is electrically connected to the tip of the lead (6) with a bonding wire. The memory semiconductor element (3) is surrounded by a resin frame (7) having a certain height, and sealed by injecting a sealing resin (8) such as epoxy resin.

斯ろ記憶用半導体素子（３）を組み込んだ第２の基板０
１）は第１の基板（１，１上のパスラインがら延在した
導電路（２）に第２の基板（１１）の各突出電極（４）
・・・（４）を半８３付けして、第２の基板ＣＩＩ）を
支持固定し且つ電気的接続をする。更にその上に重畳し
て第２の基板０１）を配置しその突出電極（４）を重ね
て第１の基板（１）の導電路（２）に半田付けして多ハ
ク冥装を行う。Thus, the second substrate 0 incorporating the memory semiconductor element (3)
1) is a conductive path (2) extending from the pass line on the first substrate (1, 1) to each protruding electrode (4) of the second substrate (11).
... (4) is attached in half 83 to support and fix the second board CII) and to make electrical connections. Further, a second substrate 01) is placed overlappingly thereon, and its protruding electrodes (4) are overlapped and soldered to the conductive paths (2) of the first substrate (1), thereby performing a multi-layered covering.

第２の基板０１）の突出電極（４）・・・（４）として
は記憶装置であるので′１「源ｖＩ）Ｄ　”　ＶＩＩＢ
端子、ナノグセレフト端子、アドレス端子、入出力端子
、リセット端子があり、重ねて導′「に路（２）に半田
伺けしても、チンプセレクト信号により所望の記憶装置
を動作させることができる。The protruding electrode (4)...(4) of the second substrate 01) is a memory device, so '1 "Source vI)D" VIIB
There are terminals, nano select terminals, address terminals, input/output terminals, and reset terminals, and even if the conductor paths (2) are overlaid with solder, the desired memory device can be operated by the chimp select signal.

本発明の第２の実施例は第３図を参照して説明する。上
述した実施例では第２の基板θ１）は突出電極（４）・
・・（４）により支持されているので振動等により突出
電極（４）・・・（４）が破断づ−るおそれがあった。A second embodiment of the invention will be described with reference to FIG. In the embodiment described above, the second substrate θ1) has protruding electrodes (4).
Since the projecting electrodes (4) are supported by (4), there is a risk that the protruding electrodes (4) may break due to vibration or the like.

これを改良するために第３図の如（、第２の基＆０１）
の反対主面に両面接着材層（９）を設け、この接着；ｊ
ｉ　Ｅづ（９）により第２の基板α１）相互を接着支持
するのである。To improve this, as shown in Figure 3 (, second group &01)
A double-sided adhesive layer (9) is provided on the opposite main surface of
The second substrates α1) are adhesively supported to each other by (9).

（へ）発明の効果 本発明に依れば第２の基板Ｈな用いることにより容易に
記憶装置の多層実装４苛造を実現できる。(f) Effects of the Invention According to the present invention, by using the second substrate H, it is possible to easily realize multilayer mounting 4 of a storage device.

この結果立体配置となるので実装密度が向上でき、記憶
装置の増設が面積を増加することなく実現できる。This results in a three-dimensional arrangement, which improves the packaging density and allows additional storage devices to be installed without increasing the area.

また両面接着材層（９）を用いると多層実装構造の機械
的強度の増加を図れ、多層の数量も増加でき実装密度の
向上に寄与できる。Further, by using the double-sided adhesive layer (9), it is possible to increase the mechanical strength of the multilayer mounting structure, and the number of multilayers can also be increased, contributing to an improvement in the mounting density.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の第１の実施例を説明する断面図、第２
図は本発明に用いる第２の基板を説明する上面図、第３
図は本発明の第２の実施例を説明する断面図である。 主な図番の説明 （１）は第１の基板、０１）は第２の基板、（３）は記
憶用半導体素子、（４）は突出電極、（９）は接着材層
である。 ２６FIG. 1 is a sectional view illustrating the first embodiment of the present invention;
The figure is a top view explaining the second substrate used in the present invention;
The figure is a sectional view illustrating a second embodiment of the present invention. Description of main figure numbers: (1) is the first substrate, 01) is the second substrate, (3) is the memory semiconductor element, (4) is the protruding electrode, and (9) is the adhesive layer. 26

Claims (1)

【特許請求の範囲】[Claims] １、所望のパターンの導電路を有する第１の基板と、記
憶用半導体素子を週み込み共通の突出電極を設けた第２
の基板とを具備し、該第２の基板を複数個重畳して前記
第１の基板に実装し前記共通の突出電極を前記導電路に
接続することを特徴とする記憶装置の多層実装構造。1. A first substrate having a conductive path in a desired pattern, and a second substrate having a common protruding electrode on which a memory semiconductor element is embedded.
1. A multilayer mounting structure for a memory device, comprising: a plurality of second substrates stacked on top of each other and mounted on the first substrate; and the common protruding electrode is connected to the conductive path.
JP1104783A 1983-01-25 1983-01-25 Multilayer mounting structure of memory storage Granted JPS59136963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1104783A JPS59136963A (en) 1983-01-25 1983-01-25 Multilayer mounting structure of memory storage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1104783A JPS59136963A (en) 1983-01-25 1983-01-25 Multilayer mounting structure of memory storage

Publications (2)

Publication Number Publication Date
JPS59136963A true JPS59136963A (en) 1984-08-06
JPH0481332B2 JPH0481332B2 (en) 1992-12-22

Family

ID=11767115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1104783A Granted JPS59136963A (en) 1983-01-25 1983-01-25 Multilayer mounting structure of memory storage

Country Status (1)

Country Link
JP (1) JPS59136963A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996583A (en) * 1989-02-15 1991-02-26 Matsushita Electric Industrial Co., Ltd. Stack type semiconductor package
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices
US5191404A (en) * 1989-12-20 1993-03-02 Digital Equipment Corporation High density memory array packaging
US5198888A (en) * 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
US5587341A (en) * 1987-06-24 1996-12-24 Hitachi, Ltd. Process for manufacturing a stacked integrated circuit package
US5633530A (en) * 1995-10-24 1997-05-27 United Microelectronics Corporation Multichip module having a multi-level configuration
JP2002360132A (en) * 2001-06-07 2002-12-17 Shimano Inc Fishing rod
US6570249B1 (en) * 2001-12-24 2003-05-27 Siliconware Precision Industries Co., Ltd. Semiconductor package
US7935572B2 (en) 2002-09-17 2011-05-03 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US8143100B2 (en) * 2002-09-17 2012-03-27 Chippac, Inc. Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929974A (en) * 1972-07-19 1974-03-16
JPS5141864A (en) * 1974-10-08 1976-04-08 Hitachi Ltd DENSHIKAIROSOCHI
JPS55165661A (en) * 1979-06-12 1980-12-24 Fujitsu Ltd Semiconductor device
JPS5688341A (en) * 1979-12-21 1981-07-17 Hitachi Ltd Laminated semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929974A (en) * 1972-07-19 1974-03-16
JPS5141864A (en) * 1974-10-08 1976-04-08 Hitachi Ltd DENSHIKAIROSOCHI
JPS55165661A (en) * 1979-06-12 1980-12-24 Fujitsu Ltd Semiconductor device
JPS5688341A (en) * 1979-12-21 1981-07-17 Hitachi Ltd Laminated semiconductor device

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521993B2 (en) 1987-06-24 2003-02-18 Hitachi, Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US6262488B1 (en) 1987-06-24 2001-07-17 Hitachi Ltd. Semiconductor memory module having double-sided memory chip layout
US6424030B2 (en) 1987-06-24 2002-07-23 Hitachi, Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US5587341A (en) * 1987-06-24 1996-12-24 Hitachi, Ltd. Process for manufacturing a stacked integrated circuit package
US5910685A (en) * 1987-06-24 1999-06-08 Hitachi Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US5708298A (en) * 1987-06-24 1998-01-13 Hitachi Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US6693346B2 (en) * 1987-06-24 2004-02-17 Hitachi, Ltd. Semiconductor memory module having double-sided stacked memory chip layout
US5334875A (en) * 1987-12-28 1994-08-02 Hitachi, Ltd. Stacked semiconductor memory device and semiconductor memory module containing the same
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices
US5198888A (en) * 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
US4996583A (en) * 1989-02-15 1991-02-26 Matsushita Electric Industrial Co., Ltd. Stack type semiconductor package
US5191404A (en) * 1989-12-20 1993-03-02 Digital Equipment Corporation High density memory array packaging
US5633530A (en) * 1995-10-24 1997-05-27 United Microelectronics Corporation Multichip module having a multi-level configuration
JP2002360132A (en) * 2001-06-07 2002-12-17 Shimano Inc Fishing rod
US6570249B1 (en) * 2001-12-24 2003-05-27 Siliconware Precision Industries Co., Ltd. Semiconductor package
US6689636B2 (en) 2001-12-24 2004-02-10 Siliconware Precision Industries Co., Ltd. Semiconductor device and fabrication method of the same
US8143100B2 (en) * 2002-09-17 2012-03-27 Chippac, Inc. Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages
US7935572B2 (en) 2002-09-17 2011-05-03 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages

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Publication number Publication date
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