JPS59134851A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59134851A JPS59134851A JP912483A JP912483A JPS59134851A JP S59134851 A JPS59134851 A JP S59134851A JP 912483 A JP912483 A JP 912483A JP 912483 A JP912483 A JP 912483A JP S59134851 A JPS59134851 A JP S59134851A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- hole
- cap
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は封止方法を改良した半導体装置に関するもので
、筒信頼度の半導体装置を提供するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device with an improved sealing method, and provides a semiconductor device with high cylinder reliability.
従来、この種の装置として第１図および第２図に示すも
のがあった。図において、１は絶縁基板、４はこの絶縁
基板１土に形成されたメタライズ、２はこのメタライズ
４土にマウントされた半壱俸チップ、６はベースリード
、７はコレクタリード、５はブリッジ、３は半導体チッ
プ２とメタライズ４とを結合する全極細線、８は上記半
導体チップ２を絶縁基板１上に位」脂到止する中空キャ
ップ、９は封止用の樹脂である。Conventionally, there have been devices of this type as shown in FIGS. 1 and 2. In the figure, 1 is an insulating substrate, 4 is a metallization formed on this insulating substrate 1, 2 is a half-chip chip mounted on this metallization 4, 6 is a base lead, 7 is a collector lead, 5 is a bridge, Reference numeral 3 designates an ultra-fine wire that connects the semiconductor chip 2 and the metallization 4, 8 a hollow cap that secures the semiconductor chip 2 onto the insulating substrate 1, and 9 a resin for sealing.
従来の半導体装置においては、第１図およびあ２図に示
すように、半導体チップ２を金属細線３によジメタライ
ズ４と結合し、その上でこれらを、中空キャップ８を用
いて封止していた。In a conventional semiconductor device, as shown in FIGS. 1 and 2, a semiconductor chip 2 is bonded to a dimetallized metal wire 4 using a thin metal wire 3, and then these are sealed using a hollow cap 8. Ta.
この一台、樹脂９を用いて中空キャップ８を接冶封止す
るが、封止後の半導体装置のリークの保証がグｏスリー
ク（１×１０ ＣＣ／５ｅＣ）以上を貿求される場合、
一般に樹脂（接着剤）は熱硬化型を用いるので、樹脂が
硬化する際に、キャップ中の空気の熱膨張と、外部との
気圧の差とによシ樹脂に穴があき易＜、ｉｏｏ％の歩留
シをもって製品を製造することは困難となる。In this one, the hollow cap 8 is welded and sealed using the resin 9, but if the guarantee of leakage of the semiconductor device after sealing is more than a good leak (1 x 10 CC/5eC),
Generally, thermosetting resins (adhesives) are used, so when the resin hardens, holes are easily formed in the resin due to the thermal expansion of the air in the cap and the difference in air pressure between the outside and the outside. It becomes difficult to manufacture products with a yield of .
また、常温硬化型の樹脂を用いることも考えられるが、
一般に常温硬化型の樹脂は環境試験（例えは温度サイク
ル）佑に脆く使用できない。It is also possible to use a resin that hardens at room temperature, but
In general, resins that cure at room temperature cannot be used because they are brittle in environmental tests (eg, temperature cycles).
更に、封止の十法として樹脂のかわシに半田付等が考え
られるが、その場付、半導体装置の構造そのものが被雑
になシ、その結果として価格上昇につながシ、％殊な用
途以外には採用できない。Furthermore, soldering to a resin adhesive may be considered as one of the ten methods for sealing, but it would complicate the structure of the semiconductor device itself, resulting in an increase in price. It cannot be adopted by anyone else.
本発明は以上の点に鑑みてなされたもので、半導体チッ
プを封止するための中空キャップに空気抜きの穴を設け
、このキャップを熱硬化型樹脂で接着した後その穴を常
温硬化型樹脂で埋めることによシ、低価格であシながら
高信頼度のリーク保証をもった半導体装置を提供するこ
とを目的としている。The present invention has been made in view of the above points, and involves providing an air vent hole in a hollow cap for sealing a semiconductor chip, bonding the cap with a thermosetting resin, and then filling the hole with a room temperature curing resin. The purpose of the present invention is to provide a semiconductor device that is low in price and has high reliability and leakage guarantee.
以下、この発明の一実施例を図について脱明する。 Hereinafter, one embodiment of the present invention will be explained with reference to the drawings.
第３図および第４図は不発明の一実施例による半導体装
置を示す。両図において第１図および第２図と同一符号
は同一のものを示し、本実施例装置において、中空キャ
ップ８の上面には空気抜きの穴１０が設けられている。3 and 4 show a semiconductor device according to an embodiment of the invention. In both figures, the same reference numerals as in FIGS. 1 and 2 indicate the same parts, and in the device of this embodiment, an air vent hole 10 is provided in the upper surface of the hollow cap 8.
半導体装置の組立ては従来と同様に行われ、組立完了後
、空気抜きの穴１０を常温硬化型の樹脂によシ穴埋めす
る。この構造を採用することによシ安定した歩留シでも
って、低価格かつ信租度の高い半導体装置の製造が可能
となる。The semiconductor device is assembled in the same manner as before, and after the assembly is completed, the air vent holes 10 are filled with room temperature curing resin. By employing this structure, it is possible to manufacture semiconductor devices at low cost and with high reliability with a stable yield.
なお、上記実施例では通常の半導体装置について読切し
たが、第５図、第６図に示すように混成集積回路に適用
することもできる。両図において、１．２はそれぞれ絶
縁基板および半導体チップである０
混成集積回路においては、半導体チップ２を金塊細線３
で結合したｂ分の信頼性が問題にされることが多く、本
発明によシこの問題も解消できる。Note that although the above embodiments have been described with reference to ordinary semiconductor devices, the present invention can also be applied to hybrid integrated circuits as shown in FIGS. 5 and 6. In both figures, 1 and 2 are an insulating substrate and a semiconductor chip, respectively.
The reliability of b combined in is often a problem, and the present invention can also solve this problem.
以上のように、この発明によれば、半導体チップを封止
するだめの中空キャップに空気抜きの穴を設け、このキ
ャップを熱硬化型樹脂で接着した後その穴を常温硬化型
樹脂で埋めるようにしだので、低価格であシながら筒信
頼度のリーク保証をもった半導体装置を提供できる効果
がある。As described above, according to the present invention, an air vent hole is provided in a hollow cap for sealing a semiconductor chip, and after this cap is bonded with a thermosetting resin, the hole is filled with a room temperature curing resin. Therefore, it is possible to provide a semiconductor device which is low in price and has leakage guarantee of cylinder reliability.
第１図および第２図は従来の半導体装１に’に示す平面
図および断ｌし１、゛第３図および第４図は本発明の一
実施例による半導体装置を示す平面図および断面図、第
５図および第６図は本発明の他の夫ツブ、３は金塊細線
、４はメタライズ、８は中空キャップ、１０は空気抜き
の穴である。
なお図中同一符号は同−又は相当鮨５分を示寸Ｏ代理人
葛野他−
第１図1 and 2 are a plan view and a cross-sectional view of a conventional semiconductor device 1, and FIGS. 3 and 4 are a plan view and a cross-sectional view of a semiconductor device according to an embodiment of the present invention. , 5 and 6 are other hubs of the present invention, 3 is a thin gold ingot wire, 4 is metallized, 8 is a hollow cap, and 10 is an air vent hole. In addition, the same reference numerals in the diagram indicate the same or equivalent 5 minutes of sushi.
Claims (1)
ズ上にマウントされた半導体チップと、該半導体チップ
と上記メタライズ配線パターンとを結合する金總細線と
、上面もしくは側面に空気抜きの穴を備え上記半導体チ
ップを上記絶縁基板上に樹脂封止する中空キャップと、
上記樹脂封止後上記空気抜きの穴に充填された常温硬化
型の樹脂とを倫えたことを％にとする半導体装置。(1) An insulating substrate, a semiconductor chip mounted on a metallized layer formed on the insulating substrate, a thin gold wire connecting the semiconductor chip and the metallized wiring pattern, and an air vent hole on the top or side surface. a hollow cap for resin-sealing the semiconductor chip onto the insulating substrate;
The semiconductor device is characterized in that the temperature of the room-temperature curing resin filled in the air vent hole after sealing with the resin is maintained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP912483A JPS59134851A (en) | 1983-01-20 | 1983-01-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP912483A JPS59134851A (en) | 1983-01-20 | 1983-01-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59134851A true JPS59134851A (en) | 1984-08-02 |
Family
ID=11711887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP912483A Pending JPS59134851A (en) | 1983-01-20 | 1983-01-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59134851A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101198762B1 (en) | 2006-06-22 | 2012-11-12 | 엘지이노텍 주식회사 | light emitting diode package and method for fabricating the same |
-
1983
- 1983-01-20 JP JP912483A patent/JPS59134851A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101198762B1 (en) | 2006-06-22 | 2012-11-12 | 엘지이노텍 주식회사 | light emitting diode package and method for fabricating the same |
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