JPH10144828A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH10144828A JPH10144828A JP8309905A JP30990596A JPH10144828A JP H10144828 A JPH10144828 A JP H10144828A JP 8309905 A JP8309905 A JP 8309905A JP 30990596 A JP30990596 A JP 30990596A JP H10144828 A JPH10144828 A JP H10144828A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- stress
- resin
- stress buffer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、リードフレームと
半導体素子の接続に金属ボールを用いた半導体パッケー
ジに関する。The present invention relates to a semiconductor package using metal balls for connecting a lead frame and a semiconductor element.
【0002】[0002]
【従来の技術】従来、図4に示すようにリードフレーム
3を使用した半導体パッケージ20ではアイランド部3
aへ半導体素子1を接合し、この半導体素子1の電極部
とリードフレーム3とを金属細線6を介して電気的に接
続し樹脂4にて封止していた。また図5に示すようにT
AB導体パッケージ30では半導体素子1の電極部とイ
ンナーリード7aとを金属バンプまたは金属球2を介し
て電気的に接続し、その周辺に液状樹脂4aを滴下し封
止していた。2. Description of the Related Art Conventionally, in a semiconductor package 20 using a lead frame 3 as shown in FIG.
The semiconductor element 1 was joined to the substrate a, and the electrode portion of the semiconductor element 1 and the lead frame 3 were electrically connected via the thin metal wire 6 and sealed with the resin 4. Also, as shown in FIG.
In the AB conductor package 30, the electrode portion of the semiconductor element 1 and the inner lead 7a are electrically connected via a metal bump or a metal ball 2, and a liquid resin 4a is dropped and sealed around the periphery.
【0003】[0003]
【発明が解決しようとする課題】ところで、図4に示す
ように半導体素子の電極部とリードフレーム3とを金属
細線6を介して電気的に接続するため金属細線の立上が
り高さを設けてやる必要が有り、樹脂部を薄くできない
という問題があった。また図5に示すようにTABテー
プを使用した場合、パッケージとして液状樹脂4aを滴
下し封止するため外形寸法が安定しないという問題があ
った。さらにTABテープを使用するため製造コストが
高くなるという問題があった。そこで本発明は、薄型で
かつ低コストで製造できる半導体パッケージを提供する
ことを目的とする。By the way, as shown in FIG. 4, in order to electrically connect the electrode portion of the semiconductor element and the lead frame 3 via the thin metal wire 6, a rising height of the thin metal wire is provided. However, there is a problem that the resin portion cannot be made thin. When a TAB tape is used as shown in FIG. 5, there is a problem that the external dimensions are not stable because the liquid resin 4a is dropped and sealed as a package. Further, the use of TAB tapes has a problem that the production cost is high. Therefore, an object of the present invention is to provide a semiconductor package that is thin and can be manufactured at low cost.
【0004】[0004]
【課題を解決するための手段】上記課題を解決するた
め、本願の請求項1記載の発明によれば、半導体素子上
に形成された電極部とリードフレームの接続部とを金属
ボールを介して接続し、樹脂封止した半導体パッケージ
において、前記接続部の周辺に応力緩衝材を設けた構成
を有するものであり、また、請求項2記載の発明によれ
ば、上記応力緩衝材が金属ボールの接合部および半導体
素子の回路部全面を覆っている構成を有するものであ
り、さらに、請求項3記載の発明によれば、上記応力緩
衝材が少なくとも金属ボールの接合部を覆っている構成
を有するものであり、そして、請求項4記載の発明によ
れば、リードフレームの両面にそれぞれ金属ボールを接
合し、これら金属ボール各々の面に電極部を形成された
半導体素子を各々接合した半導体パッケージにおいて、
各半導体素子間に応力緩衝材を設けた構成を有するもの
である。According to the first aspect of the present invention, an electrode formed on a semiconductor element and a connecting portion of a lead frame are connected via a metal ball. In the semiconductor package connected and resin-sealed, the semiconductor package has a configuration in which a stress buffer is provided around the connection portion. According to the invention of claim 2, the stress buffer is a metal ball. According to the third aspect of the present invention, the stress buffering material covers at least the bonding portion of the metal ball. According to the invention as set forth in claim 4, metal balls are bonded to both surfaces of the lead frame, and semiconductor elements having electrode portions formed on the respective surfaces of the metal balls are bonded to each other. In the semiconductor package,
It has a configuration in which a stress buffer is provided between each semiconductor element.
【0005】これらの各構成を有することにより、樹脂
封止後の高温下から常温に移行する際の樹脂の熱収縮、
製品使用時の昇温に伴う熱膨張等による接合部へのスト
レスを応力緩衝材を介し吸収することができ、かつ薄型
の半導体パッケージを製造することができる。[0005] By having each of these components, heat shrinkage of the resin at the time of transition from high temperature to normal temperature after resin sealing,
The stress on the joint due to thermal expansion or the like due to a rise in temperature during use of the product can be absorbed via the stress buffer, and a thin semiconductor package can be manufactured.
【0006】[0006]
【発明の実施の形態】本発明の第1の実施の形態を図1
を参照して説明する。図1は第1の実施の形態である半
導体パッケージの断面図である。図1に示すように、本
発明の第1の実施の形態である半導体パッケージ10で
は、パターンが形成されているリードフレーム3と半導
体素子1が金属球2を介して接続され、応力緩衝材5が
前述の半導体素子1および金属球2を覆うように形成さ
れた後、樹脂4によって封止されている。FIG. 1 shows a first embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 is a cross-sectional view of the semiconductor package according to the first embodiment. As shown in FIG. 1, in a semiconductor package 10 according to a first embodiment of the present invention, a lead frame 3 on which a pattern is formed and a semiconductor element 1 are connected via a metal ball 2, and a stress buffer 5 Are formed so as to cover the semiconductor element 1 and the metal ball 2 described above, and are then sealed with a resin 4.
【0007】ここで図1に示すように、応力緩衝材5
は、シリコーン等の外部からの圧縮・膨張応力を緩和で
きる材料からなるものである。Here, as shown in FIG.
Is made of a material such as silicone which can relieve external compression / expansion stress.
【0008】上記の様に構成された本実施の形態によれ
ば、樹脂封止後の高温下から常温に移行する際の樹脂の
熱収縮、製品使用時の昇温に伴う熱膨張等による接合部
2aへのストレスを応力緩衝材5を介し吸収することが
でき、かつ薄型の半導体パッケージを製造することがで
きる。[0010] According to the present embodiment configured as described above, the resin is sealed by heat shrinkage at the time of transition from a high temperature to a normal temperature after the resin encapsulation, bonding by thermal expansion accompanying a rise in temperature during use of the product, and the like. The stress on the portion 2a can be absorbed through the stress buffer 5, and a thin semiconductor package can be manufactured.
【0009】次に本発明の第2の実施の形態を図2を参
照して説明する。上記第1の実施の形態と異なる点は、
応力緩衝材5が接合部2a付近にのみ設けられているこ
とである。Next, a second embodiment of the present invention will be described with reference to FIG. The difference from the first embodiment is that
The point is that the stress buffer 5 is provided only near the joint 2a.
【0010】上記の様に構成された本実施の形態によれ
ば、応力緩衝材5を接合部2a付近にのみ設けたことに
より応力緩衝材の使用量を削減しつつ、応力の緩和を行
う事ができる。According to the present embodiment configured as described above, the stress buffering material 5 is provided only in the vicinity of the joint 2a so that the stress buffering material can be used while reducing the amount of stress buffering material used. Can be.
【0011】次に本発明の第3の実施の形態を図3を参
照して説明する。上記第1の実施の形態と異なる点は、
パターンが形成されているリードフレーム3の両面に金
属球2が設けられ、前述の金属球2を介し半導体素子1
が両面に接続されており、且つ応力緩衝材5が接合部2
a,2b、および半導体素子1,1a間に充填されてい
ることである。Next, a third embodiment of the present invention will be described with reference to FIG. The difference from the first embodiment is that
Metal balls 2 are provided on both sides of a lead frame 3 on which a pattern is formed.
Are connected to both sides, and the stress buffer 5
a, 2b and between the semiconductor elements 1, 1a.
【0012】上記の様に構成された本実施の形態によれ
ば、応力緩衝材5を半導体素子1,1a間に充填させた
ことにより接合部2a,2b部の応力の緩和を行う事が
できる。According to the present embodiment configured as described above, the stress in the joints 2a and 2b can be reduced by filling the stress buffer 5 between the semiconductor elements 1 and 1a. .
【0013】[0013]
【発明の効果】以上説明したように、本願の各請求項記
載の発明によれば、半導体素子とリードフレームの電気
的接合に金属球を用い、かつ、金属球周辺に応力緩衝材
を設けたことにより、薄型で低コストの半導体パッケー
ジが提供できる。As described above, according to the invention described in the claims of the present application, a metal ball is used for electrical connection between a semiconductor element and a lead frame, and a stress buffer is provided around the metal ball. Thus, a thin and low-cost semiconductor package can be provided.
【図1】本発明の第1の実施の形態である半導体パッケ
ージの断面図である。FIG. 1 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention.
【図2】本発明の第2の実施の形態である半導体パッケ
ージの断面図である。FIG. 2 is a sectional view of a semiconductor package according to a second embodiment of the present invention.
【図3】本発明の第3の実施の形態である半導体パッケ
ージの断面図である。FIG. 3 is a sectional view of a semiconductor package according to a third embodiment of the present invention.
【図4】従来の半導体パッケージの断面図である。FIG. 4 is a cross-sectional view of a conventional semiconductor package.
【図5】従来の半導体パッケージの断面図である。FIG. 5 is a sectional view of a conventional semiconductor package.
1 半導体素子 1a 半導体素子 2 金属ボール 2a 接合部 2b 接合部 3 リードフレーム 3a アイランド 4 樹脂 4a 樹脂 5 応力緩衝剤 6 金属細線 7 フィルムキャリア 7a インナーリード 10 半導体パッケージ 20 従来の半導体パッケージ 30 TABを使用した半導体パッケージ REFERENCE SIGNS LIST 1 semiconductor element 1a semiconductor element 2 metal ball 2a joint 2b joint 3 lead frame 3a island 4 resin 4a resin 5 stress buffer 6 thin metal wire 7 film carrier 7a inner lead 10 semiconductor package 20 conventional semiconductor package 30 TAB Semiconductor package
Claims (4)
ドフレームの接続部とを金属ボールを介して接続し、樹
脂封止した半導体パッケージにおいて、前記接続部の周
辺に応力緩衝材を設けたことを特徴とする半導体パッケ
ージ。An electrode formed on a semiconductor element and a connection portion of a lead frame are connected via a metal ball, and a resin-sealed semiconductor package is provided with a stress buffer around the connection portion. A semiconductor package characterized by the above-mentioned.
よび半導体素子の回路部全面を覆っていることを特徴と
する請求項1記載の半導体パッケージ。2. The semiconductor package according to claim 1, wherein said stress buffering material covers a joint portion of the metal ball and an entire circuit portion of the semiconductor element.
の接合部を覆っていることを特徴とする請求項1記載の
半導体パッケージ。3. The semiconductor package according to claim 1, wherein said stress buffering material covers at least a joint of the metal balls.
ールを接合し、これら金属ボール各々の面に電極部を形
成された半導体素子を各々接合した半導体パッケージに
おいて、各半導体素子間に応力緩衝材を設けたことを特
徴とする半導体パッケージ。4. In a semiconductor package in which metal balls are bonded to both surfaces of a lead frame, and semiconductor elements having electrode portions formed on the respective surfaces of the metal balls are bonded to each other, a stress buffer is provided between the semiconductor elements. A semiconductor package characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8309905A JPH10144828A (en) | 1996-11-07 | 1996-11-07 | Semiconductor package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8309905A JPH10144828A (en) | 1996-11-07 | 1996-11-07 | Semiconductor package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH10144828A true JPH10144828A (en) | 1998-05-29 |
Family
ID=17998753
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8309905A Pending JPH10144828A (en) | 1996-11-07 | 1996-11-07 | Semiconductor package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH10144828A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100344833B1 (en) * | 2000-04-03 | 2002-07-20 | 주식회사 하이닉스반도체 | Package of semiconductor and method for fabricating the same |
JP2008147604A (en) * | 2006-12-12 | 2008-06-26 | Gem Services Inc | Semiconductor device package featuring encapsulated leadframe with projecting bumps or balls |
-
1996
- 1996-11-07 JP JP8309905A patent/JPH10144828A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100344833B1 (en) * | 2000-04-03 | 2002-07-20 | 주식회사 하이닉스반도체 | Package of semiconductor and method for fabricating the same |
JP2008147604A (en) * | 2006-12-12 | 2008-06-26 | Gem Services Inc | Semiconductor device package featuring encapsulated leadframe with projecting bumps or balls |
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