JPS59134819A - 半導体基板の製造方法 - Google Patents

半導体基板の製造方法

Info

Publication number
JPS59134819A
JPS59134819A JP15376682A JP15376682A JPS59134819A JP S59134819 A JPS59134819 A JP S59134819A JP 15376682 A JP15376682 A JP 15376682A JP 15376682 A JP15376682 A JP 15376682A JP S59134819 A JPS59134819 A JP S59134819A
Authority
JP
Japan
Prior art keywords
film
substrate
silicon
single crystal
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15376682A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0113210B2 (enrdf_load_stackoverflow
Inventor
Nobuhiro Endo
遠藤 伸裕
Akihiko Ishitani
石谷 明彦
Hiroshi Kitajima
洋 北島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15376682A priority Critical patent/JPS59134819A/ja
Publication of JPS59134819A publication Critical patent/JPS59134819A/ja
Publication of JPH0113210B2 publication Critical patent/JPH0113210B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639Preparation of substrate for selective deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
JP15376682A 1982-09-03 1982-09-03 半導体基板の製造方法 Granted JPS59134819A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15376682A JPS59134819A (ja) 1982-09-03 1982-09-03 半導体基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15376682A JPS59134819A (ja) 1982-09-03 1982-09-03 半導体基板の製造方法

Publications (2)

Publication Number Publication Date
JPS59134819A true JPS59134819A (ja) 1984-08-02
JPH0113210B2 JPH0113210B2 (enrdf_load_stackoverflow) 1989-03-03

Family

ID=15569659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15376682A Granted JPS59134819A (ja) 1982-09-03 1982-09-03 半導体基板の製造方法

Country Status (1)

Country Link
JP (1) JPS59134819A (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4758531A (en) * 1987-10-23 1988-07-19 International Business Machines Corporation Method of making defect free silicon islands using SEG
US5135884A (en) * 1991-03-28 1992-08-04 Sgs-Thomson Microelectronics, Inc. Method of producing isoplanar isolated active regions
US5202284A (en) * 1989-12-01 1993-04-13 Hewlett-Packard Company Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2
US5213989A (en) * 1992-06-24 1993-05-25 Motorola, Inc. Method for forming a grown bipolar electrode contact using a sidewall seed

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4758531A (en) * 1987-10-23 1988-07-19 International Business Machines Corporation Method of making defect free silicon islands using SEG
US5202284A (en) * 1989-12-01 1993-04-13 Hewlett-Packard Company Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2
US5135884A (en) * 1991-03-28 1992-08-04 Sgs-Thomson Microelectronics, Inc. Method of producing isoplanar isolated active regions
US5213989A (en) * 1992-06-24 1993-05-25 Motorola, Inc. Method for forming a grown bipolar electrode contact using a sidewall seed

Also Published As

Publication number Publication date
JPH0113210B2 (enrdf_load_stackoverflow) 1989-03-03

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