JPS59132492A - 半導体記憶装置 - Google Patents
半導体記憶装置Info
- Publication number
- JPS59132492A JPS59132492A JP57223678A JP22367882A JPS59132492A JP S59132492 A JPS59132492 A JP S59132492A JP 57223678 A JP57223678 A JP 57223678A JP 22367882 A JP22367882 A JP 22367882A JP S59132492 A JPS59132492 A JP S59132492A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- potential
- bit line
- gate
- pull
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57223678A JPS59132492A (ja) | 1982-12-22 | 1982-12-22 | 半導体記憶装置 |
| US06/561,964 US4601017A (en) | 1982-12-22 | 1983-12-15 | Semiconductor memory device having active pull-up circuits |
| EP83307728A EP0114492B1 (en) | 1982-12-22 | 1983-12-19 | Semiconductor memory device having active pull-up circuits |
| DE8383307728T DE3379360D1 (en) | 1982-12-22 | 1983-12-19 | Semiconductor memory device having active pull-up circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57223678A JPS59132492A (ja) | 1982-12-22 | 1982-12-22 | 半導体記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59132492A true JPS59132492A (ja) | 1984-07-30 |
| JPH0252358B2 JPH0252358B2 (en:Method) | 1990-11-13 |
Family
ID=16801929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57223678A Granted JPS59132492A (ja) | 1982-12-22 | 1982-12-22 | 半導体記憶装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4601017A (en:Method) |
| EP (1) | EP0114492B1 (en:Method) |
| JP (1) | JPS59132492A (en:Method) |
| DE (1) | DE3379360D1 (en:Method) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6194296A (ja) * | 1984-10-16 | 1986-05-13 | Fujitsu Ltd | 半導体記憶装置 |
| JPS629590A (ja) * | 1985-07-08 | 1987-01-17 | Nec Corp | 増幅回路 |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6043296A (ja) * | 1983-08-17 | 1985-03-07 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPS61151898A (ja) * | 1984-12-26 | 1986-07-10 | Fujitsu Ltd | 半導体記憶装置におけるワ−ド線ドライバ回路 |
| EP0189908B1 (en) * | 1985-01-30 | 1992-10-28 | Nec Corporation | Dynamic memory with improved arrangement for precharging bit lines |
| JPS61217993A (ja) * | 1985-03-22 | 1986-09-27 | Mitsubishi Electric Corp | 半導体メモリ |
| JPS61239493A (ja) * | 1985-04-05 | 1986-10-24 | Fujitsu Ltd | 半導体記憶装置 |
| JPH0664907B2 (ja) * | 1985-06-26 | 1994-08-22 | 株式会社日立製作所 | ダイナミツク型ram |
| US4740921A (en) * | 1985-10-04 | 1988-04-26 | Motorola, Inc. | Precharge of a dram data line to an intermediate voltage |
| JPS62114190A (ja) * | 1985-11-13 | 1987-05-25 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPS62134894A (ja) * | 1985-12-06 | 1987-06-17 | Mitsubishi Electric Corp | 半導体記憶装置 |
| USRE34463E (en) * | 1985-12-06 | 1993-11-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with active pull up |
| US4701644A (en) * | 1986-08-13 | 1987-10-20 | Harris Corporation | Low power sense amplifier |
| JPS6376193A (ja) * | 1986-09-19 | 1988-04-06 | Fujitsu Ltd | 半導体記憶装置 |
| JPS6376192A (ja) * | 1986-09-19 | 1988-04-06 | Fujitsu Ltd | 半導体記憶装置 |
| US4768167A (en) * | 1986-09-30 | 1988-08-30 | International Business Machines Corporation | High speed CMOS latch with alternate data storage and test functions |
| US4804871A (en) * | 1987-07-28 | 1989-02-14 | Advanced Micro Devices, Inc. | Bit-line isolated, CMOS sense amplifier |
| JP2537264B2 (ja) * | 1988-04-13 | 1996-09-25 | 株式会社東芝 | 半導体記憶装置 |
| JPH02198097A (ja) * | 1989-01-25 | 1990-08-06 | Nec Ic Microcomput Syst Ltd | 半導体スタチックメモリ |
| EP0430614B1 (en) * | 1989-12-01 | 1996-02-07 | Matsushita Electronics Corporation | A dynamic type semiconductor memory |
| US5304874A (en) * | 1991-05-31 | 1994-04-19 | Thunderbird Technologies, Inc. | Differential latching inverter and random access memory using same |
| US5214317A (en) * | 1992-05-04 | 1993-05-25 | National Semiconductor Corporation | CMOS to ECL translator with incorporated latch |
| KR950014256B1 (ko) * | 1993-04-06 | 1995-11-23 | 삼성전자주식회사 | 낮은 전원전압을 사용하는 반도체 메모리장치 |
| US5602785A (en) * | 1995-12-13 | 1997-02-11 | Micron Technology, Inc. | P-channel sense amplifier pull-up circuit with a timed pulse for use in DRAM memories having non-bootstrapped word lines |
| US5933043A (en) * | 1996-10-22 | 1999-08-03 | Kabushiki Kaisha Toshiba | High speed level shift circuit |
| US6111802A (en) * | 1997-05-19 | 2000-08-29 | Fujitsu Limited | Semiconductor memory device |
| US6147893A (en) * | 1999-01-27 | 2000-11-14 | Vlsi Technology, Inc. | Programmable read only memory with high speed differential sensing at low operating voltage |
| US10318903B2 (en) | 2016-05-06 | 2019-06-11 | General Electric Company | Constrained cash computing system to optimally schedule aircraft repair capacity with closed loop dynamic physical state and asset utilization attainment control |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57152698U (en:Method) * | 1981-03-17 | 1982-09-25 | ||
| JPS5942693A (ja) * | 1982-09-01 | 1984-03-09 | Nec Corp | センスアンプ回路 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4028557A (en) * | 1976-05-21 | 1977-06-07 | Bell Telephone Laboratories, Incorporated | Dynamic sense-refresh detector amplifier |
| JPS53120238A (en) * | 1977-03-29 | 1978-10-20 | Mitsubishi Electric Corp | Semiconductor amplifier |
| US4262342A (en) * | 1979-06-28 | 1981-04-14 | Burroughs Corporation | Charge restore circuit for semiconductor memories |
| JPS5730192A (en) * | 1980-07-29 | 1982-02-18 | Fujitsu Ltd | Sense amplifying circuit |
| JPS5894189A (ja) * | 1981-11-27 | 1983-06-04 | Fujitsu Ltd | ダイナミツク型半導体記憶装置 |
| JPS5891594A (ja) * | 1981-11-27 | 1983-05-31 | Fujitsu Ltd | ダイナミツク型半導体記憶装置 |
-
1982
- 1982-12-22 JP JP57223678A patent/JPS59132492A/ja active Granted
-
1983
- 1983-12-15 US US06/561,964 patent/US4601017A/en not_active Expired - Fee Related
- 1983-12-19 DE DE8383307728T patent/DE3379360D1/de not_active Expired
- 1983-12-19 EP EP83307728A patent/EP0114492B1/en not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57152698U (en:Method) * | 1981-03-17 | 1982-09-25 | ||
| JPS5942693A (ja) * | 1982-09-01 | 1984-03-09 | Nec Corp | センスアンプ回路 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6194296A (ja) * | 1984-10-16 | 1986-05-13 | Fujitsu Ltd | 半導体記憶装置 |
| JPS629590A (ja) * | 1985-07-08 | 1987-01-17 | Nec Corp | 増幅回路 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0114492A3 (en) | 1986-09-10 |
| EP0114492B1 (en) | 1989-03-08 |
| EP0114492A2 (en) | 1984-08-01 |
| JPH0252358B2 (en:Method) | 1990-11-13 |
| DE3379360D1 (en) | 1989-04-13 |
| US4601017A (en) | 1986-07-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS59132492A (ja) | 半導体記憶装置 | |
| US7057917B2 (en) | Ferroelectric memory with an intrinsic access transistor coupled to a capacitor | |
| US5910911A (en) | Semiconductor memory and process of operating the same | |
| JPS63288496A (ja) | 高性能dramのためのセンス増幅器 | |
| JPH069114B2 (ja) | 半導体メモリ | |
| JPH0352187A (ja) | ダイナミック型ランダムアクセスメモリ | |
| JPS6137704B2 (en:Method) | ||
| JPH0320836B2 (en:Method) | ||
| KR100512545B1 (ko) | 리프레쉬 동작이 불필요한 메모리 셀을 구비하는 반도체기억 장치 | |
| KR100215734B1 (ko) | 반도체 기억장치 및 데이타처리장치 | |
| EP1619690B1 (en) | Semiconductor memory device | |
| US6631094B2 (en) | Semiconductor memory device having SRAM interface | |
| JPS599990B2 (ja) | 半導体記憶装置 | |
| JPS6376192A (ja) | 半導体記憶装置 | |
| JP2003272383A (ja) | Dramアレイ用ビット線プリチャージ手法およびセンスアンプ、ならびにdramアレイを組込んだ集積回路装置 | |
| JPS60179993A (ja) | ランダムアクセスメモリ | |
| JP4865121B2 (ja) | 少なくとも一つのメモリーセルにカップリングされたシングルビットラインを有する強誘電体メモリ素子 | |
| JPS60182595A (ja) | ランダムアクセスメモリ | |
| JP2002170382A (ja) | 半導体記憶装置 | |
| JPS63183692A (ja) | 半導体記憶装置 | |
| JP2579975B2 (ja) | 半導体記憶装置 | |
| JPS63244395A (ja) | ダイナミツク型半導体記憶装置 | |
| JPS6333239B2 (en:Method) | ||
| JPS6150286A (ja) | Mos型再生回路 | |
| JPH07262778A (ja) | 半導体記憶装置 |