JPS59131208A - Microwave monolithic amplifier - Google Patents
Microwave monolithic amplifierInfo
- Publication number
- JPS59131208A JPS59131208A JP58005692A JP569283A JPS59131208A JP S59131208 A JPS59131208 A JP S59131208A JP 58005692 A JP58005692 A JP 58005692A JP 569283 A JP569283 A JP 569283A JP S59131208 A JPS59131208 A JP S59131208A
- Authority
- JP
- Japan
- Prior art keywords
- matching circuit
- input
- thickness
- output
- transmission line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Waveguides (AREA)
- Microwave Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はマイクロ波低雑音モノリシック増幅器に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to microwave low noise monolithic amplifiers.
近年、マイクロ波増幅器の量産化をめざして、モノリシ
ックIC構成のマイクロ波増幅器の研究開発が盛んに行
なわれている。しかしながらモノリシックICにおいて
は、ハイブリッドICで通常行なわれている回路トリミ
ングができないため、回路パラメータの変動によりわず
かに帯域等がずれてもこれを修正することができず不良
品となってしまうという問題があった。In recent years, with the aim of mass producing microwave amplifiers, research and development of microwave amplifiers having a monolithic IC configuration has been actively conducted. However, with monolithic ICs, the circuit trimming that is normally done with hybrid ICs is not possible, so even if the band shifts slightly due to fluctuations in circuit parameters, this cannot be corrected, resulting in a defective product. there were.
本発明の目的は、前記問題を解決し、増幅器の特性を均
一化でき大量生産を可能にしたマイクロ −波モノ
リシック増幅器を提供することにおる。SUMMARY OF THE INVENTION An object of the present invention is to provide a microwave monolithic amplifier which solves the above-mentioned problems, has uniform amplifier characteristics, and can be mass-produced.
本発明の構成は、分布定数線路、インダクタおよびキャ
パシタの内の1種類以上の回路素子からなる入力整合回
路、段間整合回路および出力整合回路を備えたマイクロ
波モノリンツク増幅器において、前記入力整合回路の伝
送線路の導体厚を表皮効果における高周波電流の流れる
表皮厚さより厚くシ、前記段間および出力整合回路の伝
送線路の導体厚を前記表皮厚さよシ薄くしたことを特徴
とする。The configuration of the present invention provides a microwave monolink amplifier equipped with an input matching circuit, an interstage matching circuit, and an output matching circuit each including one or more circuit elements of a distributed constant line, an inductor, and a capacitor. The conductor thickness of the transmission line is thicker than the skin thickness through which high-frequency current flows in the skin effect, and the conductor thickness of the transmission line between the stages and the output matching circuit is thinner than the skin thickness.
本発明によれは、雑音指数に大きな影響を与える入力整
合回路を除いて、各伝送線路の導体厚を表皮効果におけ
る表皮厚さより薄クシているため各整合回路Qが低下し
、回路パラメータの変動が増幅器特性に与える影響を少
くすることができ、そのため増幅器の特性を均一化でき
、回路トリミングが不要となる特徴を有する。この特徴
はモノリシックマイクロ波増幅器の大量生産手段に用い
られるので大きな効果をもつ。According to the present invention, the conductor thickness of each transmission line is thinner than the skin thickness in the skin effect, except for the input matching circuit, which has a large effect on the noise figure, so the Q of each matching circuit decreases, causing fluctuations in circuit parameters. It is possible to reduce the influence of the noise on the amplifier characteristics, thereby making the characteristics of the amplifier uniform, and eliminating the need for circuit trimming. This feature has a great effect since it is used as a means of mass production of monolithic microwave amplifiers.
以下本発明を図TK+によシ詳細に説明する。The present invention will be explained in detail below with reference to Figure TK+.
第1図は本発明の実施例の平面図であり、斜線部には金
メッキが施されている。また、第4図は第1図の等価回
路図を示している。この実施例は二段のFETを含むマ
イクロ波モノリシック増幅器で、初段のFETはゲート
を極1、ソース電極2およびドレイン電極3を有し、二
段目のFETはゲート電極4、ソース電極5およびドレ
イン電極を有し、入力整合回路2段間整合回路および出
力整合回路と共に半絶縁性GaAs基板31上に設けら
れている。これら整合回路の線路上にはそれぞれ誘電体
11,12,16,19,24.26を設け、これらの
上にそれぞれ金メッキして上部電極を形成する?ことに
より、それぞれキャパシタ9,13,15.20,27
.28を形成している。FIG. 1 is a plan view of an embodiment of the present invention, in which the shaded areas are plated with gold. Further, FIG. 4 shows an equivalent circuit diagram of FIG. 1. This embodiment is a microwave monolithic amplifier including two stages of FETs, the first stage FET has a gate pole 1, a source electrode 2 and a drain electrode 3, and the second stage FET has a gate electrode 4, a source electrode 5 and a drain electrode 3. It has a drain electrode, and is provided on a semi-insulating GaAs substrate 31 together with an input matching circuit, a two-stage matching circuit, and an output matching circuit. Dielectrics 11, 12, 16, 19, 24, 26 are provided on the lines of these matching circuits, respectively, and upper electrodes are formed by plating gold on these, respectively. Therefore, capacitors 9, 13, 15, 20, 27, respectively
.. It forms 28.
第1図において、半絶縁性GaAs基板31上に構成さ
れた初段FETのゲート電極1と増幅器の入力端子とな
るDCブロックキャパシタ9の上部電極との間には、先
端にRFバイパスキャパシタ13を備えた並列伝送線路
8および直列伝送線路7からなる入力整合回路が設けら
れている。このFETのドレイン電極3と第2段FET
のゲート霜、極4との間には、直列伝送線路18と先端
にRFバイパス用キャパシタ15を備えた並列伝送線路
17とからなる段間整合回路が設けられ、ドレイン電極
3とゲート電極4に接続されているバッド21との間を
直流的に分離するためのDCブロックキャパシタ20と
が設けられている。このパッド21とゲートバイアス給
電用ポンディングパッド42との間には抵抗層41が設
けられている。In FIG. 1, an RF bypass capacitor 13 is provided at the tip between the gate electrode 1 of the first-stage FET configured on a semi-insulating GaAs substrate 31 and the upper electrode of a DC block capacitor 9 that serves as the input terminal of the amplifier. An input matching circuit consisting of a parallel transmission line 8 and a series transmission line 7 is provided. The drain electrode 3 of this FET and the second stage FET
An interstage matching circuit consisting of a series transmission line 18 and a parallel transmission line 17 equipped with an RF bypass capacitor 15 at the tip is provided between the gate electrode 3 and the gate electrode 4. A DC block capacitor 20 is provided for DC isolation from the connected pad 21. A resistive layer 41 is provided between this pad 21 and a gate bias power supply bonding pad 42.
さらに、第2段FETのドレイン電極6と出力端子を構
成するDCブロックキャパシタ27の上部電極との間に
は、直列伝送線路22および先端にR,Fバイパスキャ
パシタ28を備えた並列伝送線路23からなる出力整合
回路が設けられている。Further, between the drain electrode 6 of the second stage FET and the upper electrode of the DC block capacitor 27 constituting the output terminal, a series transmission line 22 and a parallel transmission line 23 having R and F bypass capacitors 28 at the tips are connected. An output matching circuit is provided.
この実施例における他の回路との接続は、金メッキされ
たポンディングパッドを介して入出力端子や多層配線層
のうちの一つの配線層に接続される。すなわち、入出力
端であるキャパシタ9,27の各上部電極はポンディン
グパッドとして信号ノ入出力端子に接続され、またFE
Tの各ソース電極2,5と各ドレイン電極3,6とはF
ET自体の寄生抵抗を減らすための金メッキが施されお
シ、これらソース電%i2.5と接続される各ポンディ
ングパッド29.30は接地の配線層にそれぞれ接続さ
れる。また、ポンディングパッド14.25も他の配線
層と接続されるものである。Connections with other circuits in this embodiment are made via gold-plated bonding pads to input/output terminals and one wiring layer of the multilayer wiring layer. That is, the upper electrodes of the capacitors 9 and 27, which are input/output terminals, are connected to the signal input/output terminals as bonding pads, and the FE
Each source electrode 2, 5 and each drain electrode 3, 6 of F
Gold plating is applied to reduce the parasitic resistance of the ET itself, and each of the bonding pads 29 and 30 connected to the source voltage %i2.5 is connected to a ground wiring layer. Furthermore, the bonding pads 14 and 25 are also connected to other wiring layers.
第2図、第3図は本発明の詳細な説明する第1図におけ
る入力整合回路および股間整合回路の線路の各断面図で
ある。図中、31は半絶縁性GaAs基板、32は裏面
電極、33は2〜3μmの厚さの金メッキ層、34は金
メッキに必要な給電金属、35 、36は基板31上に
蒸着により形成された02〜0.3μmの厚さの金属導
体である。2 and 3 are cross-sectional views of the lines of the input matching circuit and the crotch matching circuit in FIG. 1, which explain the present invention in detail. In the figure, 31 is a semi-insulating GaAs substrate, 32 is a back electrode, 33 is a gold plating layer with a thickness of 2 to 3 μm, 34 is a power supply metal necessary for gold plating, and 35 and 36 are formed on the substrate 31 by vapor deposition. It is a metal conductor with a thickness of 0.02 to 0.3 μm.
一般に、高周波電流は表皮効果によ多導体の表面のみに
流れ、この電流の流れる表面層の厚さδは、表皮厚さと
呼ばれ、金属の導電率をσ、透磁率をμ1周波数fとす
ると次式で表わされる。Generally, high-frequency current flows only on the surface of a multi-conductor due to the skin effect, and the thickness δ of the surface layer through which this current flows is called the skin thickness.If the electrical conductivity of the metal is σ, the magnetic permeability is μ1, and the frequency f is It is expressed by the following formula.
金の場合の表皮厚さはIQGHzで0.8μm程度であ
る。The skin thickness in the case of gold is about 0.8 μm at IQGHz.
本実施例において、入力整合回路の線路は第2図に示す
ように金メッキ層33の厚さを、この表皮厚さより厚く
しているが、その他の整合回路の線路は、第3図に示す
ように金属薄膜36の厚さを表皮厚さより薄くしている
。このため導体幅および金属の種類にもよるが、段面お
よび出力整合回路の線路の直列抵抗を入力整合回路の線
路の直列抵抗よ勺大きくすることが可能であり、入力整
合回路のQよシ段間および出力整合回路のQを低くする
ことができる。このQの低くした整合回路は広帯域性を
有するため、回路パラメータの変動が増幅器特性に与え
る影響を押えることができる。In this embodiment, the input matching circuit line has a gold plating layer 33 thicker than the skin thickness as shown in FIG. 2, but the other matching circuit lines are as shown in FIG. 3. The thickness of the metal thin film 36 is made thinner than the skin thickness. Therefore, although it depends on the conductor width and the type of metal, it is possible to make the series resistance of the stage plane and the line of the output matching circuit much larger than that of the line of the input matching circuit, and the Q of the input matching circuit can be made larger. The Q of the interstage and output matching circuits can be lowered. Since this matching circuit with a low Q has broadband characteristics, it is possible to suppress the influence of fluctuations in circuit parameters on amplifier characteristics.
一方、雑音特性に影響を与え易い入力整合回路は、表皮
厚さより厚い導体金属を有するため直列抵抗が小さく低
雑音特性を保つことが出来る。この増幅器の増幅帯域は
主としてQが比較的高い入力回路によってのみ決まり、
すなわち増幅特性の変動は主として入力回路のパラメー
タ変動のみによって定まるといえる。On the other hand, since the input matching circuit, which tends to affect the noise characteristics, has a conductive metal thicker than the skin thickness, the series resistance is small and low noise characteristics can be maintained. The amplification band of this amplifier is mainly determined only by the relatively high Q input circuit,
In other words, it can be said that fluctuations in the amplification characteristics are mainly determined only by parameter fluctuations of the input circuit.
このように本発明においては、雑音指数に大きな影舎を
与える入力整合回路を除いて線路の導体厚を表皮厚さよ
シ薄くしているので、回路Qが低下し、回路パラメータ
の変動が増幅器特性に与える影響を少くすることができ
る。このため増幅器の特性を均一化でき回路トリミング
が年少となる特徴を有し、特にモノリシックマイクロ波
増幅器における同一回路の大量生産が可能となシ大きな
効果をもつものである。In this way, in the present invention, the conductor thickness of the line is made thinner than the skin thickness, except for the input matching circuit, which has a large effect on the noise figure, so the circuit Q is lowered, and fluctuations in circuit parameters are affected by amplifier characteristics. It is possible to reduce the impact on As a result, the characteristics of the amplifier can be made uniform and the circuit trimming can be reduced, which is particularly effective in making it possible to mass-produce identical circuits in monolithic microwave amplifiers.
なお、本発明の実施例は2段構成の増幅器で説明したが
、増幅器の段数は2段に限らず何段でもよい。また半導
体基板としてはGaAsに限らずInP、8iでもよい
。Although the embodiment of the present invention has been described using a two-stage amplifier, the number of amplifier stages is not limited to two and may be any number of stages. Furthermore, the semiconductor substrate is not limited to GaAs, but may also be InP or 8i.
第1図は本発明の一実施例の増幅器の平面図、第2図、
第3図は第1図整合回路部分のA−AおよびB−B断面
図、第4図は第1図の等価回路である。図において
1.4・・・・・・ゲート電極、2,5・・・・・・ソ
ース電極3.6・・・・・・ドレイン電極s 7,8
,17,18,22゜23・・・・・・伝送線路、9,
13,15,20,27.28・・・・・・キャパシタ
ンス、11,12.16,19.24.26・・・・・
・誘電体、14,25,29.30・・・・・・ポンデ
ィングパッド(金メッキ)、21・・・・・・パッド、
31・・・・・・半絶縁性基板、32・・・・・・裏面
電極、33・・・・・・金メッキ層、34・・・・・・
給電金属、35.36・・・・・・金属導体、41・・
・・・・抵抗層、42・・・・・・ポンディングパッド
である。FIG. 1 is a plan view of an amplifier according to an embodiment of the present invention, FIG.
3 is a sectional view taken along line AA and BB of the matching circuit portion shown in FIG. 1, and FIG. 4 is an equivalent circuit of FIG. 1. In the figure, 1.4...gate electrode, 2,5...source electrode 3.6...drain electrode s7,8
,17,18,22゜23...transmission line, 9,
13, 15, 20, 27.28... Capacitance, 11, 12.16, 19.24.26...
・Dielectric, 14, 25, 29.30...Ponding pad (gold plating), 21...Pad,
31... Semi-insulating substrate, 32... Back electrode, 33... Gold plating layer, 34...
Power supply metal, 35.36...Metal conductor, 41...
. . . Resistance layer, 42 . . . Bonding pad.
Claims (1)
類以上の回路素子からなる入力整合回路。 段間整合回路および出力整合回路を備えたマイクロ波モ
ノリシックN幅器において、前記入力整合回路の伝送線
路の導体厚を表皮効果における高周波電流の流れる表皮
厚さより厚<シ、前記段間および出力整合回路の伝送線
路の導体厚を前記表皮厚さより薄くしたことを特徴とす
るマイクロ波モノリシック増幅器。[Claims:] An input matching circuit comprising one or more circuit elements of a distributed constant line, an inductor, and a capacitor. In a microwave monolithic N-width amplifier equipped with an inter-stage matching circuit and an output matching circuit, the conductor thickness of the transmission line of the input matching circuit is set to be less than the skin thickness through which a high-frequency current flows due to the skin effect, and the inter-stage and output matching circuits are A microwave monolithic amplifier characterized in that the conductor thickness of the transmission line of the circuit is made thinner than the skin thickness.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58005692A JPS59131208A (en) | 1983-01-17 | 1983-01-17 | Microwave monolithic amplifier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58005692A JPS59131208A (en) | 1983-01-17 | 1983-01-17 | Microwave monolithic amplifier |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59131208A true JPS59131208A (en) | 1984-07-28 |
JPH0218603B2 JPH0218603B2 (en) | 1990-04-26 |
Family
ID=11618149
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58005692A Granted JPS59131208A (en) | 1983-01-17 | 1983-01-17 | Microwave monolithic amplifier |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59131208A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997033335A1 (en) * | 1996-03-06 | 1997-09-12 | Central Research Laboratories Limited | Apparatus for blocking a d.c. component of a signal |
US6504189B1 (en) | 1998-07-21 | 2003-01-07 | Fujitsu Quantum Devices Limited | Semiconductor device having a microstrip line |
JP2016058920A (en) * | 2014-09-10 | 2016-04-21 | 住友電気工業株式会社 | Travelling wave amplifier |
-
1983
- 1983-01-17 JP JP58005692A patent/JPS59131208A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1997033335A1 (en) * | 1996-03-06 | 1997-09-12 | Central Research Laboratories Limited | Apparatus for blocking a d.c. component of a signal |
US6046898A (en) * | 1996-03-06 | 2000-04-04 | Central Research Laboratories Limited | Apparatus for blocking a D.C. component of a signal |
US6504189B1 (en) | 1998-07-21 | 2003-01-07 | Fujitsu Quantum Devices Limited | Semiconductor device having a microstrip line |
JP2016058920A (en) * | 2014-09-10 | 2016-04-21 | 住友電気工業株式会社 | Travelling wave amplifier |
Also Published As
Publication number | Publication date |
---|---|
JPH0218603B2 (en) | 1990-04-26 |
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