JPH0457124B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monolithic integrated circuit amplifier;
It particularly concerns monolithic integrated circuit amplifiers in the microwave band.

Conventionally, a microwave band integrated circuit amplifier has been constructed of a single active element and an external matching circuit using a capacitive or inductive stub. On the other hand, a monolithic integrated circuit amplification base that uses lumped constant elements such as capacitors or inductors in the matching circuit and integrates the matching circuit and active elements on a semiconductor substrate is being considered, which is small, lightweight, and can be mass-produced. It's coming. An example of an X-band monolithic integrated circuit amplifier using a gallium arsenide field effect transistor as an active element will be described below.

Conventionally, as shown in FIG. 1, a matching circuit for this monolithic amplifier has traditionally included lumped constant inductances 13, 16, which are connected in series from a gate input terminal 12 and a drain output terminal 15 of a field effect transistor (hereinafter referred to as FET) 11, as shown in FIG. Next, a circuit configuration was used in which lumped constant inductances 14 and 17 were connected in parallel to match the characteristic impedance of 50Ω.

FIG. 2 is a Smith chart showing the matching path of the matching circuit shown in FIG.

From points A and C, which represent the input and output impedance of the FET, move from point A to point B on the constant resistance circle, and from point C to D.
Move to point (series inductance 13, 16), then move from point B to point O on the constant conductance circle, and from point D to point O
(parallel inductances 14 and 17) to match the characteristic impedance of 50Ω. Note that 20 and 21 in FIG. 1 are input/output bias feed capacitances.

In the case of a monolithic amplifier with such a matching circuit configuration, as an actual microwave circuit,
It is necessary to insert capacitances 18 and 19 between the input/output 50Ω terminal and the matching circuit to block direct current. The value of this capacitance must be sufficiently lower than the input/output impedance of 50Ω, and the voltage standing wave (hereinafter referred to as VSWR) must be as close to 1 as possible. More specifically, in the case of VSWR < 1.2, the capacitive impedance must be 9Ω or less, which must be sufficiently low compared to the characteristic impedance of 50Ω, so we will choose 5Ω. Therefore, the capacitive impedance
When the value of _{C is determined at a frequency of 12 GHz from the formula representing X c =} 1/ωc, C = 2.7 pF. Therefore, if a parallel plate type MIM capacitor with a 6000 Å thick SiO ₂ film as a dielectric is used as the capacitor, the electrode dimensions will be 194 µm.
It will be m square. Therefore, a capacitor with a large area of 194 μm□ is required following the matching circuit for both input and output. This is a major disadvantage in that monolithic integrated circuit amplifiers using lumped elements have a small area and can be manufactured in large quantities. Further, FIG. 3 shows calculated values of the gain versus frequency characteristics of an amplifier having a matching circuit configuration as an example here. As shown in FIG. 3, the gain vs. frequency characteristic is a single peak type relatively narrow band characteristic.

FIG. 4 is a circuit diagram of another example of a conventional matching circuit.

A circuit is constructed in which lumped constant matching elements such as parallel inductances 23 and 26 and series capacitances 24 and 27 are connected from the input/output terminals 22 and 25 of the FET 11 to the series capacitances 24 and 27, thereby matching the characteristic impedance to 50Ω.

FIG. 5 is a Smith chart showing the matching path of the matching circuit shown in FIG.

Move from points A' and C', which represent the input and output impedance of the FET, on a constant conductance circle from point A' to point B' and from point C' to point D' (parallel inductance 2
3, 26), then on the constant resistance circle from B' to point O', and
Move from D' to O' point (series capacitance 24,
27) Match the characteristic impedance to 50Ω.
Here, 28 and 29 in FIG. 4 are input/output bias feed capacitances.

In such a circuit configuration, the series capacitance also functions as a DC blocking element together with the matching element. In reality, the value of this capacitance is
0.5 pF and 0.4 pF, and the dimensions of MIM capacitance are 85 μm□ and 76 μm□, respectively, when 6000 Å CVD SiO ₂ is used as a dielectric.
There is no need for a device with a large area as in the example shown in the figure, and the overall size of the amplifier can be reduced. However, the gain versus frequency characteristic (calculated value) of a monolithic amplifier with such a matching circuit configuration is
As shown in the figure, it has a single peak narrow band characteristic,
This was a drawback in terms of performance.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a monolithic integrated circuit amplifier which eliminates the above-mentioned drawbacks, reduces chip area, and has a broadband gain versus frequency characteristic.

The monolithic integrated circuit amplifier of the present invention includes an active element, a first inductance whose one end is connected to the input terminal of the active element, and whose one end is connected to the other end of the first inductance and whose other end is connected to the input terminal. a first capacitance connected to the other end of the first inductance, a third inductance connected to the other end of the first capacitance, and one end connected to the output terminal of the active element. a fourth inductance connected to the fourth inductance; a second capacitance having one end connected to the other end of the fourth inductance and the other end connected to the output terminal; and a fifth capacitance having one end connected to the other end of the fourth inductance. and a sixth inductance, one end of which is connected to the other end of the second capacitance.

Next, embodiments of the present invention will be described using the drawings.

FIG. 7 is a circuit diagram of an embodiment of the present invention.

This embodiment includes an active element 31, a first inductance 33 whose one end is connected to the input terminal of the active element 31, and whose one end is connected to the other end of the first inductance and whose other end is connected to the input terminal. a first capacitance 35 and a first inductance 3
A second inductance 34 connected to the other end of 5
, a third inductance 36 connected to the other end of the first capacitance 35, and a fourth inductance 3 whose one end is connected to the output terminal of the active element 31.
8, a second capacitance 40 whose one end is connected to the other end of the fourth inductance 38 and whose other end is connected to the output terminal, and a fifth inductance 39 whose one end is connected to the other end of the fourth inductance 38. ,
and a matching circuit consisting of a sixth inductance 41 whose one end is connected to the other end of the second capacitance 40. Capacitance 42,4
3 is for input and output bias feeds.
For example, a GaAs field effect transistor is used as the active element. If a monolithic integrated circuit amplifier including such a matching circuit is fabricated, a broadband amplifier in the microwave band can be obtained. The microwave band below is 12GHz
It will be explained as a belt.

FIG. 8 is a Smith chart showing the matching path of the embodiment shown in FIG.

Connect an inductance 33 in series from the gate input terminal 32 (point A) of the FET 31 (from point A to point B),
Furthermore, connect inductance 34 in parallel (B→C
(to point C), choose the maximum flatness, that is, the impedance at point C is √ ₍₃₃₎ The input impedance of the FET is changed in a two-stage configuration (from point D to point O).
Match to 50Ω. Capacitance 34 at this time
The size is 0.4pF and it was deposited by CVD method.
The dimensions of a MIM capacitor using an approximately 6000 Å SiO ₂ film as an interlayer insulating film are 76 μm□. Similarly, on the output side, the drain output terminal 37 of FET 31 (point E)
The same configuration (E→F→G→
(from H to O point), set the FET output impedance to 50Ω.
be consistent. The size of the capacitance at this time is 0.6pF, and the size of the MIM capacitor is 93μm.
It is □.

9 is a plan view of a semiconductor chip in which the matching circuit shown in FIG. 1 is arranged, and FIG. 10 is a plan view of a semiconductor chip in which the embodiment shown in FIG. 7 is arranged.

The chip size of the conventional product shown in Figure 9 is 1150μm.
900 μm, whereas the chip size of the embodiment of the present invention shown in FIG. 10 is 950 μm×900 μm, which is a shortened lengthwise dimension.

FIG. 11 is a characteristic curve diagram of the gain versus frequency characteristic (calculated value) of the embodiment shown in FIG. 7.

As shown in the figure, almost flat broad band characteristics from 11 GHz to 13 GHz are obtained. Figure 7 and 1
Since the series capacitances 35 and 40 shown in FIG. 0 function not only as matching elements but also as direct current blocking, there is no need for capacitances with a large area as in the conventional case.

As mentioned above, by providing a series capacitance as a matching circuit element, a capacitance with a large area as in the past is not required since it also functions as a DC blocker, and the overall chip size can therefore be reduced. This is very effective in realizing miniaturization and mass production, which are the objectives of monolithic integrated circuits.

Furthermore, the matching circuit configuration of the present invention allows a wide gain versus frequency characteristic to be obtained, which is a great advantage in terms of performance improvement.

Furthermore, according to the present invention, only the configuration of the matching circuit elements is changed, and basically the same lumped constant inductor and capacitor as before are used. Therefore, only by changing a part of the mask, It does not change the manufacturing process and has the advantage of being extremely easy to implement.

Although the embodiments of the present invention have been described using GaAs MESFETs, it goes without saying that the present invention can be similarly applied to InP.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an example of a conventional matching circuit, and Figure 2 is a circuit diagram of an example of a conventional matching circuit.
The figure is a Smith chart showing the matching path of the matching circuit shown in Fig. 1, Fig. 3 is a gain versus frequency characteristic diagram of the matching circuit shown in Fig. 1, and Fig. 4 is a circuit diagram of another example of the conventional matching circuit. , FIG. 5 is a Smith Chart showing the matching path of the matching circuit shown in FIG. 3, FIG. 6 is a gain versus frequency characteristic diagram of the matching circuit shown in FIG. 4, and FIG. 7 is a circuit of an embodiment of the present invention. 8 is a Smith chart showing the matching path of one embodiment shown in FIG. 7, FIG. 9 is a plan view of a semiconductor chip in which the matching circuit shown in FIG. 1 is arranged, and FIG. 10 is the same as that shown in FIG. FIG. 11 is a plan view of a semiconductor chip in which the embodiment shown is arranged, and FIG. 11 is a gain versus frequency characteristic diagram of the embodiment shown in FIG. 11...FET, 12...Input end, 13, 14
...Inductance, 15...Output end, 16,1
7...Inductance, 18, 19, 20, 21
... Capacitance, 22 ... Input end, 23 ...
Inductance, 24... Capacitance, 25
...Output end, 26...Inductance, 27,2
8, 29...Capacitance, 31...FET,
32... Input end, 33, 34... Inductance, 35... Capacitance, 36... Inductance, 37... Output end, 38, 39... Inductance, 40... Capacitance, 41... Inductance, 42, 43... ...capacitance.

Claims (1)

[Claims] 1 an active element, a first inductance having one end connected to an input terminal of the active element, a first capacitance having one end connected to the other end of the first inductance and the other end connected to the input terminal; 1st
a second inductance connected to the other end of the inductance; a third inductance connected to the other end of the first capacitance; a fourth inductance, one end of which is connected to the output terminal of the active element; a second capacitance connected to the other end of the fourth inductance and having the other end connected to the output terminal; a fifth inductance having one end connected to the other end of the fourth inductance;
and a sixth inductance having one end connected to the other end of the capacitance of the monolithic integrated circuit amplifier.