JPS59131163U - 半導体容器 - Google Patents
半導体容器Info
- Publication number
- JPS59131163U JPS59131163U JP1983025463U JP2546383U JPS59131163U JP S59131163 U JPS59131163 U JP S59131163U JP 1983025463 U JP1983025463 U JP 1983025463U JP 2546383 U JP2546383 U JP 2546383U JP S59131163 U JPS59131163 U JP S59131163U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor container
- metal
- semiconductor
- container
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第1図A、 B、 C,D図は従来構造の断面図、第2
図A、 B、 C図は本考案の断面図である。 1.11・・・セラミック、2.12・・・モリブデン
金属、3,13・・・IC素子、4.14・・・外部り
−ドピン、5.15・・・キャップ、6.16・・・F
e −Ni系合金板、7・・・メタライズ。
図A、 B、 C図は本考案の断面図である。 1.11・・・セラミック、2.12・・・モリブデン
金属、3,13・・・IC素子、4.14・・・外部り
−ドピン、5.15・・・キャップ、6.16・・・F
e −Ni系合金板、7・・・メタライズ。
Claims (3)
- (1)集積回路素子を収納する半導体容器において、そ
の集積回路素子の取り付は部に熱伝導性に優れた金属を
使用し、該金属と容器間に異種金属を介在させて取り付
けたことを特徴とする半導体容器。 - (2)熱伝導性に優れた金属とは、モリブデン、タング
ステン又はそれらの合金等である実用新案登録請求の範
囲第1項記載の半導体容器。 - (3)介在させる異種金属は、Fe −Ni系合金又は
無酸素銅等である実用新案登録請求の範囲第1項記載の
半導体容器。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983025463U JPS59131163U (ja) | 1983-02-23 | 1983-02-23 | 半導体容器 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1983025463U JPS59131163U (ja) | 1983-02-23 | 1983-02-23 | 半導体容器 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59131163U true JPS59131163U (ja) | 1984-09-03 |
JPS6331394Y2 JPS6331394Y2 (ja) | 1988-08-22 |
Family
ID=30156448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1983025463U Granted JPS59131163U (ja) | 1983-02-23 | 1983-02-23 | 半導体容器 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59131163U (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62199038A (ja) * | 1986-02-27 | 1987-09-02 | Hitachi Ltd | 半導体パツケ−ジ構造体 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5310273U (ja) * | 1976-07-09 | 1978-01-27 | ||
JPS5317072A (en) * | 1976-07-30 | 1978-02-16 | Nec Corp | Package for semiconductor device |
JPS5461472A (en) * | 1977-10-26 | 1979-05-17 | Hitachi Ltd | Package for semiconductor element |
-
1983
- 1983-02-23 JP JP1983025463U patent/JPS59131163U/ja active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5310273U (ja) * | 1976-07-09 | 1978-01-27 | ||
JPS5317072A (en) * | 1976-07-30 | 1978-02-16 | Nec Corp | Package for semiconductor device |
JPS5461472A (en) * | 1977-10-26 | 1979-05-17 | Hitachi Ltd | Package for semiconductor element |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62199038A (ja) * | 1986-02-27 | 1987-09-02 | Hitachi Ltd | 半導体パツケ−ジ構造体 |
Also Published As
Publication number | Publication date |
---|---|
JPS6331394Y2 (ja) | 1988-08-22 |
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