JPS59130292U - system controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the mutual relationship among the processing unit, main memory, and system control unit; FIG. 2-A is a diagram showing the format of commands sent from the processing unit to the system control unit and the meaning of each bit; FIG. 2-B is a diagram showing a specific example of the command, FIG. 3 is a diagram showing an embodiment of the system control device according to the present invention, and FIG. 4 is a diagram showing the central directory shown in FIG. 3 and its peripheral circuits. It is a diagram. 1...System control unit (abbreviated as 5CU), 2.
and 3...Central processing unit (abbreviation cpu), 4.
...Channel device (abbreviation CH), 5 and 6...
...Main memory (abbreviation MM), 7...Central directory (abbreviation CD), 8 and 9...Buffer memory means (abbreviation BM), 10...Request Control circuit, 11...Reply control circuit.

Claims (1)

[Scope of utility model registration request] a plurality of processing units, at least one of which includes buffer memory means controlled in a swap manner, and a main memory, each of the plurality of processing units being not independently accessible; A system control device that controls the main memory and the buffer memory in response to a read request from any one of the processing devices, the system control device being provided corresponding to a plurality of blocks included in the buffer memory means. , write state storage means for storing whether or not writing has occurred in this block, and data indicated by the address information sent from the processing device that is the source of the read request is stored in the buffer memory means of the processing device that is not the source of the read request. scanty write detection means that outputs a write detection signal in response to a read request when the write status storage means has been written and the write status storage means has written, and the write detection means outputs a write detection signal in response to a read request; reading means for reading out the data indicated by the address information from the buffer memory means of the processing device that is not the read request when the write detection signal is output; and reading the data read by the reading means into the main memory A system control device comprising: sending means for sending the read request source processing device to the processing device without sending the read request source to the processing device.