JPS59127431A - デジタルチユ−ナ用pll装置 - Google Patents
デジタルチユ−ナ用pll装置Info
- Publication number
- JPS59127431A JPS59127431A JP301383A JP301383A JPS59127431A JP S59127431 A JPS59127431 A JP S59127431A JP 301383 A JP301383 A JP 301383A JP 301383 A JP301383 A JP 301383A JP S59127431 A JPS59127431 A JP S59127431A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pll
- integrated circuit
- digital tuner
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
- H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
- H03J5/0245—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
- H03J5/0272—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Circuits Of Receivers In General (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP301383A JPS59127431A (ja) | 1983-01-12 | 1983-01-12 | デジタルチユ−ナ用pll装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP301383A JPS59127431A (ja) | 1983-01-12 | 1983-01-12 | デジタルチユ−ナ用pll装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59127431A true JPS59127431A (ja) | 1984-07-23 |
| JPH0124449B2 JPH0124449B2 (enrdf_load_stackoverflow) | 1989-05-11 |
Family
ID=11545451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP301383A Granted JPS59127431A (ja) | 1983-01-12 | 1983-01-12 | デジタルチユ−ナ用pll装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59127431A (enrdf_load_stackoverflow) |
-
1983
- 1983-01-12 JP JP301383A patent/JPS59127431A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0124449B2 (enrdf_load_stackoverflow) | 1989-05-11 |
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