JPS59124170A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59124170A JPS59124170A JP23370382A JP23370382A JPS59124170A JP S59124170 A JPS59124170 A JP S59124170A JP 23370382 A JP23370382 A JP 23370382A JP 23370382 A JP23370382 A JP 23370382A JP S59124170 A JPS59124170 A JP S59124170A
- Authority
- JP
- Japan
- Prior art keywords
- gaas
- layer
- algaas
- ions
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 21
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- -1 oxygen ions Chemical class 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 6
- 230000004913 activation Effects 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000009826 distribution Methods 0.000 abstract description 10
- 150000002500 ions Chemical class 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 7
- 230000002779 inactivation Effects 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 2
- 238000005546 reactive sputtering Methods 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
- 229910052711 selenium Inorganic materials 0.000 description 8
- 239000011669 selenium Substances 0.000 description 8
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 230000007423 decrease Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 101150106726 Cnr2 gene Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は高抵抗のＡｌＧａＡｓ層を形成する半導体装置
の製造方法に関し、更に詳しくはＧａＡＳ−へ１ｅａ八
８２層構造のＧａＡ３面から■族元素と酸素全イオン注
入し、熱処理を行なうことによって高抵抗のに狐ａＡａ
層を得る、半導体装置、特にＧａ Ａｓ電界効果トラン
ジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device forming a high-resistance AlGaAs layer, and more specifically to a method for manufacturing a semiconductor device in which a high-resistance AlGaAs layer is formed. By implanting all ions of oxygen and heat treatment, a high-resistance aAa
The present invention relates to a method for manufacturing semiconductor devices, in particular GaAs field effect transistors, in which layers are obtained.
（２）技術の背景及び従来技術の問題点高周波のパワー
素子としてＧａ八へ ＦｆＣＴが広く用いられており
、その高周波特性が、活性層として用いられるチャンネ
ル層を成長させる前に成長されるバッファ層自体の、あ
るいはバッファ層−とチャンネル層界面の性質により左
右されることは良く知られている。パワーＦＢｌｉＴ用
のバッファ層としては特に高抵抗が要求される。また、
チャンネル層のドーピング・プロファイルとしてはより
急峻な濃度分布をもったものが有利とされている。(2) Background of the technology and problems with the conventional technology FfCT is widely used as a high-frequency power device for Ga8, and its high-frequency characteristics are unique to the buffer layer that is grown before growing the channel layer used as the active layer. It is well known that it depends on the properties of the buffer layer itself or the interface between the buffer layer and the channel layer. A particularly high resistance is required as a buffer layer for power FBliT. Also,
It is considered advantageous for the doping profile of the channel layer to have a steeper concentration distribution.
第１図は、従来のショットキーゲート形Ｇａ ＡｓＦＫ
Ｔの断面図で、図中、１は半絶縁性ＧａＡ３基板、２は
アンドープの（）ａＡｓＡｓバラフッ３はｎ型Ｇａ Ａ
ｓ活性層、４と５はソースまたはドレイ／電極、６はシ
ョットキーゲートである。Figure 1 shows a conventional Schottky gate type GaAsFK.
This is a cross-sectional view of T. In the figure, 1 is a semi-insulating GaA3 substrate, 2 is an undoped ()aAsAs substrate, and 3 is an n-type GaA substrate.
s active layer, 4 and 5 are sources or drains/electrodes, and 6 is a Schottky gate.
バッファ層２として、ＧａＡｓよりパンドギャッ −プ
が大きく、高抵抗層が得られ易いＡｌＧａＡｓ を用い
ることが提案されている。このＧａ Ａｓ −ＡｌＧａ
Ａｓ ２層構造に、ｎ型不純物であるシリコンをイオ
ン注入し、アニールする場合には、第２図の如く、ある
範囲の温度では、ＧａＡｓ中でのみ、電気的活性化がお
こるため、より急１唆な濃度分布をもったチャンネル層
の形成が可能となってきている。As the buffer layer 2, it has been proposed to use AlGaAs, which has a larger breadth gap than GaAs and can easily form a high resistance layer. This Ga As -AlGa
When silicon, which is an n-type impurity, is ion-implanted into an As two-layer structure and annealed, electrical activation occurs only in GaAs at a certain temperature range, as shown in Figure 2, so the process becomes more rapid. It has become possible to form a channel layer with a uniform concentration distribution.
第２図中、横軸は深さを示し、縦軸はキャリア濃度を示
す。図中の点線は、１ｏＯＫｅｖのエネルギーでシリコ
ンイオンを注入した場合の注入イオン分布であり、７０
０℃で熱処理したときのキャリア分布は実線にて示しで
ある。ＡｌＧａＡｓ 中で特に、キャリア濃度分布が低
下しているのは、ＡｌＧａＡｓにおける活性化温度がＧ
ａＡｓ中に比べおよそ２００℃高いことに依るものであ
る。In FIG. 2, the horizontal axis indicates depth, and the vertical axis indicates carrier concentration. The dotted line in the figure is the implanted ion distribution when silicon ions are implanted with an energy of 1oOKev, which is 70
The carrier distribution when heat treated at 0° C. is shown by a solid line. Especially in AlGaAs, the carrier concentration distribution decreases because the activation temperature in AlGaAs is G.
This is due to the fact that the temperature is approximately 200°C higher than that in aAs.
このようにＡＩ Ｇａ Ａｓ 中でキャリア濃度’Ｔｈ
１Ｏ”ｃｒｎ−３以ドと極めて低くできるが、ノくワー
Ｆ’ＥｆｉＴとしては充分な高抵抗となっていない。In this way, the carrier concentration 'Th in AI Ga As
Although the resistance can be extremely low as less than 10" crn-3, the resistance is not high enough for a lower F'EfiT.
（３）発明の目的
本発明の目的は、上記ＡｌＧａＡｇ層の抵抗を更に高め
得る方法を提供するものである。更には、Ｇａ Ａｓ
−Ａｌ Ｇａ Ａｓ 二重層におけるＧａＡ３活性層の
キャリア濃度は変えずに、ＡｌＧａＡｓ層の抵抗を更に
高め得るＧａＡｓＦＫＴの製造方法を提供するものであ
る。(3) Purpose of the Invention An object of the present invention is to provide a method for further increasing the resistance of the AlGaAg layer. Furthermore, GaAs
The present invention provides a method for manufacturing GaAsFKT that can further increase the resistance of the AlGaAs layer without changing the carrier concentration of the GaA3 active layer in the -AlGaAs double layer.
（４）発明の構成
上記の目的は、本発明によれば
（イ） ＡｌＧａＡｓ層に■族元素全イオン注入すると
共に、酸素イオンを注入する工程および該注入工程後不
活性化のための熱処理を行なう工程により高抵抗の八１
（）ａＡｓ層を形成すること全特徴とする半導体装置の
製造方法、
（ロ）前記ＡＩ Ｇａ Ａｓ層がＧａＡＳ層によって覆
われ、前記■族元素が該Ｇａ Ａｓ層表面からイオン注
入されることを特徴とす−る前記の半導体装置の製造方
法とすることにより達成される。(4) Structure of the Invention According to the present invention, the above-mentioned object is achieved by (a) implanting all ions of group (I) elements into the AlGaAs layer, as well as a step of implanting oxygen ions and a heat treatment for inactivation after the implantation step; 81 with high resistance depending on the process performed.
(2) A method for manufacturing a semiconductor device characterized in that an aAs layer is formed, (b) the AI GaAs layer is covered with a GaAS layer, and the group (3) element is ion-implanted from the surface of the GaAs layer. This is achieved by the above-described method for manufacturing a semiconductor device.
（５）発明の実施例 以下に図面全参照して本発明の詳細な説明する。(5) Examples of the invention The present invention will be described in detail below with reference to all the drawings.
第３図は、Ｇａ八へ−ＡＩＧａＡｓ２重層を形成した基
板の断面図で、クロム全添加した半絶縁性基板ｌの上に
、分子ビームエピタキシャル法により、アンドープでα
５μｍの厚さにＡｌｘＧａ１−１ Ａｓ （Ｘ ＝α３
）層７を形成し、続いて、アンドープで０．２μｍの厚
さのＧａ Ａｓ層８を連続成長させる。Fig. 3 is a cross-sectional view of a substrate on which a Ga-AIGaAs double layer is formed, and it is undoped with α
AlxGa1-1 As (X = α3
) layer 7 is formed, followed by successive growth of an undoped GaAs layer 8 with a thickness of 0.2 μm.
第３図の構造に対して、■族元素のセレンイオｙｉ ４
００ ＫｅＶのエネルギー、２ Ｘ 、 １０ ” ２
Ｃｎｒ２の密度でイオン注入し、次いで酸素イオンを１
５０ＫｅＶ Ｉ Ｘ １０ ”ｃｍ−２の条件でイオ
ン注入する。For the structure shown in Figure 3, the group ■ element selenium io yi 4
00 KeV energy, 2 X, 10 ” 2
Ion implantation at a density of Cnr2 followed by oxygen ions at 1
Ion implantation is performed under the condition of 50 KeV I x 10''cm-2.
Ｒ記の条件でのセレンイオンのＲｐ （飛程距離）は約
０１５μｍ１酸素イオンのＲｐはα２４μｍである。The Rp (range distance) of selenium ions under the conditions described in R is approximately 015 μm, and the Rp of oxygen ions is α24 μm.
注入イオンの活性化のための熱処理を行なうにあたって
、ＧａＡＢ層８の表面を反応スパッタ法によって０１μ
ｍのＡＱＮ膜で被覆し、この状態で８００℃、２０分の
熱処理を行なう。When performing heat treatment for activating the implanted ions, the surface of the GaAB layer 8 is coated with 01 μm by reactive sputtering.
It is coated with an AQN film of 100 m thick, and in this state, heat treatment is performed at 800° C. for 20 minutes.
この結＋ｉ第４図に示す。横軸は深さであり、縦軸に＃
度を示す。点綴はセレンのイオン分布であり、実線がキ
ャリア分布である。ＡｌＧａＡｓ中でキャリア分布が急
激に減少していることがわかる。This result is shown in FIG. The horizontal axis is depth and the vertical axis is #
Show degree. The dotted line is the selenium ion distribution, and the solid line is the carrier distribution. It can be seen that the carrier distribution in AlGaAs decreases rapidly.
この／ｑＧａＡ８層の抵抗は周知のＣ−Ｖ法で測定した
が、比抵抗として１０６Ω・ｍ以上のものであった。The resistance of this /qGaA8 layer was measured by the well-known CV method, and the specific resistance was 106 Ω·m or more.
尚、■族元素として、セレンの他イオウ、テルル等があ
り、同様に実施できる。Incidentally, in addition to selenium, sulfur, tellurium, and the like can be used as group (Ⅰ) elements, and the same method can be used.
ところで、前記のセレン注入に代えてシリコンイオンを
注入した場合には、注入酸素イオンによる不活性化が檄
しく、Ｎ型としてのキャリア濃度は低下するかもしくは
Ｎ型が得られない場合があり、ＧａＡｓ中でのドーピン
グ教の制御が困難であるのに対し、■族ドナー不純物で
は酸素注入による不活性化がＧａＡｓ中ではみとめられ
ていない。By the way, when silicon ions are implanted instead of the selenium implantation described above, inactivation by the implanted oxygen ions is a problem, and the N-type carrier concentration may decrease or the N-type may not be obtained. While it is difficult to control the doping behavior in GaAs, inactivation of group III donor impurities by oxygen implantation has not been observed in GaAs.
このため、ＧａＡＳ中のドーピングはセレン注入のみで
制御され、かつ、ＡｌＧａＡｓ中では酸素原子の導入す
る深いレベルのために高抵抗層が形成される０
上記の実施例においてＡｌ（）ａＡｓのＸ値はα３とし
たが、このＸ値は０２〜α４の範囲で変えることができ
、注入後の熱処理温度は６２５〜８５０℃の範囲で変え
ることができる。Therefore, the doping in GaAS is controlled only by selenium implantation, and in AlGaAs, a high resistance layer is formed due to the deep level of oxygen atoms introduced. is α3, but this X value can be changed in the range of 02 to α4, and the heat treatment temperature after injection can be changed in the range of 625 to 850°C.
ＧａＡｓ１Ｔ［ｎＴの製作にあたっては、コンタクト抵
抗減少のためソース、ドレイン電極の形成すべきＧａ
Ａｓ部分に■族元素を高濃度に注入する工程全付加する
のがよく、セレン注入の場合は、例えば５０ ＫｅＶで
１〜３Ｘ１０１３ｃｒ１ｒ２のイオンを行なう。When manufacturing GaAs1T[nT, the source and drain electrodes are formed using GaAs to reduce contact resistance.
It is preferable to add a complete step of implanting group (I) elements at a high concentration into the As portion. In the case of selenium implantation, ions of 1 to 3×10 13 cr 1 r 2 are implanted at 50 KeV, for example.
（６）発明の効果
本発明ではＡＩ Ｇａ Ａｓ層に■族元素と酸素を注入
し、熱処理を行なうことにより、ＡｌＧａＡｓ層中で活
性化する■族元素は酸素によって不活性化させることが
でき、高抵抗を保つことができる。更に、このイオン注
入はＧａＡｓＦＢ’ｌ”における様なＧａ Ａｓ −Ａ
ＩＧａ Ａｓ二重構造に対してなせば、酸素はＧａＡｓ
中では不活性化の働きをしないので、ＧａＡｓ中のキャ
リア濃度は■族元素のみで制御できると共に、ＡＩ Ｇ
ａ Ａｓは高抵抗となし得るので好都合であり、ノイズ
の影響のない高周波パワー素子が実現できる。(6) Effects of the Invention In the present invention, by injecting group Ⅰ elements and oxygen into the AI GaAs layer and performing heat treatment, the group Ⅰ elements activated in the AlGaAs layer can be inactivated by oxygen. Can maintain high resistance. Furthermore, this ion implantation can be applied to GaAs-A as in GaAsFB'l''.
When applied to the IGaAs double structure, oxygen
Since the carrier concentration in GaAs does not act as inactivation, it is possible to control the carrier concentration in GaAs only by using group III elements.
aAs is advantageous because it can have a high resistance, and a high frequency power device without the influence of noise can be realized.
第１図は従来のショットキーゲート形ＧａＡＳＦＥＬＴ
の断面図、第２図は従来提案されているＧａＡｓ −Ａ
’ｌＧａ Ａｓ構造にシリコンイオン全注入しアニール
したときの濃度分布金示す図、第３図は本発明の実施に
用いたＧａ Ａｓ ７ ＡＩ Ｇａ Ａｓ構造の断面図
、第４図は第３図の構造にセレンと酸素を共にイオン注
入し、アニールしたときの濃度分布を示す図である。
図中、ｌは半絶縁性基板、７はＡＩ Ｇａ Ａｓ層、８
はＧａ Ａｓ層である。
第 １ 図
０．２０．４ノ１
１蚤さ
第２口
第３ 図
θ、２ ０７１ｍ
、＋＠ さ
第４ 図Figure 1 shows a conventional Schottky gate type GaASFELT.
Figure 2 is a cross-sectional view of the conventionally proposed GaAs-A
Figure 3 is a cross-sectional view of the GaAs 7 AI GaAs structure used in the implementation of the present invention, and Figure 4 is the same as that of Figure 3. FIG. 3 is a diagram showing the concentration distribution when both selenium and oxygen are ion-implanted into a structure and annealed. In the figure, l is a semi-insulating substrate, 7 is an AI Ga As layer, and 8 is a semi-insulating substrate.
is a GaAs layer. 1st Figure 0.20.4 No. 1 1 Flea 2nd mouth 3rd figure θ, 2 071m, +@sa Figure 4
Claims (2)
ると共に、酸素イオン金注入する工程および該注入工程
後年活性化のための熱処理を行なう工程により高抵抗の
ＡＩ ＧａｋＳ層を形成することを特徴とする半導体装
置の製造方法。(1) A high-resistance AI GakS layer is formed by ion-implanting a group III element into the A1GaA43 layer, implanting oxygen ions with gold, and performing heat treatment for activation after the implantation step. A method for manufacturing a semiconductor device.
れ、前記■族元素が該Ｇａ Ａｓ層表面からイオン注入
されることを特徴とする特許請求の範囲第（１）項記載
の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim (1), characterized in that the AlGaAs layer is covered with a GaAs layer, and the Group Ⅰ element is ion-implanted from the surface of the GaAs layer. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23370382A JPS59124170A (en) | 1982-12-29 | 1982-12-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23370382A JPS59124170A (en) | 1982-12-29 | 1982-12-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59124170A true JPS59124170A (en) | 1984-07-18 |
Family
ID=16959218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23370382A Pending JPS59124170A (en) | 1982-12-29 | 1982-12-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59124170A (en) |
-
1982
- 1982-12-29 JP JP23370382A patent/JPS59124170A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4489480A (en) | Method of manufacturing field effect transistors of GaAs by ion implantation | |
| US3909307A (en) | Process for compensating boundary charges in silicon thin layers epitaxially grown on a substrate | |
| IE52184B1 (en) | Device isolation in silicon semiconductor substrates | |
| JPH01175265A (en) | Field-effect transistor and its manufacture | |
| EP0177494A1 (en) | PROCESS FOR FABRICATING GaAs FET WITH ION IMPLANTED CHANNEL LAYER | |
| JPS59124170A (en) | Manufacture of semiconductor device | |
| US3936321A (en) | Method of making a compound semiconductor layer of high resistivity | |
| JPS596054B2 (en) | Method for manufacturing semiconductor devices | |
| JPS6327852B2 (en) | ||
| JPS5853863A (en) | Preparation of semiconductor device | |
| JPS6047428A (en) | Manufacture of semiconductor device | |
| JPH0212875A (en) | Manufacture of semiconductor device | |
| JPH0533527B2 (en) | ||
| JPS6157714B2 (en) | ||
| JP3035941B2 (en) | Method for manufacturing group III-V compound semiconductor device | |
| FR2463825A1 (en) | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE IN A SIMULATED EPITAXIAL LAYER | |
| JPS61135166A (en) | Manufacture of schottky barrier gate type field-effect transistor | |
| JPH01286308A (en) | Manufacture of gallium arsenide field effect transistor | |
| JPS60254672A (en) | Manufacture of fet | |
| JPH02266534A (en) | Manufacture of semiconductor device | |
| JPS59228713A (en) | Manufacture of semiconductor device | |
| JPS58145119A (en) | Manufacture of compound semiconductor device | |
| JPS6223175A (en) | Manufacture of semiconductor device | |
| WO1988006802A1 (en) | IMPROVED ION-IMPLANTED GaAs FIELD-EFFECT TRANSISTOR | |
| JPH0373542A (en) | Manufacture of ga-as field effect transistor |