JPS6047428A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6047428A JPS6047428A JP58155006A JP15500683A JPS6047428A JP S6047428 A JPS6047428 A JP S6047428A JP 58155006 A JP58155006 A JP 58155006A JP 15500683 A JP15500683 A JP 15500683A JP S6047428 A JPS6047428 A JP S6047428A
- Authority
- JP
- Japan
- Prior art keywords
- protective film
- ions
- semi
- semiconductor device
- approximately
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 230000001681 protective effect Effects 0.000 claims abstract description 30
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 150000002500 ions Chemical class 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 14
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 28
- -1 oxygen ions Chemical class 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 10
- 230000000694 effects Effects 0.000 claims description 7
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 230000002411 adverse Effects 0.000 claims description 3
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 claims 3
- 239000013078 crystal Substances 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 238000005979 thermal decomposition reaction Methods 0.000 abstract description 2
- 229910017083 AlN Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 231100000989 no adverse effect Toxicity 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 150000004820 halides Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
- H01L21/2656—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds characterised by the implantation of both electrically active and inactive species in the same semiconductor region to be doped
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は、半絶縁性砒化ガリウム（ＧａＡｓ）基板を用
いる半導体装置を製造する際に適用して好結果が得られ
る方法に関する。TECHNICAL FIELD OF THE INVENTION The present invention relates to a method that can be successfully applied in manufacturing semiconductor devices using semi-insulating gallium arsenide (GaAs) substrates.
従来技術と問題点
近年、ＧａＡｓ系集積回路或いは光−電気集積回路（Ｏ
ＥＩＣ）等に関する開発及び研究が盛んである。。Prior art and problems In recent years, GaAs-based integrated circuits or opto-electrical integrated circuits (O
Development and research regarding EIC) etc. are active. .
一般に、それ等半導体装置には、半絶縁性ＧａＡｓ基板
が使用されていが、このＧａＡｓ基板はシリコン（Ｓｔ
）基板に比較して結晶欠陥が著しく多い。例えば、Ｇａ
Ａｓ基板に於ける転位密度は１０３〜１０５ 〔個／Ｃ
ｍ２）であり、Ｓｉ基板に於けるそれは０である。Generally, semi-insulating GaAs substrates are used in these semiconductor devices;
) There are significantly more crystal defects than the substrate. For example, Ga
The dislocation density in the As substrate is 103 to 105 [pieces/C
m2), which is 0 in the Si substrate.
ところで、ＧａＡｓ系半導体装置を製造する場合、半絶
縁性ＧａＡｓ基板に対してイオン注入法を適用し、不純
物イオン、例えばＳｔイオンを１Ｘｌ０１７ （ω−３
〕程度打ち込み、その後、全面に保護膜を形成してから
温度８００（’Ｃ）乃至８５０〔℃〕程度で２０〔分〕
乃至３０〔分〕程度の熱処理をして動作領域を形成し、
その動作領域に素子を作り込むことが行なわれている。By the way, when manufacturing a GaAs-based semiconductor device, an ion implantation method is applied to a semi-insulating GaAs substrate, and impurity ions, for example, St ions are added to 1Xl017 (ω-3
] After that, after forming a protective film on the entire surface, the temperature is about 800 ('C) to 850 [℃] for 20 [minutes].
A heat treatment is performed for about 30 to 30 minutes to form an operating region.
Efforts are being made to build elements into the operating region.
然し乍ら、注入されたＳｔイオンを活性化する為の前記
熱処理を行なうと、Ｓｔイオンが前記半絶縁性ＧａＡｓ
基板中の結晶欠陥にゲッタリング（吸着）され、前記動
作領域内で活性化された不純物の濃度、即ちキャリヤ濃
度が局所的に不均一になり、例えば前記結晶欠陥が存在
する部分ではキャリヤ濃度が５ Ｘ １０” （ｃｍ−
３）にもなってしまう。However, when the heat treatment for activating the implanted St ions is performed, the St ions are transferred to the semi-insulating GaAs.
The concentration of impurities that are gettered (adsorbed) by crystal defects in the substrate and activated within the operating region, that is, the carrier concentration, becomes locally non-uniform. 5 x 10” (cm-
It also becomes 3).
このような動作領域に、ＧａＡｓ系半導体装置の基本的
素子の一つである電界効果トランジスタを形成した場合
、その闇値電圧ｖｔｈにバラツキが発生する。例えば結
晶欠陥がある部分、或いはその近傍に電界効果トランジ
スタのゲート電極が存在した場合、キャリヤ濃度が他の
部分より高いから闇値電圧ｖｔｈは深く （大きく）な
り、また、結晶欠陥がない部分にゲート電極が存在した
場合、キャリヤ濃度は低いから闇値電圧ｖ−ｔｈは浅く
（小さく）なる。そして、動作領域全域に亙り結晶欠
陥の密度に比例して闇値電圧の標準偏差σｖｔｈが大き
くなる。ＧａＡｓ系半導体装置では、電界効果トランジ
スタを高密度に広い面積に亙り集積化したものであるか
ら、或既定値以上に闇値電圧の標準偏差σｖｔｈが大き
くなると装置は動作することができなくなる。When a field effect transistor, which is one of the basic elements of a GaAs-based semiconductor device, is formed in such an operating region, variations occur in its dark value voltage vth. For example, if the gate electrode of a field effect transistor exists in a part where there is a crystal defect or in the vicinity thereof, the dark value voltage vth becomes deeper (larger) because the carrier concentration is higher than in other parts. When the gate electrode exists, the carrier concentration is low, so the dark value voltage v-th becomes shallow (small). Then, the standard deviation σvth of the dark value voltage increases in proportion to the density of crystal defects over the entire operating region. In a GaAs-based semiconductor device, field effect transistors are integrated at high density over a wide area, so if the standard deviation σvth of the dark value voltage becomes larger than a certain predetermined value, the device becomes unable to operate.
また、前記とは別に、半導体装置では、回路を構成する
上で抵抗層が必要であって、これはＧａＡｓ系も例外で
はなく、特に、シート抵抗として１ （ＫΩ〕乃至５
（ＫΩ〕程度の値のものが要求される。In addition, apart from the above, semiconductor devices require a resistance layer to form a circuit, and GaAs systems are no exception to this, and in particular, the sheet resistance ranges from 1 (KΩ) to 5
(KΩ) is required.
この抵抗層をイオン注入法で形成するとした場合、抵抗
層の抵抗値を高くするには不純物濃度を下げることが必
要である。If this resistance layer is formed by ion implantation, it is necessary to lower the impurity concentration in order to increase the resistance value of the resistance layer.
然し乍ら、ＧａＡｓの表面準位が抵抗層表面に容易に形
成されること及び抵抗層の不純物濃度が低いことと相俟
って、表面準位密度に起因する空乏層が抵抗層側へ表面
から延びて来て、抵抗層の電流値を変化させ、従って、
抵抗層の抵抗値にバラツキを生じ、特に高い抵抗値の抵
抗層を得ようとするとその傾向が著しくなる。However, because the surface states of GaAs are easily formed on the surface of the resistance layer and the impurity concentration of the resistance layer is low, a depletion layer due to the density of surface states extends from the surface toward the resistance layer side. changes the current value of the resistive layer, and therefore,
Variations occur in the resistance value of the resistance layer, and this tendency becomes remarkable when attempting to obtain a resistance layer with a particularly high resistance value.
発明の目的
本発明は、半絶縁性ＧａＡｓ基板に不純物を導入して動
作領域を形成しても、その不純物が動作領域全域に均一
に分布し、結晶欠陥に依る闇値電圧のバラツキが発生し
ないように、また、抵抗層の抵抗値を容易に制御するこ
とが可能であるようにする。Purpose of the Invention The present invention provides a method for forming an operating region by introducing impurities into a semi-insulating GaAs substrate, but the impurities are uniformly distributed over the entire operating region, and variations in dark voltage due to crystal defects do not occur. In addition, it is possible to easily control the resistance value of the resistive layer.
発明の構成
本発明の半導体装置の製造方法では、半絶縁性ＧａＡｓ
基板上に保護膜を形成し、次いで、該保護膜を通して前
記半絶縁性ＧａＡｓ基板に酸素イオン或いは水素イオン
など後に半導体装置に悪影響を与えないイオン及び所要
の不純物イオンを注入し、次いで、前記保護膜を残留さ
せたまま熱処理する工程を採ることに依り、動作領域全
域に前記不純物を均一に分布させるようにしている。Structure of the Invention In the method for manufacturing a semiconductor device of the present invention, semi-insulating GaAs
A protective film is formed on the substrate, and then, ions such as oxygen ions or hydrogen ions that do not have an adverse effect on the semiconductor device later and necessary impurity ions are implanted into the semi-insulating GaAs substrate through the protective film. By employing a heat treatment step with the film remaining, the impurities are uniformly distributed over the entire operating region.
発明の実施例
本発明を実施してＧａＡｓ系半導体装置を作成する場合
について説明する。Embodiments of the Invention A case will be described in which a GaAs-based semiconductor device is manufactured by implementing the present invention.
先ず、半絶縁（’ｌ Ｇ ａ Ａ ｓ基板上にスパッタ
法或いは熱分解法を通用して保護膜を形成する。この保
護膜の材料としては、例えば二酸化シリコン（ＳｉＯｚ
）、窒化シリコン（Ｓｉ’３Ｎ４）、窒化アルミニウム
（Ａ ｅ Ｎ）等を用いることができるが、ここではＡ
７２Ｎ膜を使用することにする。First, a protective film is formed on a semi-insulating ('lGaAs) substrate using a sputtering method or a thermal decomposition method.The material for this protective film is, for example, silicon dioxide (SiOz).
), silicon nitride (Si'3N4), aluminum nitride (A e N), etc., but here A
A 72N membrane will be used.
その理由は、ＡＩＮはＧａＡｓと熱膨張係数が略等しい
ので、熱処理時にＡｌ１Ｎ膜とＧａＡｓ基板との界面に
歪みを発生することがなく、しかも、ＧａＡｓとは化学
的に反応せず、安定しているので好ましいことに依る。The reason for this is that AIN has approximately the same coefficient of thermal expansion as GaAs, so it does not cause distortion at the interface between the Al1N film and the GaAs substrate during heat treatment, and it does not chemically react with GaAs, making it stable. It depends on what is preferable.
尚、保護膜の厚さは、例えば２０〜３０〔μｍ〕程度で
良い。Note that the thickness of the protective film may be, for example, about 20 to 30 [μm].
次いで、保護膜を通して水素イオン（Ｈ＋：プロトン・
イオン）を加速電圧例えば３００（Ｋｅ■〕、ドーズ量
例えば１０１４（ｃｍ−２）程度として注入する。Next, hydrogen ions (H+: protons) pass through the protective film.
Ions) are implanted at an acceleration voltage of, for example, 300 (Ke) and a dose of, for example, about 1014 (cm-2).
次いで、同じく保護膜を通してシリコン・イオン（Ｓｔ
”）を加速電圧例えば８０（ＫｅＶ）、ドーズ量例えば
２Ｘ１０１２（ω−２〕程度として注入する。Next, silicon ions (St
'') is implanted at an accelerating voltage of, for example, 80 (KeV) and a dose of, for example, about 2×10 12 (ω-2).
次いで、保護膜を残留させたまま温度例えば８５０（”
ｃ）程度、時間２０ 〔分〕程度の熱処理を行なう。Next, with the protective film remaining, the temperature is increased to, for example, 850 ("
c) Heat treatment is performed for about 20 minutes.
前記のようにして動作領域が完成されるので、そこに、
通當の技法でソース電極及びドレイン電極、ゲート電極
を形成して電界効果トランジスタを形成する。Since the operating area is completed as described above, there is
A field effect transistor is formed by forming a source electrode, a drain electrode, and a gate electrode using conventional techniques.
第１図は本発明を適用して形成した電界効果トランジス
タと従来技術を適用して形成した電界効果トランジスタ
とに於ける闇値電圧の標準偏差σｖｔｈ及び１１＋ドー
ズ量の関係を表わす線図であって、ＴＰ（実線）は本発
明に依るもの、ＰＡ（破線）は従来技術に依るものを示
している。FIG. 1 is a diagram showing the relationship between the standard deviation σvth of the dark value voltage and the 11+ dose in a field effect transistor formed by applying the present invention and a field effect transistor formed by applying the conventional technology. TP (solid line) shows the one according to the present invention, and PA (broken line) shows the one according to the prior art.
図から判るように、Ｈ＋ドーズ量が増加するにつれて闇
値電圧の標準偏差σｖｔｈは小さくなり、或値以上にな
ると飽和する。As can be seen from the figure, as the H+ dose increases, the standard deviation σvth of the dark value voltage becomes smaller, and becomes saturated when it exceeds a certain value.
このように、Ｈ＋の注入に依り閾値電圧の標準偏差σｖ
ｔｈのバラツキ幅が小さくなると同時に低くなる原因に
関しては種々な推測が成り立つが、その一つとして次の
ように考えることができる。In this way, the standard deviation of the threshold voltage σv due to the injection of H+
Various speculations can be made regarding the reason why the variation width of th becomes smaller and lower at the same time, and one of them can be considered as follows.
Ｈ＋を半絶縁性ＧａＡｓ基板中に注入することに依り、
その領域はアモーファス化している。そして、熱処理す
る際、このアモーファス化している領域が再結晶化する
ので、不純物イオンのゲッタリング作用が低減され、該
領域内で均一化される。その結果、該領域内に於けるキ
ャリヤ濃度分布も均一になり、闇値電圧の標準偏差σｖ
ｔｈが小さくなる。 ところで、本発明は、前記したよ
うに、所定領域内のキャリヤ濃度分布を均一化すること
に卓効があることから、抵抗層の抵抗値を安定に一定化
するのにもを効にであり、次に、その実施例について説
明する。By implanting H+ into a semi-insulating GaAs substrate,
That area has become amorphous. Then, during heat treatment, this amorphous region is recrystallized, so that the gettering effect of impurity ions is reduced and the impurity ions are made uniform within the region. As a result, the carrier concentration distribution within the region becomes uniform, and the standard deviation of the dark value voltage σv
th becomes smaller. By the way, as described above, the present invention is extremely effective in uniformizing the carrier concentration distribution within a predetermined region, and therefore is also effective in stably keeping the resistance value of the resistive layer constant. , Next, an example thereof will be described.
先ず、半絶縁性ＧａＡｓ基板上に、例えば気相成長法を
適用して、高抵抗或いは半絶縁性であるＧａｘＡβｌ−
ｘ Ａ Ｓ半導体層を厚さ例えば４０〜５０（ｎｍ）程
度に成長する。この時、適用する気相成長法としてはハ
ライド法、ＭＯＣＶＤ（ｍｅｔａｌ ｏｒｇａｎｉｃ
ｃｈｅｍｉｃａｌ Ｖａｐｏｕｒ ｄｅｐｏｓｉｔｉｏ
ｎ）法、ＭＢＥ（ｍｏｌｅｃｕｌａｒ ｂｅａｍ ｅｐ
ｉｔａｘｙ）法等を適用して良い。また、Ｘ値は０．２
〜０．６とする。First, high resistance or semi-insulating GaxAβl- is deposited on a semi-insulating GaAs substrate by, for example, vapor phase growth.
The x AS semiconductor layer is grown to a thickness of, for example, about 40 to 50 (nm). At this time, the vapor phase growth methods to be applied include the halide method, MOCVD (metal organic
chemical vapor deposition
n) method, MBE (molecular beam ep
itaxy) method etc. may be applied. Also, the X value is 0.2
~0.6.
次いで、スパッタ法を適用して保護膜を厚さ例えば２０
（ｎｍ）乃至４．０（ｎｍ）程度に形成する。この保護
膜の材料は、前記同様、５ｉ０２、Ｓ ｉ ３ Ｎ ４
、ＡｌＮ等から選択して良い。Next, a protective film is formed to a thickness of, for example, 20 mm by applying a sputtering method.
(nm) to about 4.0 (nm). As above, the material of this protective film is 5i02, S i 3 N 4
, AlN, etc.
次いで、保護膜並びに高抵抗或いは半絶縁性であるＧａ
ｘＡβト。Ａｓ半導体層を通してＨ＋を加 −速電圧３
００ （’ＫｅＶ） 、ドーズ量例えば１０Ｉ４（１０
ｌ４（程度として注入する。 次いで、同じく保護膜並
びにＧａｘＡβｌ−Ｘ Ａ Ｓ半導体層を通してＳｉ＋
を加速電圧を例えば１７５（ＫｅＶ）程度として注入す
る。尚、ドーズ量は必要な抵抗値に対応して選択する。Next, a protective film and high resistance or semi-insulating Ga are formed.
xAβt. Accelerate H+ through the As semiconductor layer - Accelerate voltage 3
00 ('KeV), dose amount e.g. 10I4 (10
Then, Si + is implanted through the protective film and the Ga
is injected at an accelerating voltage of, for example, about 175 (KeV). Note that the dose amount is selected depending on the required resistance value.
次いで、保護膜を残留させたまま温度例えば７５０（’
Ｃ）乃至８５０（’Ｃ）程度、時間例えば２０〔分〕程
度に選定して熱処理を行なう。Next, with the protective film remaining, the temperature is, for example, 750 ('
The heat treatment is performed at a temperature of about 850 ('C) and a time of about 20 minutes, for example.
これに依り、所定の抵抗値を有する抵抗層を再現性よく
形成することができる。With this, a resistive layer having a predetermined resistance value can be formed with good reproducibility.
第２図は本発明を適用して形成した抵抗層と従来技術を
適用して形成した抵抗層とに於けるシート抵抗値〔Ω−
ロ〕及びＳｔ＋のドーズ量の関係を表わす線図であって
、ＴＰ（実線）は本発明に依るものであり、ＰＡ（破線
）は従来技術に依るものを示している。FIG. 2 shows the sheet resistance values [Ω-
B] is a diagram showing the relationship between the doses of St + and TP, in which TP (solid line) is based on the present invention, and PA (broken line) is based on the prior art.
図から判るように、Ｓｔ＋のドーズ量が少なくなるにつ
れてシート抵抗値は増加している。そして、従来技術で
作成された抵抗では、シート抵抗値の増大とともにバラ
ツキも大きくなっている。As can be seen from the figure, the sheet resistance value increases as the St+ dose decreases. Furthermore, in resistors made using conventional techniques, as the sheet resistance value increases, the variation also increases.
しかも、１０１２ （ｃｍ−２）以下のドーズ量では基
板に於ける一部で高抵抗化し、その抵抗値制御は不可能
な状態になっている。Moreover, if the dose is less than 10@12 (cm@-2), a portion of the substrate becomes highly resistive, making it impossible to control the resistance value.
これは、ＧａＡｓ基板の表面準位に依る空乏層が抵抗層
へ延びてきて、完全に抵抗層チャネルを遮断した状態で
高抵抗になったものであると考察される。This is considered to be because the depletion layer due to the surface level of the GaAs substrate extends to the resistance layer, and the resistance layer becomes high in a state where the channel is completely blocked.
本発明の場合には、Ｓｉ＋のドーズ量の減少につれてシ
ート抵抗値は増加するが基板内に於けるバラツキに然程
の変化は無く、また、制御し得ない程の高抵抗にもなら
ない。In the case of the present invention, although the sheet resistance value increases as the Si+ dose decreases, the variation within the substrate does not change appreciably, and the resistance does not become uncontrollably high.
この理由としては、少ない不純物が全域に亙り均一に分
布していること、保護膜と高抵抗或いは半絶縁性Ｇａｘ
ＡβトウＡｓ半導体層との界面に於ける表面準位密度が
低減されていること、表面準位に基因する空乏層がＧ
ａ Ｘ Ａ Ｉｔ Ｉ−Ｘ Ａ ｓ半導体層で遮断され
ていること等に依ると考えられる。尚、Ａｌ１Ｎ膜−半
絶縁性ＧａＡｓ基板からなる構造でも、かなり表面準位
密度を低下させることが可能ではあるが、Ｇ 、ａ ｘ
Ａ Ａ Ｉ−Ｘ Ａ ｓ半導体層を介挿することに依り
、前記効果は更に向上することが確認されている。The reason for this is that a small number of impurities are uniformly distributed over the entire area, and that the protective film and high resistance or semi-insulating Gax
The surface state density at the interface with the Aβ to As semiconductor layer is reduced, and the depletion layer based on the surface state is
This is thought to be due to the fact that it is blocked by the aXAItI-XAs semiconductor layer. Although it is possible to considerably reduce the surface state density even with a structure consisting of an Al1N film and a semi-insulating GaAs substrate, G, a x
It has been confirmed that the above effect is further improved by interposing an AAI-XAs semiconductor layer.
前記二つの実施例の何れに於いても、Ｈ＋の注入に依る
半絶縁性ＧａＡｓ基板のアモーファス化が重要な役割を
果しているが、この場合、Ｈ＋に限らず、酸素イオン（
０＋）或いは他のイオンで半導体装置に悪影響を及ぼす
虞がないものであれば使用することができる。また、該
アモーファス化の為のイオン注入は導電性に影響を与え
る不純物イオンの注入の前後いずれの時期に行なっても
良い。In both of the above two embodiments, making the semi-insulating GaAs substrate amorphous by implanting H+ plays an important role, but in this case, not only H+ but also oxygen ions (
0+) or other ions that have no risk of adversely affecting the semiconductor device can be used. Further, the ion implantation for making the material amorphous may be performed either before or after the implantation of impurity ions that affect conductivity.
発明の効果
本発明の半導体装置の製造方法では、半絶縁性ＧａＡｓ
基板に保護膜を形成し、次いで、該保護膜を通して酸素
イオン或いは水素イオンなど後に半導体装置に悪影響を
与えないイオン及び所要の不純物イオンを注入し、次い
で、前記保護膜を残留させたまま熱処理する工程を採る
ことに依り、前記半絶縁性ＧａＡｓ基板に結晶欠陥が存
在していても不純物の分布を均一にすることが可能であ
る為、特性が揃った素子を形成することができ、特に、
多数の電界効果トランジスタの闇値電圧を一定に保つの
有効である。また、同じ理由から、抵抗層の抵抗値を制
御性良く均一化することができ、特に高抵抗値の抵抗層
を容易に且つ再現性良く作成することができる。Effects of the Invention In the method for manufacturing a semiconductor device of the present invention, semi-insulating GaAs
A protective film is formed on the substrate, and then, through the protective film, ions such as oxygen ions or hydrogen ions, as well as necessary impurity ions, which will not have a negative effect on the semiconductor device are implanted, and then heat treatment is performed with the protective film remaining. By adopting this process, it is possible to make the distribution of impurities uniform even if crystal defects exist in the semi-insulating GaAs substrate, so it is possible to form an element with uniform characteristics, and in particular,
This is effective in keeping the dark voltage of a large number of field effect transistors constant. Furthermore, for the same reason, the resistance value of the resistance layer can be made uniform with good controllability, and a resistance layer with particularly high resistance value can be easily created with good reproducibility.
第１図は闇値電圧の標準偏差σｖｔｈ及びＨ＋のドーズ
量（ｃｓ −２）の関係を説明する為の線図、第２図は
シート抵抗〔Ω−ロ〕及びＳｉ＋のドーズ量（ｃ、−２
）の関係を説明する為の線図である。
特許出願人 富士通株式会社
代理人弁理士 相 谷 昭 司
代理人弁理士 渡 邊 弘 −Fig. 1 is a diagram for explaining the relationship between the standard deviation σvth of the dark value voltage and the H+ dose (cs -2), and Fig. 2 is a diagram for explaining the relationship between the standard deviation σvth of the dark value voltage and the H+ dose (cs -2), and Fig. 2 is a diagram showing the relationship between the sheet resistance [Ω-b] and the Si+ dose (c, -2
) is a diagram for explaining the relationship. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Shoji Aitani Representative Patent Attorney Hiroshi Watanabe −
Claims (2)
次いで、該保護膜を通して前記半絶縁性砒化ガリウム基
板に酸素イオン或いは水素イオンなど後に半導体装置に
悪影響を与えないイオン及び所要の不純物イオンを注入
し、次いで、前記保護膜を残留させたまま熱処理する工
程が含まれてなることを特徴とする半導体装置の製造方
法。(1) Forming a protective film on a semi-insulating gallium arsenide substrate,
Next, ions such as oxygen ions or hydrogen ions that do not have a negative effect on the semiconductor device and necessary impurity ions are implanted into the semi-insulating gallium arsenide substrate through the protective film, and then heat treatment is performed while the protective film remains. 1. A method for manufacturing a semiconductor device, comprising the steps of:
縁性ガリウム・アルミニウム砒素層を形成し、次いで、
該高抵抗或いは半絶縁性ガリウム・アルミニウム砒素層
」二に保護膜を形成し、次いで、該保護膜並びに前記高
抵抗或いは半絶縁性ガリウム・アルミニウム砒素層を通
して前記半絶縁性砒化ガリウム基板に酸素イオン或いは
水素イオンなど後に半導体装置に悪影響を与えないイオ
ン及び所要の不純物イオンを注入し、次いで、前記保護
膜を残留させたまま熱処理する工程が含まれてなること
を特徴とする半導体装置の製造方法。(2) forming a high resistance or semi-insulating gallium aluminum arsenide layer on a semi-insulating gallium arsenide substrate;
A protective film is formed on the high resistance or semi-insulating gallium aluminum arsenide layer, and then oxygen ions are introduced into the semi-insulating gallium arsenide substrate through the protective film and the high resistance or semi-insulating gallium aluminum arsenide layer. Alternatively, a method for manufacturing a semiconductor device comprising the steps of implanting ions such as hydrogen ions that do not have an adverse effect on the semiconductor device and necessary impurity ions, and then performing heat treatment with the protective film remaining. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58155006A JPS6047428A (en) | 1983-08-26 | 1983-08-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58155006A JPS6047428A (en) | 1983-08-26 | 1983-08-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6047428A true JPS6047428A (en) | 1985-03-14 |
Family
ID=15596630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58155006A Pending JPS6047428A (en) | 1983-08-26 | 1983-08-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6047428A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4701422A (en) * | 1986-04-07 | 1987-10-20 | Rockwell International Corporation | Method of adjusting threshold voltage subsequent to fabrication of transistor |
| JPS62250635A (en) * | 1986-04-23 | 1987-10-31 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| US4713354A (en) * | 1985-02-28 | 1987-12-15 | Oki Electric Industry Co., Ltd. | Method of heat treatment for reduction of dislocation density near III-V substrate surface |
| FR2627901A1 (en) * | 1988-02-29 | 1989-09-01 | Mitsubishi Electric Corp | METHOD FOR MANUFACTURING A COMPOUND SEMICONDUCTOR DEVICE HAVING A CONDUCTIVE LAYER HAVING A CONCENTRATION OF UNIFORM DOPANT |
| EP3836193A1 (en) * | 2019-12-12 | 2021-06-16 | Commissariat à l'Energie Atomique et aux Energies Alternatives | Method for manufacturing a doped semiconductor layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5247676A (en) * | 1975-10-14 | 1977-04-15 | Matsushita Electric Ind Co Ltd | Process for production of semiconductor device |
| JPS57186326A (en) * | 1981-05-13 | 1982-11-16 | Nec Corp | Ion implanting method |
| JPS583236A (en) * | 1981-06-30 | 1983-01-10 | Fujitsu Ltd | Manufacture of gallium arsenide element |
-
1983
- 1983-08-26 JP JP58155006A patent/JPS6047428A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5247676A (en) * | 1975-10-14 | 1977-04-15 | Matsushita Electric Ind Co Ltd | Process for production of semiconductor device |
| JPS57186326A (en) * | 1981-05-13 | 1982-11-16 | Nec Corp | Ion implanting method |
| JPS583236A (en) * | 1981-06-30 | 1983-01-10 | Fujitsu Ltd | Manufacture of gallium arsenide element |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4713354A (en) * | 1985-02-28 | 1987-12-15 | Oki Electric Industry Co., Ltd. | Method of heat treatment for reduction of dislocation density near III-V substrate surface |
| US4701422A (en) * | 1986-04-07 | 1987-10-20 | Rockwell International Corporation | Method of adjusting threshold voltage subsequent to fabrication of transistor |
| JPS62250635A (en) * | 1986-04-23 | 1987-10-31 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| FR2627901A1 (en) * | 1988-02-29 | 1989-09-01 | Mitsubishi Electric Corp | METHOD FOR MANUFACTURING A COMPOUND SEMICONDUCTOR DEVICE HAVING A CONDUCTIVE LAYER HAVING A CONCENTRATION OF UNIFORM DOPANT |
| EP3836193A1 (en) * | 2019-12-12 | 2021-06-16 | Commissariat à l'Energie Atomique et aux Energies Alternatives | Method for manufacturing a doped semiconductor layer |
| FR3104808A1 (en) * | 2019-12-12 | 2021-06-18 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Method for producing a doped semiconductor layer |
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