FR2463825A1 - METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE IN A SIMULATED EPITAXIAL LAYER - Google Patents

Abstract

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE IN A SIMULATED EPITAXIAL LAYER. THE PROCESS CONSISTS OF: AA FORMING A SIMULATED EPITAXIAL LAYER 18 OF A THICKNESS GIVEN BELOW THE SURFACE OF THE SEMICONDUCTOR BODY I BY IMPLANT IN THE BODY 10 IMPURITIES OF A CONDUCTIVITY DETERMINATOR TYPE OPPOSED TO THE CONDUCTIVITY TYPE OF THE BODY, TO A DEPTH 16, BELOW THE SURFACE 14 OF THE BODY 10, WHICH IS LESS THAN THE DESIRED THICKNESS OF THE SIMULATED EPITAXIAL LAYER 18, II BY HEATING THE SEMICONDUCTOR BODY 10 TO A TEMPERATURE ABOVE THAT WHERE THERE IS A NOTABLE DIFFUSION OF IMPLANTED IMPURITIES AND III BY ENDING THE APPLICATION OF HEAT TO THE SEMICONDUCTOR BODY 10 ONCE THE IMPLANTED IMPURITIES HAVE DIFFUSED UNDER THE SURFACE OF THE SEMICONDUCTOR BODY AT APPROXIMATELY EQUAL THICKNESS DISTANCE DESIREE OF THE SIMULATED EPITAXIAL LAYER 18; B.A DOPING DETERMINED ZONES 22, 24; C.A FORM AN INSULATING LAYER 26; AND D.A FORM METALLIZED ZONES 28, 30, 32. APPLICATION TO THE MANUFACTURE OF SEMICONDUCTOR MATERIALS.

Description

The present invention relates to a manufacturing process

  cation of a semiconductor device, and more particularly

  a process for the production of semiconducting materials

  these monocrystallines comprising a simulated epitaxial layer

  formed by ion implantation.

  The use of epitaxial layers in the manufacture of

  semiconductor devices and integrated circuits

  has become widespread in the industry since the provisions

  Such products are manufactured commercially. We use

  various methods for forming epitaxial layers. In

  a commonly applied process, one begins by preparing

  the surface of the substrate to remove impurities

  at the atomic scale and obtain a crystallographic surface

  oriented with an exceptional degree of flatness.

  However, even if the surface is prepared very carefully, the initial growth of an epitaxial layer is often

  characterized by lattice dislocations and other

  perfections. After proper preparation of the surface, the layer is developed by a vapor deposition process. We

  can perform the deposition of silicon in the vapor state in re-

  with hydrogen, silicon tetrachloride, triturium

  chlorosilane or silane at temperatures of about 10,000C.

  Flow rates and proportions of reagents are usually very critical as well as accurate temperature control during the deposition process. In addition, it is essential to carefully adjust the dopant densities introduced during

epitaxial deposition.

  Given the delicate nature of the process of depositing

  steam, the yields obtained in the manufacture of pastil-

  epitaxial tend to be weak, largely to

  imperfections of the crystal lattice and the lack of unity

  thickness of the epitaxial layer from one pellet to another and from one point to another on the same pellet. For this reason, the cost of epitaxial pellets tends to be

  relatively high. Since epitaxial lozenges

  are the raw materials from which we manufacture

  semiconductor devices and integrated circuits

  the cost of end products is also increased.

  In addition, there is a tendency in industry to use thinner epitaxial layers. Some epitaxial thicknesses of some microns or less have been needed for some time. However, it is difficult to achieve uniform thin epitaxial layers by vapor deposition techniques, and epitaxial layers may not be able to be produced by conventional methods.

1 gNm thick.

  The subject of the present invention is therefore

  - a method of manufacturing a semiconductor device

  conductor in a semiconductor body having a

epitaxial simulated cheek;

  a method of forming an epitaxial layer

  merged onto a semiconductor body in which it is no longer

  necessary to regulate the flow rates accurately, the

  reagents and dopant densities, as it is

  normally necessary in the commercial processes of

  steam; a method of forming a simulated epitaxial layer on a semiconductor body by a method using ion implantation; a method of manufacturing an epitaxial layer

  simulated on a semiconductor body that can be implemented

  on commercial ion implantation devices; a method of forming a semiconductor body having a simulated epitaxial layer which is significantly less expensive than a corresponding product manufactured by conventional methods; a process for forming an epitaxial layer

  simulated on a semiconductor body in which one can re-

  accurately determine the uniformity and thickness of the simulated epitaxial layer;

  a method of forming an epitaxial layer

  mulled on a semiconductor body which may have a thickness of a few microns or less;

  a process for forming an epitaxial layer

  xiale simulated on a semiconductor body without the need to carefully prepare the surface of the substrate; a method for manufacturing in a body

  semiconductor a simulated epitaxial layer having a

  It is a more uniform smelter, a more uniform dopant density, and a higher degree of crystallographic perfection than is normally possible by prior commercial processes. According to the present invention, a method of

  manufacture of a semiconductor device in a se-

  conductor of a given type of conductivity.The process

  to form a simulated epitaxial layer of a given thickness below the surface of the semiconductor body. To form the simulated epitaxial layer, impurities of a determinant type of opposite conductivity are implanted in the body.

  the conductivity type of the body, at a depth,

  below the body surface, which is less than the desired thickness of the simulated epitaxial layer. Then, the semiconductor body is heated to a temperature higher than that

  o there is a noticeable diffusion of the impurities implied

  Tees. The application of heat is terminated once the implanted impurities have diffused below the surface of the body

  semiconductor, at a distance approximately equal to the

  desired thickness of the simulated epitaxial layer. We dope

  in defined areas of the simulated epitaxial layer

  to modify their conductivity and form regions of

  this and drain within the simulated epitaxial layer. We

  forms an insulating layer on the surface of the semiconducting body.

  above the simulated epitaxial layer at a point between the source and drain regions. Then, areas are metallized, respectively, above the region of the source, the grain region and the layer.

  insulation, to form electrodes.

  It is better to repair the damage of the network and activate the impurities implanted before heating the

  semiconductor body for diffusing the implanted impurity.

  In this embodiment, the method includes a step

  heating element in which the semiconductor body is heated to a temperature below that there is a significant diffusion of the implanted impurities, for

  repair network damage and activate impurities im-

planted.

  Preferably, the implantation of the impurities is effected

  kills through a thin layer of oxide formed on the surface

  that of the semiconductor body. Implantation through a thin oxide layer eliminates the surface damage that normally occurs when impurities are implanted with

great energies of acceleration.

  In order to achieve the above aims as well as any other objects which may appear hereinafter, the invention proposes a method of manufacturing a semiconductor device.

  in a semiconductor body having an epitaxial layer

  the simulated method, which is described below with reference to

  drawings on which the same reference symbols

  they designate similar parts: Fig. 1 is a section of a prepared semiconductor body

  to undergo the process of the invention.

  Fig. 2 is a semiconductor body section once

  impurities have been implanted below its surface.

  this. Fig. 3 is a section of the semiconductor body as it

  appears once the simulated epitaxial layer has been formed

according to the invention.

  Fig. 4 is a section of the semiconductor body once source and drain regions have been formed in the

simulated epitaxial layer.

  Fig. 5 is a section of the semiconductor body as it appears once the door insulator has been formed on its surface and FIG. 6 is a section of the terminated semiconductor device. The present invention is applicable to the manufacture

  of semiconductor devices in semiconductors

  of various semiconductor materials known as

  silicon, germanium, gallium arsenide and arsenide

  senesure-gallium phosphide. Determinant impurities of the conductivity type which are suitable for being implanted

  in each of the different types of semiconducting

  these are well known as well as the diffusion coefficients.

  various impurities. For example, we illustrate

  ra the invention by an example in which one implants

  boron ions in n-type silicon to form a

  epitaxial simulated p type. However, it is understood that these materials are chosen only as examples

  that the invention should not be interpreted as limiting

to these.

  In addition, the example of the method of the invention which has been chosen to illustrate it describes the formation of a simulated epitaxial layer approximately 12 Am thick. We choose

  consequently, the implantation energies, the impurity assay,

  and the broadcast settings. However, he is

  that these values are determined according to the

  selected impurities, the implanted impurity and the particular depth of the desired simulated epitaxial

  should not be interpreted as limiting the invention.

  As shown in Figure 1, the process starts from a body

  or silicon wafer of the type n, 10, having an over-

  practically flat face 12. It is preferable to oxidize

  the body 10 to form on its entire surface 12 a relatively thin layer of silicon dioxide 14.

  preferably, the silicon dioxide layer 14 has a thickness of

  about 500 A. The role of the silicon dioxide layer

  licium 14 is to prevent physical damage normally

  bi by the surface 12 of the body 10 during implantation io-

  great energy of acceleration.

  Without any photolithographic masking operation, an impurity having a conductivity determining type which is opposite to the conductivity type of the body 10 is implanted in the entire surface of the semiconductor body 10. For example, boron can be used which results in a layer of type p. A typical implantation dose of 3.0 x 10 12 /

  cm2 at about 200 keV appeared appropriate.

  Boron is implanted at a depth, below the surface 12 of the body 14, which is significantly less than the desired thickness of the simulated epitaxial layer. For

  the implementation parameters indicated above, the

  boron will have a maximum concentration of approximately

  0.02 μm below surface 12 with a limit or

  less than 0.05 Ulm below the

  The body thus appears as shown in FIG. 2, the implanted boron layer being designated

by the reference 16.

  Once the implantation step is completed,

  vee, the semiconductor body is cleaned with a hot mixture of sulfuric and nitric acids and rinsed with water

  deionized. Then the semi-con-

  cleaned at a short heat treatment of about

  minutes at 9500C to repair the damage to the network and

  tive implanted boron ions.It should be noted that

  to repair the damage to the network and to

  activate the implanted impurity is at a temperature no-

  less than that where there is a noticeable diffusion of the impurity implanted. In such a case, since boron has a diffusion temperature of about 1200 ° C,

  a temperature significantly lower than this is chosen

  their. The semiconductor body is then subjected to a heat treatment which lasts about 12 hours at about 1200 hours.

  OC in an oxidizing medium consisting of only 02 or a

  lange of it and nitrogen, to cause diffusion

  notable implanted boron ions. The parameters of this

  are chosen according to the concentration

  desired superficial impurity content and thickness

  desired of the simulated epitaxial layer formed. The parameters

  selected by way of example lead to a layer of

  simulated pitaxial about 12 mm thick. The body se-

  the conductor then has the appearance indicated by the

  3 reference 18 denotes the epitaxial layer

mullée formed according to the invention.

  Once the simulated epitaxial layer 18 has been formed,

  below the surface 12 of the semiconductor body 10, the body 10 is processed in a conventional manner to manufacture therein

  a semiconductor device. By photo techniques

  lithography, we form on the surface 12 of

  semiconductor body 10 a mask 20 having openings

  above the portions of the simulated epitaxial

  18 where it is necessary to form source and drain regions. The source 22 and drain 24 regions are then formed in the simulated epitaxial layer 18, in any known manner, for example by diffusion or ion implantation of an n-type dopant. After the formation of the regions of

  source 22 and drain 24, the semiconductor body 10

the appearance of Figure 4.

  Once the source 22 and drain 24 regions have been formed, the mask 20 is removed and a relatively thin insulating layer composed of carbon dioxide is developed or deposited on the surface 12 of the semiconductor body 10.

  silicon or similar body. Then, by a second

  photolithographic process, the insulating layer is removed from

  all areas of surface 12 except the area

  above the channel of the semiconductor device that extends

  between source 22 and dedra-in 24 regions.

  In this case, the door insulator 26 is formed. The semiconducting body

  then has the appearance of Figure 5.

  The semiconductor body is then subjected to a metallization process in which a thin layer of

  metal on the surface of the body and then removed

  by a third photolithographic process

  conventional manner so as to form a source electrode 28

  above the source region 22, a drain electrode 30 above the drain region 24 and a gate electrode 32 at the upper surface of the insulating layer 26. It is possible to

  then connect conductors to the electrodes. The semi body

  driver then has the appearance of Figure 6.

  It will be understood that the semiconductor device

  that the process of the invention is identical to the

  corresponding properties manufactured on semiconductor

  the epitaxial layer is formed by a conventional technique

  that, except in the process of the invention, it is

  me the source and drain regions in an epita-

  simulated xiale created by ion implantation and diffusion instead by conventional techniques of chemical agent vapor deposition. The simulated epitaxial layer thus formed has physical and electrical properties identical to those of an epitaxial layer formed by conventional vapor deposition techniques but it is no longer necessary

  carefully prepare the surface of the substrate, monitor

  Strictly the flow rates, the proportions of reagents and the temperature as in conventional methods of deposition of chemical agents. The simulated epitaxial layer formed by the method of the invention has a more uniform depth, a more uniform dopant density and a higher degree

  crystallographic perfection that it is not possible

  by conventional techniques. In addition, the entire process of formation of the simulated epitaxial layer can

  run with conventional io-

  Picnic. It is also possible, by the method of the invention,

  to obtain a simulated epitaxial layer thinner than this

  which can be obtained by conventional techniques.

  Only one preferred embodiment of the invention has been described for purposes of illustration, but it is obvious that many modifications and variations could be made, and it is understood that the invention extends to

these variants.

Claims (2)

  1. A method of manufacturing a semicon-   conductor in a semiconductor body of a conductivity type   given, characterized in that it consists of: (a) forming a simulated epitaxial layer (18) of a   given thickness below the surface of the semicon-   conductor (I) by implanting in the body (10) impurities of a conductivity determining type opposite to the conductivity type of the body, at a depth (16), below   the surface (14) of the body (10), which is less than the thickness   desired state of the simulated epitaxial layer (18), (II) by heating the semiconductor body (10) to a temperature higher than that where significant diffusion occurs   implanted impuritiesPet (III) by terminating the application   cation of heat to the semiconductor body (10) once the implanted impurities have diffused beneath the surface of the   semiconductor body, at a distance of approximately   at the desired thickness of the simulated epitaxial layer (18). (b) doping specific areas (22,24) of the simulated epitaxial layer (18) to modify their conductivity and form source (22) and drain (24) regions within the simulated epitaxial layer (18) (c) forming an insulating layer (26) at the surface (12)   of the semiconductor body (10), above the epitaxial layer   simulated xiale (18), at a point between the source (22) and drain (24) regions, and (d) forming metallized zones (28, 30, 32) operatively connected, respectively, to the region of source (22),   to the drain region (24) and the insulating layer (26).   2. Method according to claim 1, characterized in that the step of forming the simulated epitaxial layer (18) further comprises a step of heating the semiconductor body (10) to a temperature lower than that where there occurs a significant diffusion of the implanted impurities, to repair the damage to the network and activate the implanted impurities, this step being carried out before the step of heating the semiconductor body (10) to   cause the diffusion of the implanted impurity.