GB2056765A - Fabrication of a semiconductor device in a simulated epitaxial layer - Google Patents
Fabrication of a semiconductor device in a simulated epitaxial layer Download PDFInfo
- Publication number
- GB2056765A GB2056765A GB8013170A GB8013170A GB2056765A GB 2056765 A GB2056765 A GB 2056765A GB 8013170 A GB8013170 A GB 8013170A GB 8013170 A GB8013170 A GB 8013170A GB 2056765 A GB2056765 A GB 2056765A
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- GB
- United Kingdom
- Prior art keywords
- epitaxial layer
- semiconductor body
- simulated
- simulated epitaxial
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 238000009792 diffusion process Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 25
- 238000010438 heat treatment Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- -1 boron ions Chemical class 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000009850 completed effect Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000005019 vapor deposition process Methods 0.000 description 2
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000005049 silicon tetrachloride Substances 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Ceramic Engineering (AREA)
Abstract
A simulated epitaxial layer 18 is formed at the surface of the semiconductor body by implanting impurities, of a conductivity determining type opposite to the conductivity type of the body, into the body to a depth below the surface of the body less than the desired thickness of the simulated epitaxial layer. The body is then heated to a temperature above the diffusion temperature of the implanted impurity. The application of heat is terminated after the implanted impurity has diffused to a distance below the surface of the semiconductor body approximately equal to the desired thickness of the simulated epitaxial layer. Designated areas of the simulated epitaxial layer are doped to alter the conductivity thereof to form source and drain regions 22, 24. An insulating layer 26 is formed on the surface of the semiconductor body above the channel region. Metallized areas 28, 30, 32 are formed over the source and drain regions and the insulating layer, respectively, to act as electrodes. <IMAGE>
Description
SPECIFICATION
Fabrication of a semiconductor device in a simulated epitaxial layer
The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabrication of monocrystalline semiconductive materials having a simulated epitaxial layer therein produced by ion implantation.
The use of epitaxial layers in the fabrication of semiconductor devices and integrated circuits has been an industry-wide practice ever since such devices have been commercially produced. A variety of different processes have been utilized to form epitaxial layers. In one commonly used method, the substrate surface is first carefully prepared in order to remove contaminants on an atomic scale and to provide a crystallographically oriented surface having an exceptional degree of planarity. However, even with the most careful surface preparation, the initial characterized by lattice dislocations and other imperfections.
After suitable surface perparation, the layer is grown by a vapor deposition process. Vapor deposition of silicon may be achieved by the hydrogen reduction of silicon tetrachloride, trichlorosilane or silane at temperatures around 1 000 C. The flow rates and reactant ratios are usually quite critical to the process, as is the accurate control of temperature during the deposition process. Moreover, careful control over the doping levels introduced during epitaxial deposition is essential.Because of the delicate nature of the vapor deposition process, yields obtained in the production of epitaxial wafers tend to be low, in large part because of crystal lattice imperfections and the lack of uniform thickness in the epitaxial layer from wafer to wafer and from place to place on individual wafers. for this reason, the cost of epitaxial wafers tends to be relatively high. Since the epitaxial wafers are the raw materials from which semiconductor devices and integrated circuits are fabricated, the cost of the end products is likewise increased.
In addition, there is a trend in the industry towards the use of thinner epitaxial layers.
The need has recently arisen for epitaxial thicknesses of a few microns or less. However, uniform epitaxial layers as thin as this are difficult to produce by vapor deposition techniques and the production of epitaxial layers of one micron thickness by conventional methods may never be realized on a commercial basis.
It is, therefore, a prime object of the present invention to provide a method of fabricating a semiconductor device in a semiconductor body having a simulated epitaxial layer.
It is still a further object of the present invention to provide a method for forming a semiconductor body with a simulated epitaxial layer which is substantially less expensive than a corresponding product fabricated by conventional processes.
It is a still further object of the present invention to provide a method of forming a simulated epitaxial layer on a semiconductor body which may have a thickness of a few microns or less.
In accordance with the present invention, a method of fabricating a semiconductor device in a semiconductor body of a given conductivity type is provided. The method includes the step forming a simulated epitaxial layer of a given thickness below the surface of the semiconductor body. The simulated epitaxial layer is formed by implanting impurities, of a conductivity determining type opposite to the conductivity type of the body, into the body to a depth below the surface of the body less than the desired thickness of the simulated epitaxial layer. Thereafter, the semiconductor body is heated to a temperature above the temperature wherein substantial diffusion of the implanted inpurities occurs.The application of heat to the semiconductor body is terminated after the implanted impurities have diffused to a distance below the surface of the semiconductor body approximately equal to the desired thickness of the simulated epitaxial layer. Designated areas of the simulated epitaxial layer are then doped, to alter the conductivity thereof, to form source and drain regions within the simulated epitaxial layer.
An insulating layer is formed on the surface of the semiconductor body above the simulated epitaxial layer at a point between the source and drain regions. Thereafter, areas above the source and drain regions and the insulating layer, respectively, are metallized to form elec trodes.
It is preferable to cure lattice damage and activate the implanted impurities prior to heating the semiconductor body to diffuse the implanted impurity. This procedure comprises an additional heating step wherein the semiconductor body is heated to a temperature less than the temperature wherein substantial diffusion of the implanted impurities occur to cure lattice damage and activate the implanted impurities.
Preferably, implantation of the impurities takes place through a thin oxide layer, formed on the surface of the semiconductor body.
Implanting through a thin oxide layer eliminates surface damage which normally occurs when implanting impurities at high acceleration energies.
To the accomplishment of the above and to such other objects as may hereinafter appear, the present invention relates to a method of fabricating a semiconductor device in a semiconductor body having a simulated epitaxial layer, as described in the following specification and taken together with the accompanying drawings, wherein like numerals refer to like parts, and in which::
Figure 1 is a cross-sectional view of a semiconductor body as it is prepared to undergo the process of the present invention;
Figure 2 is a cross-sectional view of the semiconductor body after impurities have been implanted below the surface thereof;
Figure 3 is a cross-sectional view of the semiconductor body as it appears after the simulated epitaxial layer has been formed in accordance with the present invention;
Figure 4 is a cross-sectional view of the semiconductor body after source and drain regions have been formed in the simulated epitaxial layer;
Figure 5 is a cross-sectional view of the semiconductor body as same appears after the gate insulation has been formed on the surface thereof; and
Figure 6 is a cross-sectional view of the completed semiconductor device.
The present invention is applicable to the fabrication of semiconductor devices in semiconductor bodies of a variety of known semiconductor materials such as silicon, germanium, gallium arsenide and gallium arsenide phosphide, for example. Suitable conductivity type determining impurities for implantation in each of the various types of semiconductor materials are well known in the art as are the diffusion coefficients for the various impurities. For purposes of illustration, the present invention will be illustrated by an example wherein N-type silicon is implanted with boron ions to form a p-type simulated epitaxial layer.
However, it should be understood that these materials are chosen for purposes of illustration only and that the present invention is not to be construed as being limited to same.
In addition, the example of the method of the present invention which has been chosen for purposes of illustration teaches the formation of a simulated epitaxial layer of approximately 12 micron thickness. Implantation energies, impurity dosage and diffusion parameters have been selected accordingly. It should be appreciated, however, that these values are determined in accordance with the materials selected, the impurity implanted, and the particular depth of the simulated epitaxial layer desired, and should not be construed as a limitation on the present invention.
As illustrated in Fig. 1, the process starts with a body or wafer of n-type silicon 10 having a substantially planar surface 12. It is preferable to thermally oxidize body 10 to produce a relatively thin silicon dioxide layer 14 across the entire surface 12 thereof. Preferably, silicon dioxide layer 14 is approximately 500 Angstroms thick. The purpose of silicon dioxide layer 14 is to prevent physical damage to the surface 1 2 of body 1 0 which normally occurs during ion implantation at high acceleration energies.
Without any photolithographic masking op
erations, the entire surface area of the semi
conductor body 10 is implanted with an im
purity which has a conductivity determining
type which is opposite to the conductivity type of body 10. For example, boron, which
will result in a p-type layer, may be utilized. A
typical implant dose of 3.0 x 1 012/Cm2 at
approximately 200 Kev. has proved suitable.
The boron is implanted to a depth below surface 1 2 of body 14 which is substantially
less than the desired thickness of the simu
lated epitaxial layer. For the implantation pa
rameters set forth above, the boron implant
will have a peak concentration of approxi mately .02 microns below surface 12 with a
lower boundary or periphery approximately
.05 microns below surface 12. The body thus
appears as illustrated in Fig. 2 with the im
planted boron layer being denoted by numeral 16.
After the implantation step has been com
pleted, the semiconductory body is cleaned
with hot sulphuric/nitric acid and rinsed with
deionized water. The cleaned semiconductor body is then preferably subjected to a short
heat treatment for approximately 30 minutes
at 950 C to cure the lattice damage and
activate the implanted boron ions. It should
be noted, that the heat treatment to cure lattice damage and activate the implanted
impurity takes place at a temperature which is
substantially less than the temperature at
which substantial diffusion of the implanted
impurity takes place. In this case, since boron has a diffusion temperature of approximately 1 200on, a temperature substantially below
this value has been selected.
The semiconductor body is now subjected
to an extensive heat treatment which lasts
approximately 12 hours at approximately 1 200 C, in an oxidizing ambient consisting of 02 alone or in combination with nitrogen, to
cause substantial diffusion of the implanted
boron ions. The parameters of this diffusion
step are selected in accordance with the de
sired impurity surface concentration and the
desired thickness of the simulated epitaxial
layer which is formed. The parameters se
lected for the purposes of illustration will result in a simulated epitaxial layer approxi
mately 12 microns thick. The semiconductor
body then appears as illustrated in Fig. 3,
wherein numeral 18 denotes the simulated
epitaxial layer formed in accordance with the present invention.
After simulated epitaxial layer 18 has been
formed, below surface 12 of semiconductor
body 10, the semiconductor body 10 is proc
essed in a conventional manner to fabricate a
semiconductor device therein. By conventional
photolithographic techniques, a mask 20 is
formed on the surface 12 semiconductor body
10 with openings above the portions of simu
lated epitaxial layer 18 where source and
drain regions are to be formed. The source 22 and drain 24 regions are then formed in simulated epitaxial layer 18 in any known manner such as by diffusion or ion implantation of an n-type dopant. After the formation of the source 22 and drain 24 regions, the semiconductor body 10 appears as shown in
Fig. 4.
After the source 22 and drain 24 regions have been formed, mask 20 is removed and a relatively thin insulating layer composed of silicon dioxide or the like is grown or deposited on surface 12 of semiconductor body 10.
Thereafter, by a second conventional photolithographic process, the insulating layer is removed from all areas of surface 12 except for the area above the channel of the semiconductor device which extends between the source 22 and drain 24 regions. In this manner, the gate insulation 26 is formed. The semiconductor body then appears as shown in
Fig. 5.
The semiconductory body is then subjected to a metallization process where a thin layer of metal is deposited on the surface of the body and thereafter selectively removed, by a third conventional photolithographic process, so as to form a source electrode 28 above source region 22, a drain electrode 30 above drain region 24 and a gate electrode 32 on the top surface of insulating layer 26. Leads may then be connected to the electrodes. The semiconductor body now appears as shown in Fig. 6.
It will now be appreciated that the semiconductor device fabricated by the process of the present invention is identical to corresponding devices fabricated on semiconductor bodies where the epitaxial layer is formed by a conventional technique, except that in the method of the present invention, the source and drain regions are formed in a simulated epitaxial layer created by ion implantation and diffusion, instead of by conventional chemical vapor deposition techniques. The simulated epitaxial layer thus formed has the identical physical and electrical properties of an epitaxial layer formed by conventional vapor deposition techniques, but the need for careful surface preparation of the substrate, critical monitoring of flow rates reactant ratios and temperature, as in the conventional chemical deposition processes, is eliminated. The simulated epitaxial layer formed by the process of the present invention has a more uniform depth, more uniform doping and a greater degree of crystallographic perfection than is normally obtainable by conventional techniques. In addition, the entire process for forming the simulated epitaxial layer can be performed with conventional ion implantation equipment. It is also possible, utilizing the method of the present invention, to provide a simulated epitaxial layer which is thinner than those which can be produced with conventional techniques.
Claims (2)
1. A method of fabricating a semiconduc- tor device in a semiconductor body of a given conductivity type characterized by:
(a) forming a simulated epitaxial layer (18) of given thickness below the surface of the semiconductor body by:
(i) implanting impurities of a conductivity determining type opposite to the conductivity type of the body, into the body (10) to a depth (16) below the surface (14) of the body (10) less than the desired thickness of the simulated epitaxial layer (18),
(ii) heating the semiconductor body (10) to a temperature above the temperature wherein substantial diffusion of the implanted impurities occur, and
(iii) terminating the application of heat to the semiconductor body (10) after the implanted impurities have diffused to a distance below the surface of the semiconductor body approximately equal to the desired thickness of the simulated epitaxial layer (18),
(b) doping designated areas (22, 24) of the simulated epitaxial layer (18) to alter the conductivity thereof to form source (22) and drain (24) regions within the simulated epitaxial layer (18);
(c) forming an insulating layer (26) on the surface (12) of the semiconductor body (10) above the simulated epitaxial layer (18) at a location between the source (22) and drain (24) regions; and
(d) forming metallized areas (28, 30, 32) operably connected to the source (22) and drain (24) regions and to the insulating layer (26), respectively.
2. The method of Claim 1, characterized in that the step of forming the simulated epitaxial layer (18) further comprises the step of heating the semiconductor body to a temperature less than the temperature wherein substantial diffusion of the implanted impurities occurs to cure lattice damage and to activate the implanted impurities, said step of heating the semiconductor body to cure lattice damage and to activate the implanted impurities taking place prior to the step of heating the semiconductor body to cause diffusion of the implanted impurity.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US6768679A | 1979-08-20 | 1979-08-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB2056765A true GB2056765A (en) | 1981-03-18 |
Family
ID=22077689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8013170A Withdrawn GB2056765A (en) | 1979-08-20 | 1980-04-22 | Fabrication of a semiconductor device in a simulated epitaxial layer |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5630766A (en) |
| CA (1) | CA1131797A (en) |
| DE (1) | DE3027197A1 (en) |
| FR (1) | FR2463825A1 (en) |
| GB (1) | GB2056765A (en) |
| IT (1) | IT1147064B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2156383A (en) * | 1984-02-06 | 1985-10-09 | Plessey Co Plc | Infra-red material structures |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02109158U (en) * | 1989-02-10 | 1990-08-30 | ||
| JPH0338044A (en) * | 1989-07-05 | 1991-02-19 | Toshiba Corp | Manufacture of semiconductor device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL302630A (en) * | 1963-01-18 | 1900-01-01 | ||
| US3810791A (en) * | 1970-08-03 | 1974-05-14 | Texas Instruments Inc | Process for the fabrication of semiconductor materials |
| US3876472A (en) * | 1974-04-15 | 1975-04-08 | Rca Corp | Method of achieving semiconductor substrates having similar surface resistivity |
| US3945856A (en) * | 1974-07-15 | 1976-03-23 | Ibm Corporation | Method of ion implantation through an electrically insulative material |
| JPS6051275B2 (en) * | 1975-10-30 | 1985-11-13 | ソニー株式会社 | Manufacturing method of semiconductor device |
| US4055884A (en) * | 1976-12-13 | 1977-11-01 | International Business Machines Corporation | Fabrication of power field effect transistors and the resulting structures |
-
1980
- 1980-03-24 CA CA348,272A patent/CA1131797A/en not_active Expired
- 1980-04-22 GB GB8013170A patent/GB2056765A/en not_active Withdrawn
- 1980-06-23 FR FR8013899A patent/FR2463825A1/en active Granted
- 1980-07-18 DE DE19803027197 patent/DE3027197A1/en not_active Withdrawn
- 1980-07-23 JP JP10001280A patent/JPS5630766A/en active Pending
- 1980-08-14 IT IT49502/80A patent/IT1147064B/en active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2156383A (en) * | 1984-02-06 | 1985-10-09 | Plessey Co Plc | Infra-red material structures |
Also Published As
| Publication number | Publication date |
|---|---|
| CA1131797A (en) | 1982-09-14 |
| DE3027197A1 (en) | 1981-03-19 |
| IT8049502A0 (en) | 1980-08-14 |
| FR2463825B1 (en) | 1982-12-10 |
| IT1147064B (en) | 1986-11-19 |
| JPS5630766A (en) | 1981-03-27 |
| FR2463825A1 (en) | 1981-02-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |