JPS61135166A - Manufacture of schottky barrier gate type field-effect transistor - Google Patents

Abstract

PURPOSE:To form a MESFET consisting of an N type operating layer and an N<+> layer by shaping an ion implantation layer of tin or tellurium to the surface of a compound semiconductor crystal wafer containing a gate-electrode forming region, thermally treating the whole and forming a Schottky electrode. CONSTITUTION:A photo-resist film 2 as an implantation mask is shaped selectively on the one surface side of a semi-insulating GaAs crystal wafer 1, and Sn<+> 3 ions are implanted. The photo-resist film 2 is removed, WSi4 as a Schottky gate metal is applied, and Si<+> 5 ions are implanted while using a WSi gate 4 as a mask to form a high-concentration implantation layer 19. An SiOxNy film 6 is applied on the whole surface of the semi-insulating GaAs crystal wafer 1 containing WSi 4, and both surface sides of the semi-insulating GaAs crystal 1 are thermally treated by projecting rays 7 to shape an N type operating layer 8 and an N<+> layer 9. Accordingly, characteristics can easily be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a Schottky contact gate! &1 field effect transistor (hereinafter referred to as MliSfI'ET), particularly relates to a method for manufacturing a compound semiconductor MESFET.

[Conventional technology]

Logic elements and memory elements hidden in electronic counters are currently manufactured using silicon crystal as element material, but compound semiconductor crystals such as GaAs have electron mobility several times higher than silicon crystals. Due to its unique characteristics, it is expected to be used as a semiconductor crystal for future high-performance logic and memory devices. These high-performance logic elements and memory elements require field effect transistors (ME8F) with high transconductance (Jlm) and shallow threshold orthovoltage (Vt).
ET) is essential.

In the conventional manufacturing method of compound semiconductor MB8FET, silicon (8i), a light element with a small thermal diffusion coefficient, is ion-implanted into the surface of a compound semiconductor crystal to form an n-type operating layer. In such conventional 81 injection M18FE'r, it is necessary to form a shallow and high electron concentration distribution in order to obtain high Jm% properties.

For this purpose, it is necessary to form an n-type active layer with the implantation energy of the implantation 8i+ as low as possible.

[Problem that the invention seeks to solve]

However, the implantation energy of F31+ is 30ke! 8i+ implanted Ga with n-type active layer reduced to about V
The Aa MESFET has a problem in that its JFm does not increase but rather decreases. The reduction in jIm of GaAs MESFETs due to low-energy 8i+ implants was particularly significant for MESFETs with Vt near Ov, which are used to operate the logic/memory devices at low power consumption.

The impurity constituting the n-type active layer is the above-mentioned tellurium (T).
e) etc. are known. Of these, forming the active layer of a MESFET by ion implantation of S or 8e is often done, but sufficient device characteristics to satisfy are not achieved with Si.
＋ Similarly, it was not obtained. In addition, there are many reports on ion implantation in an+ and Te as a means of investigating the nature of the damage itself, focusing on the large implantation damage that occurs due to their high mass (for example, T, αF 1nst
ad, etc.

al, F'hys, 5lat, 8o1 (a) 25
, P., 515 (1974)) was never ion-implanted to form a MESFET operating layer. First of all, the reason for this is that Sn/Te is a high-quality T7C element, so it is difficult to recover from the crystal damage that has occurred. I had to. (L.K., Surr.
idge, etc.

al l In5 (Phys Conf Set, N
o, 3aat p, 16.1 (1977)),
The 21st 8n'' r T6+, like S+ and 8e'', undergoes significant thermal diffusion, and the electron concentration distribution formed by ion implantation expands (F,) LEisen.

ef, al, e 5olid-8f, gleot
This was because there were many difficulties in implementing it as an operating layer for ME8FET, such as ronics e 20* P219 (1977)).

An object of the present invention is to provide a method for manufacturing a MESFET consisting of an n-type operating layer and a 1+ layer formed by ion implantation and having a shallow and high electron concentration distribution that can obtain a high Jm even at a Vt near Ov. do.

(Means for Solving the Intermediate Point) The present invention provides tin (8n) or Te/L//L on the surface of a compound semiconductor crystal wafer including at least a gate electrode forming region.
/ (Te) o Maximum concentration is 2.4 x 10”c
! A step of forming an ion implantation layer of L-" or less, a step of selectively ion-implanting donor impurities at a high concentration into the surface of the compound semiconductor crystal in the source and drain electrode forming regions, and an infrared lamp annealing step of 850° C. or higher. The disadvantage is that it includes a process of performing heat treatment and a process of forming gate electrodes and source-drain electrodes.

According to the eighth aspect of the present invention, an epitaxial growth layer may be formed instead of implanting impurity ions at a high concentration into the surface of the compound semiconductor crystal in the source and drain electrode forming regions.

[Effect]

First, the actions and effects of Sn and Te that are ion-implanted to form the active layer will be explained. In general, it is known that the average implantation depth Rp of impurities obtained by ion implantation is not shallow for high-mass ions, and the standard deviation σ8 of the implantation depth, which indicates distribution variation, is also small. There is. Therefore, Rp and σ8 in an+ and Te, whose mass is more than 4 times larger than zero i, are calculated to be 1 of that of Si+ with the same implantation energy.
73, and a shallower and steeper electron concentration distribution can be expected.

In general, MESFBTOVt and ym6'i electron concentration N.

There is a relationship between the thickness of the active layer and the mobility M.

VtoeND” (1)ym a
c M h L2) Therefore, even if the Vt value is the same, the smaller D is, that is, the shallower the active layer is formed, the higher N can be made, and as a result, 1 m can be increased. Therefore, the ym of the Sn+-implanted ME8FET, which has an active layer formed by ion-implanting high-mass ann and Te, is about three times as large as the flm of the 8i+-implanted ME8FET, which is implanted with the same energy. .

However, if only to obtain a shallow active layer, the implantation energy of 81+ can be lowered, but as shown in Part 3 @ta), the S1+ implanted MESFET with low energy implantation
It has been found from experiments that the pm does not necessarily increase.

As can be seen from this figure, in the case of Si + implanted MhSFET, when the implantation energy is lowered to about 30 keV, Vt ~
Jam near 0 oath has become smaller than when it was 50 keV. However, the 8n ten-pressure injection E8F according to the present invention
In ET, the implantation energy was set to 30k as shown in Figure 3(b).
It was found that even if the voltage is lowered to about eV, the 9m around Vt-0v increases.

This is a feature found in MESFETs using ion implantation of high mass elements such as 8n''+T6.

8" necessary for obtaining the effect of the present invention on the arrow.

The injection conditions ζ for Tc+ will be explained below. Figure 3(b)
From the implantation energy dependence of Jam in the Sn-doped MESFET shown in Figure 2, the effect of lowering the implantation energy in the range of q < 0 to -〇, 5V, as described above, can be seen.
It has been found that at a deep Vt of about -1.0 V, the lower the implantation energy, the more the ymo decreases. The cause of this is that at the same implantation energy, Vt
In order to deepen the value, it is necessary to implant at a high dose, so the implantation damage is correspondingly large, and even after heat treatment, it is thought that the activation rate and movement of JK were lowered due to the loss of hot water.

Based on numerous experimental results, the conditions for Sn''+'re+ implantation that avoid the 9m drop that is thought to be caused by the large crystallization loss are as follows: the maximum impurity concentration is 2.4X as in the present invention.
It was found that it is best to set the distance to 10"cm or less.

In short, we will explain the heat treatment conditions for an integrated crystal in a compound in which 8n+ or Te is injected at ten pressures. It has already been explained that the concentration distribution of an and Te in the injection layer is wider than the concentration distribution obtained by theoretical calculation, but it has been found that such diffusion of 8rl+ and Te+ can be prevented by performing infrared lamp annealing.

Infrared lamp annealing, as already known, is a heat treatment method in which a compound semiconductor is irradiated with infrared rays to heat the semiconductor crystal. By using such infrared lamp annealing, it is possible to suppress the diffusion of impurities, such as sulfur, which cannot be diffused in GaAs (M. Kuzhara, at
, al., J., Appl., Phys., +54 eP.
, 3121 (1983)). It was confirmed that when 8n+ and Te+ are subjected to a relatively short heat treatment using an infrared lamp as in the present invention, a steep electron concentration distribution close to that calculated by theory can be obtained.

As in the present invention, the heat treatment temperature is required to be at least 850''C or higher, and if it is lower than 850C, the activation of the implanted impurity is insufficient.

As explained above, in the present invention, a compound semiconductor is implanted under ion implantation conditions such that the maximum concentration of Sn+ or Te+ does not exceed 2.4X10"cm+, which makes it easy to obtain essentially a shallow implanted layer. By combining the step of implanting into the crystal surface and the step of heat treatment at 850° C. or higher using an infrared lamp to suppress the diffusion of the implanted impurities, an active layer having a shallow and steep electron concentration distribution can be easily obtained. There was a problem with the rough Si+ MESFET.
This has the effect of preventing a decrease in Ji+m near ~Ov.

Finally, an explanation will be given of the effect of the N+ type epitaxial layer formed in the source and drain regions after N+ type ion implantation or N+ type epitaxial layer. In the above equation (2), IIm==Mff
I have described the relational expression. This equation (2) ignores the influence of the source series resistance R8, but in reality, for n-type operation near Vt=Ov, the influence of R3 cannot be ignored. Iim when Rs = O is jTmo
Then, the adjusted 1m satisfies the following formula: 1m = #mO/(1+RsJiFmo) (
3) Therefore, reducing Rs will reduce the MESFET's p
This has the effect of increasing m. In order to reduce Rs, it is preferable to form a high concentration, low resistance layer in both the source and drain electrode regions. The N intermediate layer formed by selectively ion-implanting donor impurities at a high concentration of the present invention or the N intermediate layer formed by epitaxial growth has the effect of reducing the series resistance R8 of the source.

〔Example〕

Let us now briefly describe embodiments of the present invention in detail.

First, in an embodiment of the present invention, GaAs is used as a compound semiconductor.
This will be explained with reference to the drawings, taking Sn+ as an example of implanted ions.

FIG. 1 is a cross-sectional view of a GaAs crystal wafer at each step for explaining an embodiment of the present invention. In Figure 1 (
In a), a photoresist film 2 serving as an implantation mask is selectively formed on one side of a semi-insulating GaAs crystal wafer l, and 8n"3 is injected into 4XIO" pieces at 0 keV.
This shows how ions are implanted by d. At this time, injection layer 1
The highest Sn concentration in No. 8 was 1.65 x 1 o”cR-
1 (bJ) After removing all the photoresist film 2, WSi2, which is a silicon gate metal, is deposited to a thickness of 0.5μ, and then using the W8i gate 4 as a mask, Si+5'F- 4 X I O”ca with 100ke■
This figure shows how a high-concentration implantation layer 19 is formed by implanting t-'' ions. FIG. This figure shows how the n-type active layer 8 and the N-type layer 9 were formed by two heat treatments by irradiation with infrared rays 7.The heat treatment with infrared rays was performed at 950°C;
I did 8 in 4 seconds. FIG. 1(d) shows a sealed barrier gate field effect transistor in which a source IE electrode 10 and a drain electrode 11 are formed on the 9N layer 9 by the usual alignment method after removing the 8i0xNy film. show.

FIG. 2 is a diagram for explaining another embodiment of the present invention, and is a cross-sectional view of a G@A3 crystal wafer at each step. FIG. 2(a) shows how a photoresist film 2 serving as an implantation mask is selectively formed on one side of a semi-insulating aGaAs crystal wafer 1, and Sn"3 is ion-implanted by 4XlO" pieces 1d at 70 keV. .

At this time, the maximum value of 5nWk degree of the injection layer 18 is 1.65X
10"" art-3. FIG. 1 (bJ is 8i0xNy after completely removing the photoresist film 2.
Temporarily adhere a film (refractive index 1, 75) 6 with a thickness of 0.1 μm,
A state in which an n-type operating layer 8 is formed by heat treatment by irradiating infrared light #M7 using an infrared lamp is shown. The heat treatment conditions are the same as in Figure 1erj)6o gzFigure (C)4t8i0x
After removing the Ny film 6, WSi4 was deposited on the gate ta to a thickness of 0.5 μm, and further MOCVD (:M
etalOrganic Chemical Va
pow Deposition)) trimethylgallium and AsH. Si-doped n” as a source
- GaAs N (thickness 0.4 μm) 12 to 650
This figure shows selective epitaxial growth on the source and drain electrodes at ℃. The Si concentration is 1. 2 x 1
It is 0"cm7". FIG. 2(d) shows a sheet Km formed by forming a source electrode 10 and a drain electrode 11 on N''-GaAs 12 using the usual alignment method.
Figure 3 shows a gate m field effect transistor.

〔Effect of the invention〕

The Sigitky barrier gate field effect transistor according to the present invention is a GaAs MESF'ET described in the embodiment.
An average of 230 m8/W (Vt~Ov) was obtained for both at 9 m. This value is 8i for the same FgT structure with the same Yt.
+ Injection ME8 FIT cD 11m O with a good value of about 1,4 times larger R. This is the result of the reduction effect. In this way, the present invention can easily improve properties that could not be achieved with conventional methods. In addition, if Sn+ is explained in the above-mentioned example, T
Similar effects have been obtained with e+. Furthermore, the idea of the present invention is that np, In()aAl, GaAlAs5I
It goes without saying that the present invention can also be applied to other compound semiconductor crystals such as nGIAsP.

[Brief explanation of the drawing]

FIGS. 1(a) to (d) are process sectional views showing one embodiment of the present invention, FIGS. 2(a) to (dl are process sectional views showing another embodiment, and 1 is a semi-insulating G aA s wafer, 3
is 8n ion, 4 is W8i film, 5 is 8i ion, 6 is 8i0XNY film, 7 is infrared radiation, 8 is n-type active layer, 9 is N
In the middle layer, 10 and 11 indicate an n source electrode and a drain electrode, respectively, and 18 indicates an injection layer. Figure 3 shows the Si+ injection MBSFET<81+ of the present invention.
In the diagram comparing Jilm of ME81i'ET (b), the horizontal axis shows the implantation energy and the threshold l ortho voltage Vt is taken as a parameter. Figure 1 Figure 2 Note X Energy hav Figure 3 Main input energy, KtV

Claims (1)

[Claims] forming a tin or tellurium ion implantation layer on the surface of the compound semiconductor crystal wafer including at least the gate electrode formation region;
A method for manufacturing a Schottky barrier gate field effect transistor, characterized in that an active layer in which a Schottky electrode is formed is formed by subsequent heat treatment.