JPH0371641A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce irregularity in FET characteristics within the surface of a wafer as well as to contrive the improvement of the gate breakdown strength characteristics of a FET by a method wherein hydrogen electrons are diffused in an ion-implanted layer and a heat treatment is performed. CONSTITUTION:Si<+> ions are implanted in a semi-insulative GaAs substrate 1 using a resist 2 as a mask and an ion-implanted layer 3 is formed. Then, after the resist 2 is removed and an SiN film 4 is formed on the whole surface of a wafer, a resist 5 is formed and source and drain regions 6a and 6b are formed using this resist 5 as a mask. Moreover, the resist 5 is etched, an SiO2 film 7 is deposited on the whole surface of the wafer and the resist 5 is removed. Thereby a gate opening part 7' is formed at a position, where corresponds to a scheduled gate electrode region site 5 ', on the film 7 and after then, the layer 3 and the regions 6a and 6b are activated by a short-time annealing. Thereby, irregularity in FET characteristics within the surface of the wafer can be lessened and the improvement of the gate breakdown strength characteristics of a FET is contrived.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method of manufacturing a field effect transistor.

(b) Conventional technology Many compound semiconductor devices, including GaAs, have excellent characteristics in terms of high-speed operation and low power consumption, and research into ultra-high-speed and ultra-high frequency integrated circuits is being conducted in various forms. It is.

In the case of a Ga, As integrated circuit, high performance of the MESFET that constitutes the integrated circuit is essential for its high performance. One of the effective ways to improve the performance of G a As M E S F E T is to make the active layer thinner and more concentrated, which is expected to improve mutual conductance (g) and suppress short channel effects. can.

In addition, ion implantation is widely used to form the active layer in consideration of cost, controllability, and uniformity, and in recent years, low-energy, high-dose implantation has been used to achieve high-concentration thinning of the active layer. It has been reported that an extremely high performance MESFET with ,g,=630mS/Ioffi was obtained (K,0noderaet al, IEEE T
rans, Electron Devices L
etters v.

1.9 No, 8 1988 P, 417-P, 4
(see 18).

However, in order to achieve thinning of the active layer by ion implantation, it is necessary to lower the implantation energy. In implantation, there is a problem that the stability of the ion beam deteriorates, the FET characteristics vary within the plane, and there is also a problem that the gate breakdown voltage characteristics deteriorate as the layer becomes thinner with high concentration.

(c) Problems to be solved by the invention Achieving high concentration and thinning of the active layer by ion implantation, ~IES
When manufacturing FETs, there are problems in that the stability of the ion beam decreases due to the lowering of the implantation energy, the FET characteristics vary within the plane, and the gate breakdown voltage characteristics deteriorate as the concentration of the active layer increases. .

(D) Means for Solving the Problems The present invention includes the steps of forming an ion implantation layer on a semiconductor substrate, diffusing hydrogen atoms into the ion implantation layer, and heat treating the ion implantation layer. 1 is a method of manufacturing a field effect transistor, characterized in that the method includes the steps of:

(e) Action It is known that by diffusing hydrogen into semiconductors such as QSi and GaAs through hydrogen plasma treatment, donors in the semiconductors are inactivated (S, J, Pea
rtonet al, J, Appi, Phys, 59
, 1986. (See P, 28212827).

The inventor of the present application has demonstrated that by subjecting the ion-implanted layer to this hydrogen plasma treatment, when the donor is first inactivated and then reactivated by heat treatment, the area near the implantation range is approximately 1
We have discovered a phenomenon in which the reactivation rate is low at the surface and tail parts, whereas the reactivation rate is 00%. The present invention is based on this phenomenon and thins the injection profile.
It is possible to use higher implantation energy than conventional methods and to reduce the carrier concentration near the surface.

(1) in Figure 2 shows Si' on a semi-insulating GaAs substrate.
''Ion at 100KeV, 1,8xlO'1cm-'
This is the implanted carrier profile of sample A, which was implanted at 850° C. and activated by short-time annealing for 5 seconds.

Further, (2) in FIG. 2 is an injection carrier profile of sample B, which was obtained by subjecting sample A to hydrogen plasma treatment for 15 minutes at a substrate temperature of 220° C. using an ECR plasma device.

Furthermore, (3) in Figure 3 shows that sample A has 5
This is the injection carrier profile of sample C after heat treatment at 00° C. for 10 minutes.

It can be seen that sample C, which has been subjected to the hydrogen plasma treatment and heat treatment steps, has a thinner injected carrier profile and a lower carrier concentration on the surface.

Further, even when the treatment time of the heat treatment after the hydrogen plasma treatment is set to 12 hours, the same injection carrier profile as in (3) can be obtained.

(F) Example A case in which the method of the present invention is applied to a GaAs MESFET will be explained using FIGS. 1(a) to (j).

First, Si'' ions were applied to a semi-insulating GaAs substrate (1) at 35 KeV using a resist (2) as a mask.

1°; > X 10 "cm-" to form an ion implantation layer (3) (FIG. 1(a)). At this time 35K
If the implantation energy is on the order of eV, an ion beam can be stably extracted even with a 200KeV class implantation device.

After removing the resist (2) and depositing a SiN film (4) of 300λ on the entire surface of the wafer by ECR plasma CVD, a resist (5) is formed. At this time, the width of the constant portion (5°) of the gate electrode formation 7 was set to 0.5 μm.

Using this resist (5) as a mask, one Si" ion was
A source region (6a) and a drain region (6b) are formed by implanting at 00 KeV and 3×10′″cm −’ (FIG. 2(b)).

Etching the resist (5) using oxygen plasma,
The width of the part (5') is 0.25 μn1 (see the same figure (
C)).

SiQ is deposited on the entire surface of the wafer using the ECR plasma CVD method.

By depositing 300 films (7) and removing the resist (5), a gate opening (7') was formed at a position corresponding to the part (5') of the film (7). Thereafter, the ion-implanted layer (3) and regions (6a) and (6b) are activated by short-time annealing using a halogen lamp at 880° C. for 5 seconds (FIG. 4(d)).

510! RI the SiN film (4) using the film (7) as a mask.
Etching is performed using E to remove the above-mentioned portion (
After forming a gate opening (4°) at a position corresponding to 5'), ECR hydrogen plasma treatment is performed for 5 minutes. At this time, the substrate temperature was 220℃, and the hydrogen pressure was 5xlO-'Torr.
Figure (e)).

After that, heat treatment is applied for 10 minutes at 500℃ in hydrogen (
Figure (f)). As explained in the section (Function), the channel layer (active layer) (8) becomes thinner through the hydrogen plasma treatment and heat treatment steps, automatically creating an LDD structure (with a channel layer between the channel layer and the drain region). A region having a carrier concentration intermediate between that of the drain region and that of the drain region is realized.

A WSi film (9) is deposited over the entire surface of the wafer by sputtering, and a resist (10) is formed on the WSi film (9) (FIG. 2(g)).

An Au film (11) is deposited on the entire surface of the wafer, and a resist (10) is deposited on the entire surface of the wafer.
) is removed, and then W is removed using the Au film (11) as a mask.
The Si film (9) is etched ((h) in the same figure).

Applying resist (12), this resist (12) and A
St N films (4) and 5 using the u film (11) as a mask
Etch iO=QI (7) ((i) in the same figure).

By depositing an A u / Ti / P d film (13) on the entire surface and removing the resist (12), the gate electrode 8i is
(14) was completed, and in step 4, it was heated at 450℃ for 2 minutes and 3 minutes in hydrogen.
By applying Ohmive Quaalloy for 0 seconds, the source electrode (
15) and drain electrode (16) are completed (see figure (j)
)).

In the GaAs MESFET completed as described above, the peak carrier concentration of the channel layer (8) is 1.2×IQ"cm-"
Even though it has a high breakdown voltage of 8V or more, it has a high breakdown voltage of 8V or more. Also, in the characteristics of FET, g = 580
m s /rm, NFm1n=1. Very excellent characteristics of OdB were obtained. This is the channel layer (8
It is thought that this is due to the thinning of the carrier profile as well as the sharpening of the tooth hole in the carrier profile. It was also confirmed that the in-plane threshold voltage deviation was excellent, being 30 mV or less.

In this example, GaAS is used as the semiconductor substrate and S!
Although ions were implanted, InP was used as the semiconductor substrate and S
It is also possible to implant As using Si as the semiconductor substrate.
may be injected. Furthermore, high-frequency hydrogen plasma may be used instead of ECR hydrogen plasma treatment.

(G) Effects of the Invention As is clear from the above description, the present invention can reduce in-plane variations in FET characteristics by diffusing hydrogen atoms into the ion-implanted layer and subjecting it to heat treatment. Withstand voltage characteristics can be improved.

Further, by providing a protective film in areas other than the portion where the gate electrode is to be formed, and then performing hydrogen atom diffusion and heat treatment, an LDD structure can be obtained in a self-aligned manner.

[Brief explanation of drawings]

FIGS. 1(a) to (j) are process explanatory diagrams for explaining the method of the present invention, and FIG. 2 is a diagram showing an injection carrier profile. (1) ... Semi-insulating GaAs substrate, (2) (5) (1
0) (12)...Resist, (3)...Ion implantation layer, (4)...SiN film, (7)...5ins film,
(8>...Channel layer, (9)"W Si film, (
11)...Au film, (13)-A u , /Ti, /
Pd film, (14)...gate electrode, (15)...source electrode, (16)...drain electrode.

Claims (1)

[Claims] 1. The method is characterized by comprising the steps of forming an ion implantation layer on a semiconductor substrate, diffusing hydrogen atoms into the ion implantation layer, and heat treating the ion implantation layer. A method of manufacturing a field effect transistor. 2. Claim 1, further comprising the step of forming a protective film on a portion of the ion-implanted layer other than a portion where a gate electrode is to be formed.
A method for manufacturing a field effect transistor according to.