JPH0770545B2 - Method for manufacturing GaAs field effect transistor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor using compound semiconductor GaAs.

Conventional technology A Schottky gate type field effect transistor using GaAs as a semiconductor (hereinafter abbreviated as MESFET) is a conventional SiFET.
It has the advantages of high speed and low power consumption compared to, and is expected in both digital and analog IC fields. In particular, the method of forming a FET on a semi-insulating GaAs substrate by using an ion implantation method makes it easy to manufacture a FET with uniform characteristics, and recently, it is possible to reduce parasitic resistance such as source resistance. A self-aligned FET using a melting point metal gate has been developed and its performance is being improved.

However, in such a conventional GaAs MESFET, low frequency (especially
Noise increases in the region below 200MHz), making it difficult to apply to analog ICs that cover this low frequency region.

Means for Solving the Problems The present invention has been made in view of the above problems, and in manufacturing a GaAs FET, a step of heat-treating at a suitable temperature is performed after processing the GaAs surface in a gas plasma containing P (phosphorus). It is a thing.

According to the method of the present invention, GaAs is used in a gas plasma containing P.
By processing the surface, a large number of As vacancies that are present on the GaAs surface and are the source of the surface level are reduced by diffusion of P atoms, and the surface level density that is the source of noise at low frequencies is reduced. Is what you can get.

Example Hereinafter, a self-alignment type using a refractory metal gate
A FET will be described as an example. As shown in FIG. 1 (a), the semi-insulating GaAs substrate 1 is put into the chamber 20 of the plasma device, and while the heater 21 heats it at about 300 ° C., PH ₃ (phosphine) gas is caused to flow to 13.56 MHz. PH between electrodes 22 at high frequency
₃ Plasma is generated, GaAs with pressure 0.3 Torr, RF power 100W
Treat the substrate surface for about 15 minutes. By this PH ₃ plasma treatment, a P atom diffusion layer 2 is formed on the GaAs surface. Using the semi-insulating GaAs substrate treated in this way, the GaAsME is processed by the process flow shown in FIGS.
Fabricate SFET. First, as shown in FIG. 2B, Si ²⁹ ions are accelerated into a predetermined region of a semi-insulating GaAs substrate 1 having a P atom diffusion layer 2 formed on the surface thereof with a photoresist film 3 as a mask and an accelerating voltage of 30 KeV, forming a dose 8 × 10 ¹² cm ^-2 implanted well layer 4 serving as a channel region. After removing the photoresist film 3A, the WSiN (2000Å) / TaN (500Å) / Au (4000Å) is formed by the sputtering method as shown in FIG.
The three-layer film 5A is formed. Next, as shown in FIG. 3D, the photoresist film 3B is used as a mask in a predetermined region,
Ar ion milling and anisotropic plasma etching of CF ₄ / O ₂ gas are performed to form the Schottky gate electrode 5 composed of a part of the three-layer film 5A. Next, after removing the photoresist film B, Si ²⁹ ions are applied at 50 KeV, 5 × 1 in a predetermined region again using the photoresist film 3C as a mask as shown in FIG.
Implantation is performed under the condition of 0 ¹² cm ⁻² to form the n ′ layer 6 which will be a part of the source and drain. Next, after removing the photoresist film 3C, the SiO ₂ film 7 (2500
After forming Å), the photoresist film 3D is
Si ²⁸ ions as a mask through the SiO ₂ film at 160 KeV, 5
Implantation is performed under the condition of × 10 ¹³ cm ^-2 to form the n ⁺ layer 8 which will be a part of the source and drain. Next, after removing the photoresist film 3D, as shown in FIG.
Annealing is performed at 15 ° C for 15 minutes to activate the ion-implanted layer. This annealing treatment also recovers the PH ₃ plasma damage. Next, as shown in FIG.
After opening a predetermined area of the O ₂ film 7 with a hydrofluoric acid-based etching solution using the photoresist film as a mask, AuGe
After the vapor deposition, the substrate is lifted off and the source electrode 9 and the drain electrode 10 are formed by carrying out a minter at 450 ° C. for 3 minutes to manufacture a FET. FIG. 2 shows the frequency dependence of the noise figure of the FET of the present invention subjected to the PH ₃ plasma treatment shown in FIG. 1 and the conventional FET not subjected to the plasma treatment. The gate length of the FET is 1 μm, the gate width is 600 μm, and the threshold voltage is −0.9V. From the figure, it can be seen that the FET according to the manufacturing method of the present invention has a drastically reduced noise figure in the low frequency region (especially 200 MHz or less) as compared with the FET according to the conventional manufacturing method. This is because the P atom diffusion layer 2 formed by the PH ₃ plasma treatment reduces the surface state density mainly due to As vacancies near the GaAs surface between the gate and the source, and between the gate and the drain, and in the low frequency region. This is because the noise characteristic of is improved. In the above description, the PH ₃ plasma treatment is performed at the beginning of the process, but it goes without saying that the same effect can be obtained even if it is performed at the stage of (c) of FIG. 1, that is, after the gate is formed. . Further, as the PH ₃ plasma condition, if it is carried out for a too long time, the damage due to the plasma treatment becomes large on the contrary. However, when an ECR (Electron Cyclotron Resonance) type plasma device, which has recently been popularized, is used, the plasma generating portion and the substrate are located apart from each other, so that plasma processing can be performed for a longer period of time with less damage. In the above description, the case where PH ₃ gas is used has been described.
It goes without saying that the same applies when phosphorus pentafluoride (PH ₅ ) gas is used, for example. Further, as the method of manufacturing the FET, the one using the ion implantation method is described, but the manufacturing method using the epitaxial layer can be applied.
However, in this case, it is desirable to perform heat treatment at an appropriate temperature (for example, 400 ° C.) in order to recover plasma damage after the plasma treatment.

Effects of the Invention As described above, after the GaAs surface is treated in PH ₃ plasma to form a P atom diffusion layer on the surface, ion implantation is performed.
By forming a FET, it is possible to obtain a GaAs FET in which the surface state density of GaAs is reduced and the noise at low frequencies is reduced.

[Brief description of drawings]

FIG. 1 is a process diagram of a method for manufacturing a GaAs MESFET according to an embodiment of the present invention, and FIG. 2 is a diagram showing frequency dependence of noise characteristics of a GaAs MESFET according to the manufacturing method of the present invention and a conventional manufacturing method. 1 ... GaAs substrate, 2 ... P atom diffusion layer, 5 ... Gate electrode.

Claims (1)

[Claims] 1. A step of treating a GaAs substrate surface to form a P atom diffusion layer on the GaAs substrate surface in a gas plasma containing P atoms, and a step of heat-treating the P atom diffusion layer at an appropriate temperature. A method of manufacturing a GaAs field effect transistor, comprising: