JPS59119823A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59119823A
JPS59119823A JP57228403A JP22840382A JPS59119823A JP S59119823 A JPS59119823 A JP S59119823A JP 57228403 A JP57228403 A JP 57228403A JP 22840382 A JP22840382 A JP 22840382A JP S59119823 A JPS59119823 A JP S59119823A
Authority
JP
Japan
Prior art keywords
region
element forming
forming region
film
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57228403A
Other languages
Japanese (ja)
Inventor
Seiichiro Kawamura
河村　誠一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57228403A priority Critical patent/JPS59119823A/en
Publication of JPS59119823A publication Critical patent/JPS59119823A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To single-crystallize an element forming region completely by forming an insulating layer having a large thermal conductivity from among the insulating layers formed on the semiconductor substrate in the region where elements are to be formed, providing an insulating layer having small thermal conductivity in other region and irradiating the element forming region with an energy beam after forming a polycrystalline silicon layer on the insulating layers. CONSTITUTION:A silicon nitride film is formed by the growth method in the thickness of 1,000 to 2,000Angstrom on a silicon substrate 21 and the film is etched by patterning, leaving the nitride film 24 of the element forming region. Next, an oxide film 22 is formed by the growth method on the surface of silicon substrate 21 by the thermal oxidation surrounding the nitride film 24 and thereby an insulating layer can be formed. Thereafter, only the element forming region is annealed by the laser beam after the polysilicon layer is formed by the growth method in the thickness of 4,000Angstrom . After the annealing, the element forming region is cooled for single-crystallization. At this time, since the oxide film 22 has a larger thermal conducivity than that of nitride film 24, single crystallization progresses toward the oxide film 22 in both sides from the center of element forming region and thereby a perfect single crystal 23a can be formed.

Description

【発明の詳細な説明】 （１）発明の技術分野 本発明は半導体装置の製造方法、詳しくはシリコン・オ
ン・インシュレーター（ＳＯＩ＋　５ｉｌｉｃｏｎｏｎ
　Ｉｎ５ｕｌａｔｏｒ）技術における素子形成領域の単
結晶化の方法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, specifically a method for manufacturing a semiconductor device, specifically a silicon-on-insulator (SOI+) semiconductor device.
The present invention relates to a method for single crystallizing an element formation region in the In5lator technology.

（２）技術の背景 ＳＯ１技術は一様な絶縁膜上にシリコン単結晶を形成し
、当該単結晶領域に素子を形成する技術で、三次元回路
による高密度化（超ＬＳＩ　）　、薄膜トランジスタ、
その地平導体素子の改良に広い応用分野をもっている。(2) Background of the technology SO1 technology is a technology in which silicon single crystal is formed on a uniform insulating film and elements are formed in the single crystal region.
It has a wide range of applications in improving horizontal conductor elements.

本発明に係わる単結晶化技術は、上記Ｓｏｌ技術におい
て最も重要なものであり、この単結晶成長の成否が半導
体装置の特性に大きく影響する。The single crystallization technology according to the present invention is the most important one in the above Sol technology, and the success or failure of this single crystal growth greatly influences the characteristics of the semiconductor device.

単結晶化の方法には一般に加熱方法か用いられ、化学気
相成長（ＣＶＤ）法により形成された多結晶シリコン（
ポリシリコン）もしくはアモルファスシリコンをレーザ
ビームなどを使ってアニールし、次いで冷却する工程に
より行われる。しかし、現在の単結晶化技術では完全な
単結晶の成長が困難であるため、その技術が要望される
。A heating method is generally used for single crystallization, and polycrystalline silicon (
Polysilicon) or amorphous silicon is annealed using a laser beam or the like, and then cooled. However, since it is difficult to grow a perfect single crystal using current single crystallization technology, such technology is desired.

（３）従来技術と問題点 第１図は従来の単精品化技術を説明するための図で、同
図を参照するとソリコン（Ｓｉ）　基板１の表面に二酸
化シリコン（５ｉＯｚ　）　ＩＩＩ　２を例えばｉ’、
％　）！ｌ（２化により形成し、次いでポリシリコン層
３を（：　Ｖ　Ｌｌ法により成Ｊｉする。しかる後例え
ば１〕−サヒームによりポリシリコン層３の素子形成予
定領域をアニールしく同図（ａｌ）、次いで冷却するこ
とにより単結晶化する。この単結晶化された領域を同図
（ｂｌに３８で示す。(3) Prior Art and Problems Figure 1 is a diagram for explaining the conventional single-product technology. ',
%)! Then, the polysilicon layer 3 is formed by the V Ll method. Then, for example, the region where the element is to be formed in the polysilicon layer 3 is annealed using 1]-Saheem. Then, it is cooled to form a single crystal. This single crystallized region is shown at 38 in the same figure (bl).

次いで素子領域分離のため、同図（ｂ）に示す如く単結
晶化領域に窒化シリコ：／”（Ｓｉ３Ｎ　ｕ　）　　４
のパターンを通當の技術で形成し、しかる後）ｊ４５酸
化を行い分離酸化ｊ模３ｂを形成する。Next, in order to separate the device regions, silicon nitride:/''(Si3N u ) 4 is applied to the single crystallized region as shown in FIG. 2(b).
A pattern is formed using a conventional technique, and then 45 oxidation is performed to form an isolated oxidized pattern 3b.

ところで、上述の単結晶化の方法では、フレインサイズ
の多少の拡大はあるが、素子形成領域を完全に単結晶化
することができない問題がある。By the way, in the above-mentioned single crystallization method, although the grain size is increased to some extent, there is a problem in that the element forming region cannot be completely single crystallized.

ずなわら、上記レーザアニール後の冷却において、熱の
放散か方向性なく」１下四方に不規則に行われるため、
単結晶化か同時に枚数の場所で進行し、冷却後は小さな
小結晶の集合となってしまう。第１図（ｂｌには完全に
単結晶化した領域を模式的に白地で示したが、現実には
多くの場合同図（Ｃ）に破線で模式的に示す如きダレイ
ンか発生ずるのである。However, in the cooling after laser annealing, the heat is dissipated irregularly in all directions, without any direction.
Single crystallization progresses in several places at the same time, and after cooling, it becomes a collection of small crystals. In FIG. 1 (bl), a completely single-crystalline region is schematically shown on a white background, but in reality, in many cases, drain as shown schematically by the broken line in FIG. 1 (C) occurs.

このような不完全な単結晶はそこに形成される素子特性
にＨＨ＜影響ちを与え、半導体装置の信頼性を低下させ
るため、何らかの方法により熱伝導を制御して完全な単
結晶化を実現する必要かある。Such an imperfect single crystal affects the characteristics of the device formed there and reduces the reliability of the semiconductor device, so it is necessary to control heat conduction by some method to achieve perfect single crystal formation. Is there a need to do that?

（４１発明の目的 本発明は上記従来の問題点に鑑み、ｓｏｒ技術において
素子形成領域を完全に単結晶化する方法の提供を目的と
する。(41 Object of the Invention In view of the above-mentioned conventional problems, an object of the present invention is to provide a method for completely converting an element formation region into a single crystal in the SOR technology.

（５）発明の構成 そしこの目的は本発明の方法によれば、半導体基板トに
熱伝導率の異なる２種類の絶縁膜を組み合せて絶縁層を
形成し、当該絶縁層のうち熱伝導率の大なる絶縁膜を素
子形成予定領域に形成し、他の領域に熱伝導率の小なる
絶縁膜を設ける］二枚、次いで上記絶縁層上に多結晶シ
リコンＪ５を成長した後素子形成予定領域にエネルギー
線を照射し、次いて冷却して当該領域を単結晶化する工
程を含むことを特徴とする半導体装置の製造方法を提供
することによって達成され、また」１記熱伝導率の大な
る絶縁膜の厚さをこれより熱伝導インの小なる絶縁膜の
ｊ！ｆさより薄く形成することを特徴とする上記半導体
装置の製造方法によっても達成される。(5) Structure of the invention According to the method of the invention, an insulating layer is formed by combining two types of insulating films with different thermal conductivities on a semiconductor substrate, and one of the insulating layers has a lower thermal conductivity. A large insulating film is formed in the area where the device is to be formed, and an insulating film with a low thermal conductivity is provided in other areas.] Next, polycrystalline silicon J5 is grown on the insulating layer, and then in the area where the device is to be formed. This is achieved by providing a method for manufacturing a semiconductor device, which includes a step of irradiating energy rays and then cooling the region to single crystallize the region, and also achieves the following: 1. Insulation with high thermal conductivity The thickness of the film is smaller than this for thermal conduction in the insulating film j! This can also be achieved by the method for manufacturing a semiconductor device described above, which is characterized in that the semiconductor device is formed to be thinner than f.

（６）発明の実施例 以下図面により本発明実施例を説明する。(6) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

第２図は本発明実施例を説明するための図で、１ｉｊＪ
しｊを参照すると、シリコン基板２ｊ上に窒化シリ：コ
ン（Ｓｉ３Ｎｕ）膜をＣＶＤ法により厚さ１０００ない
し２０００八にｌ戊１ａし、次いでパターニングにより
素ｆ−形成予定？！Ｉ′Ｊ域部分の窒化膜２４以外をエ
ツチング除去するく同図（ａ））。FIG. 2 is a diagram for explaining an embodiment of the present invention.
Referring to Figure 1, a silicon nitride (Si3Nu) film is formed on a silicon substrate 2j to a thickness of 1000 to 2000 mm by CVD, and then patterned to form an element f-. ! The portions other than the nitride film 24 in the I'J region are etched away (FIG. 2(a)).

次いでにソシ酸化によりシリコン基板２１の表面に、」
二記輩化ｊ１ぐ２４を１川む如く酸化１次（５ｉ（ｈ　
ン　２２を１０００ないし２０００人の厚さに成長して
１つの絶縁層を形成する（　＋’＃Ｊ図（ｂＯｏこのと
き窒化１１り２４の部分には酸化ｊ模は形成されない。Then, on the surface of the silicon substrate 21 by oxidation,
Oxidation primary (5i (h
22 is grown to a thickness of 1,000 to 2,000 layers to form one insulating layer (+'#J figure (bOo) At this time, no oxide layer is formed on the nitride 11 and 24 portions.

また窒化膜２４と酸化１ｉＡ２２から形成される凹凸形
状は本発明の実施には何ら影■！を与えない。Moreover, the uneven shape formed by the nitride film 24 and the oxide 1iA 22 has no effect on the implementation of the present invention! not give.

次いで同図（Ｃ）に示す如く、ＣＶＤ法によりポリノリ
コン層を４０００人の厚さに成長した後レーザビームを
使用して素子形成予定領域のみをアニールする。当該ア
ニールには、出力１０１ＩＩ、スポット１条４０μφの
連続波（ＣＷ）アルゴン（Ａｒ）レーザを使用し、また
スキャン速度を５　ｃｍ／　ｓｅｃとすると最も効果が
ある。Next, as shown in FIG. 3C, after a polynolycon layer is grown to a thickness of 4,000 wafers by CVD, only the region where the element is to be formed is annealed using a laser beam. For the annealing, it is most effective to use a continuous wave (CW) argon (Ar) laser with an output of 101 II and a spot of 40 μΦ, and a scan speed of 5 cm/sec.

上記アニール後は、冷却により素子形成予定領域を単結
晶化する（同図（ｄ））。このとき、酸化［２２より窒
化膜２４の方が熱伝導率が大きいため、上記ポリシリコ
ン２３の冷却において、窒化ｊ漠２４に接する部分か最
も速く冷える（窒化１１５ｉｉ２４がヒートシンクの役
割を果す）。そのため、単結晶化が素子形成予定領域の
中心から両側の酸化膜２２の方向へ進み完全な単結晶２
３ａが形成される。なお酸化＋を臭２２上のポリシリコ
ン２３ｂば小さな単結晶の集合となる。After the above-mentioned annealing, the region where the element is to be formed is made into a single crystal by cooling (FIG. 4(d)). At this time, since the nitride film 24 has a higher thermal conductivity than the oxide film 22, when cooling the polysilicon 23, the portion in contact with the nitride film 24 cools down fastest (the nitride film 24 acts as a heat sink). Therefore, single crystallization progresses from the center of the planned element formation region toward the oxide films 22 on both sides, resulting in a complete single crystal 2.
3a is formed. It should be noted that if the polysilicon 23b on the oxidized layer 22 is oxidized, it becomes a collection of small single crystals.

同図（Ｑｌは上記単結晶化を行う素子形成予定領域の平
面図で、その幅Ｗは２５μｍ５−ＷさＬは５０μｍであ
る。本願の発明者は上述の方法により当該素予形成予定
領域を完全に単結晶化できることを確認し、更に図に示
す如く、当該領域に例えばソースＳ、ゲーｈ　Ｇ、ドレ
インＤを形成してトランジスタを構成した場合、その特
性が良好であることも確認した。なお半導体装置の製造
においては、同図ｔｄ）に示す単結晶成長の後、前に説
明した通常の技術で素子分離絶縁膜を形成した後、各素
子を形成する。In the same figure (Ql is a plan view of the element formation area where the above-mentioned single crystallization is to be performed, the width W is 25 μm5-W x L is 50 μm. It was confirmed that complete single crystallization could be achieved, and it was also confirmed that when a transistor was constructed by forming, for example, a source S, a gate hG, and a drain D in the region as shown in the figure, its characteristics were good. In manufacturing the semiconductor device, after the single crystal growth shown in td) in the figure, an element isolation insulating film is formed using the conventional technique described above, and then each element is formed.

第３図は本発明の他の実施例を説明するための図で、同
図を参照すると、窒化）模３４またはその他の絶縁膜を
酸化膜３２の厚さより薄く成長して絶縁層を形成するこ
とにより、両者の熱伝導率の差をより大きくして、窒化
膜３４またはその他の絶縁膜を介したシリコン基板３１
への熱の放散効率を向上する。FIG. 3 is a diagram for explaining another embodiment of the present invention. Referring to FIG. 3, an insulating layer is formed by growing a nitride film 34 or other insulating film thinner than the thickness of the oxide film 32. By doing so, the difference in thermal conductivity between the two is made larger, and the silicon substrate 31 is bonded to the silicon substrate 31 through the nitride film 34 or other insulating film.
improve the efficiency of heat dissipation.

以上いずれかの方法を用いても、素子形成領域に完全な
単結晶３３ａの形成が実現される。なお本発明の方法に
おいて、絶縁層を形成する熱伝導率の異なる２種類の絶
縁膜は、上記した熱放散の制御を実現できるものであれ
ば実施例のものに限るものではない。また、レーザビー
ムの照射に代えて、ポリシリコンを熔融しうるその他の
エネルギー線（ビーム）を用いても本発明の方法は実施
可能である。Even if any of the above methods is used, a complete single crystal 33a can be formed in the element formation region. In the method of the present invention, the two types of insulating films having different thermal conductivities that form the insulating layer are not limited to those in the embodiments, as long as they can realize the above-described control of heat dissipation. Further, the method of the present invention can be implemented using other energy rays (beams) capable of melting polysilicon in place of laser beam irradiation.

（７）発明の効果 以上詳細に説明した如く、本発明の方法によれば、素子
形成領域を完全単結晶化できるＳＯＩ技術を提供するこ
とができるため、半導体装置の信頼性向上および高密度
化達成に効果大である。(7) Effects of the Invention As explained in detail above, according to the method of the present invention, it is possible to provide SOI technology in which the element formation region can be completely single crystallized, thereby improving the reliability and increasing the density of semiconductor devices. It is very effective in achieving this goal.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の単結晶化方法を説明するための断面図、
第２図および第３図は本発明の単結晶化方法の実施例を
説明するための断面図である。 １．２Ｌ３１・−シリコン基板、２．３ｂ、２２．３２
−酸化膜、３．２３．３３−・−ポリシリコン層、３ａ
、　２３ａ、　３３ａ−シリコン単結晶、４．２４．３
４−・・窒化膜 第１図 （ 第２図 ９− 第２図 つ人 ｗ−Figure 1 is a cross-sectional view for explaining the conventional single crystallization method;
FIGS. 2 and 3 are cross-sectional views for explaining an embodiment of the single crystallization method of the present invention. 1.2L31・-Silicon substrate, 2.3b, 22.32
-Oxide film, 3.23.33--Polysilicon layer, 3a
, 23a, 33a - silicon single crystal, 4.24.3
4-...Nitride film Figure 1 (Figure 2 9- Figure 2 person w-

Claims (1)

【特許請求の範囲】[Claims] （１）半導体基板」二にりＬ）伝導率の異なる２種類の
絶縁膜を組み合・ヒ゛て絶縁層を形成し、当該絶縁層の
うぢ３：ｐ＞伝導率の大なる絶縁膜を素子形成予定領域
に形成し、他の領域に熱伝導率の小なる絶縁膜を設ける
工程、次いで上記絶縁層上に多結晶シリコン層を成長し
たｔｈ　ｓ＜予形成予定領域にエネルギー線を照射し、
次いで冷却して当該領域を単結晶化する工程を含むこと
を特徴とする半導体装置の製造方法。 【２）上記熱伝導率の大なる絶縁）庚の１漢厚を熱伝導
−ｆ４の小なる絶縁膜の膜厚より薄く形成することを特
徴とする特許請求の範囲第１項記載の半導体装置の製造
方法。(1) Semiconductor substrate "Second L) Two types of insulating films with different conductivities are combined to form an insulating layer, and an insulating film with a high conductivity of 3:p> A process of forming an insulating film in the area where the element is to be formed and providing an insulating film with low thermal conductivity in other areas, and then irradiating the area where a polycrystalline silicon layer is grown on the insulating layer with energy rays. ,
1. A method of manufacturing a semiconductor device, comprising the step of subsequently cooling the region to single-crystallize the region. (2) The semiconductor device according to claim 1, characterized in that the insulating film having a high thermal conductivity is formed so that the thickness of the insulating film is thinner than the film thickness of the insulating film having a low thermal conductivity of -f4. manufacturing method.
JP57228403A 1982-12-27 1982-12-27 Manufacture of semiconductor device Pending JPS59119823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57228403A JPS59119823A (en) 1982-12-27 1982-12-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57228403A JPS59119823A (en) 1982-12-27 1982-12-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59119823A true JPS59119823A (en) 1984-07-11

Family

ID=16875915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57228403A Pending JPS59119823A (en) 1982-12-27 1982-12-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59119823A (en)

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