JPS6151821A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6151821A
JPS6151821A JP17362984A JP17362984A JPS6151821A JP S6151821 A JPS6151821 A JP S6151821A JP 17362984 A JP17362984 A JP 17362984A JP 17362984 A JP17362984 A JP 17362984A JP S6151821 A JPS6151821 A JP S6151821A
Authority
JP
Japan
Prior art keywords
single crystal
silicon film
film
amorphous
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17362984A
Other languages
Japanese (ja)
Inventor
Ryoichi Mukai
良一 向井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17362984A priority Critical patent/JPS6151821A/en
Publication of JPS6151821A publication Critical patent/JPS6151821A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Abstract

PURPOSE:To provide a single crystal semiconductor layer with better quality without melting semiconductor seeds, by coating an amorphous semiconductor layer with a low melting point, on a single crystal semiconductor seeds, and by annealing the amorphous semiconductor layer by low power beams to make it single crystal. CONSTITUTION:On an SiO2 film substrate 2, 4 buried in a single crystal silicon film 3 having an island shape, an amorphous silicon layer 15 is coated with an evaporation or plasma CVD method. By scanning continuous argon laser beams, the amorphous silicon film is heated and melted to be converted to a single crystal silicon film 15. Even with the laser output reduced, the amorphous silicon film can be melted and therefore the single crystal silicon film 15 in the same crystal orientation as the single crystalline silicon film 3 being silicon seeds is formed, with the result that the single crystal silicon with extreamly good quality can be laminated in multi-level.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体装置の製造方法のうち、特にSOI構造
半導体装置における単結晶半導体層の形成方法に関する
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a single crystal semiconductor layer in an SOI structure semiconductor device.

半導体築禎回路(IC)はLSI、VLSIと二次元(
平面的)領域−で微細化、高集積化されてきたが、その
微細化にも限度があって、それを更に高集積化するため
の手段として、現在、立体的に積み上げる三次元LSI
が大きくクローズアップしている。
Semiconductor construction circuits (ICs) are LSI, VLSI, and two-dimensional (
Although miniaturization and high integration have been achieved in the (planar) area, there is a limit to this miniaturization, and three-dimensional LSIs that are stacked three-dimensionally are currently being used as a means to further increase the integration.
is shown in close-up.

このような三次元LSIの基礎となるのが、So 1 
 (Silicon On IrHsulator)構
造の半導体素子であって、それは、絶縁基板上に非単結
晶性半導体層を被着し、ビームアニールして単結晶化し
、その単結晶半導体層に素子を形成する方法によつ  
 ・て作成されている。
The basis of such three-dimensional LSI is So1
It is a semiconductor device with a (Silicon On IrHsulator) structure, and it is a method of depositing a non-single-crystalline semiconductor layer on an insulating substrate, converting it into a single crystal by beam annealing, and forming a device on the single-crystal semiconductor layer. Yotsu
・It has been created.

力、・<シて、このような半導体素子が絶縁膜を介して
多層に積み上げられて三次元LSIに形成されるが、更
に、このSOI構造の半導体素子は、従来の半導体基板
上に形成した半導体素子に比べて、更に高集積化・高性
能化される利点がある。
Although such semiconductor elements are stacked in multiple layers via insulating films to form a three-dimensional LSI, semiconductor elements with this SOI structure cannot be formed on a conventional semiconductor substrate. Compared to semiconductor devices, they have the advantage of higher integration and higher performance.

例えば、CMO3素子からなるLCを形成する場合、半
導体領域が絶縁股上にあるために、特性上からはランチ
アップの心配がなくなり、更に、チャネルストッパも不
要となって、集積度が一層向上する。
For example, when forming an LC made of CMO3 elements, since the semiconductor region is located on the insulating ridge, there is no need to worry about launch-up from a characteristic point of view, and furthermore, a channel stopper is not required, which further improves the degree of integration.

しかし1.上記のビームアニールして単結晶化する工程
は結晶品質上から特に重要で、出来るだけ品質の良い単
結晶半導体層(半導体膜)が形成されることが望ましい
But 1. The step of performing single crystallization by beam annealing is particularly important from the viewpoint of crystal quality, and it is desirable to form a single crystal semiconductor layer (semiconductor film) of as high quality as possible.

[従来の技術] さて、従来の絶縁膜上に形成する単結晶半導体膜の形成
方法を説明すると、第2図(alないしくd)にその工
程順断面図を示している。まず、同図(alに示すよう
に、シリコン基板1の上に選択的に二酸化シリコン(S
i02 ) H’A 2を形成し、その上に多結晶シリ
コン膜3を化学気相成長(CV D)法によって被着さ
せる。
[Prior Art] Now, to explain a conventional method for forming a single crystal semiconductor film on an insulating film, FIGS. 2A to 2D show cross-sectional views in the order of steps. First, as shown in the same figure (al), silicon dioxide (S
i02) H'A 2 is formed, and a polycrystalline silicon film 3 is deposited thereon by chemical vapor deposition (CVD).

次いで、第2図(blに示すように、その多結晶シリコ
ン膜3の上から連続アルゴンレーザ(CW−Ar La
5er)ビームをスキャンニング(走f)して加熱熔融
しくこれがビームアニールで、本例はレーザアニールで
ある)、多結晶シリコン膜を単結晶シリコン膜3に変成
させた後、更に、シリコン基板1と接した単結晶シリコ
ン膜部分を、選択的に酸化してS i O2膜4を生成
させる。この場合、選択酸化の酸化防止マスク(図示せ
ず)には、例えば窒化シリコン膜を用いる。
Next, as shown in FIG. 2 (bl), a continuous argon laser (CW-Ar La
5er) The polycrystalline silicon film is transformed into a single-crystalline silicon film 3 by scanning the beam (f) to heat and melt the polycrystalline silicon film (this is beam annealing (this example is laser annealing)), and then the silicon substrate 1 The portion of the single crystal silicon film in contact with is selectively oxidized to produce a SiO2 film 4. In this case, a silicon nitride film, for example, is used as an oxidation prevention mask (not shown) for selective oxidation.

そうすると、島状の単結晶シリコン膜3を埋没したS 
i O2膜基板(絶縁膜基板)2.4が形成され、次い
で、第2図(C1に示すように、その上に再び多結晶シ
リコン膜5をCVD法によって被着する。
Then, the S which buried the island-shaped single crystal silicon film 3
An i O2 film substrate (insulating film substrate) 2.4 is formed, and then, as shown in FIG. 2 (C1), a polycrystalline silicon film 5 is again deposited thereon by the CVD method.

次いで、第2図(d)に示すように、再びレーザアニー
ルして、多結晶シリコン膜を単結晶シリコンH灸5に変
成させる。
Next, as shown in FIG. 2(d), laser annealing is performed again to transform the polycrystalline silicon film into single crystal silicon H moxibustion 5.

このようにすれば、絶縁膜基板上に単結晶半導体膜を形
成することができて、この単結晶半導体膜に作成する半
導体素子は高性能化され、全体としてのICは高速化さ
れる。
In this way, a single-crystal semiconductor film can be formed on the insulating film substrate, and the semiconductor element formed on this single-crystal semiconductor film has higher performance, and the overall speed of the IC can be increased.

〔発明が解決しようとする問題点コ ところで、上記に説明した単結晶化工程のうち、単結晶
シリコン膜3を形成する初期のレーザアニール工程にお
いては、単結晶シード部分がシリコン基板1そのもので
あり、この構造では熱伝導の良いシリコン基板lから熱
が逸散し易い。従って、レーザアニールによってシリコ
ン膜を溶融している処理中に、単結晶シード部分は冷却
が速くて、シードの/8融は起こらない。そのために、
良質の単結晶シリコンMF!3を形成することできる。
[Problems to be Solved by the Invention] Incidentally, in the single crystallization process described above, in the initial laser annealing process for forming the single crystal silicon film 3, the single crystal seed portion is the silicon substrate 1 itself. In this structure, heat is easily dissipated from the silicon substrate l, which has good thermal conductivity. Therefore, during the process of melting the silicon film by laser annealing, the single-crystal seed portion is cooled quickly, and /8 melting of the seed does not occur. for that,
High quality single crystal silicon MF! 3 can be formed.

しかし、一方、単結晶シリコン膜5を形成する次のレー
ザアニール工程では、単結晶シード部分が熱伝導の悪い
5i02膜2,4で遊離された単結晶シリコン膜3であ
るから、レーザアニールによってシリコンH臭を溶融中
に、単結晶シード部分が溶融され易くて、単結晶化でき
なくなるが、あるいは品質の良くない結晶シリコン膜が
形成される可能性が高(なる。
However, on the other hand, in the next laser annealing process to form the single crystal silicon film 5, since the single crystal seed portion is the single crystal silicon film 3 liberated by the 5i02 films 2 and 4, which have poor thermal conductivity, the laser annealing While melting the H odor, the single crystal seed portion is likely to be melted, making it impossible to form a single crystal, or there is a high possibility that a poor quality crystalline silicon film will be formed.

本発明は、この第2の絶縁膜基板上に被着した非単結晶
シリコン膜のレーザアニール工程において、結晶品質の
良い単結晶シリコン膜が得られる形成方法を提案するも
のである。
The present invention proposes a method of forming a single crystal silicon film with good crystal quality in a laser annealing process for a non-single crystal silicon film deposited on the second insulating film substrate.

[問題点を解決するための手段] その問題は、単結晶半導体シードが設けられた絶縁基板
上に、アモルファス半導体層をM、着し、該アモルファ
ス半導体層をビームアニールして、前記単結晶半導体シ
ードの結晶方位に沿った単結晶半導体層を形成するよう
にした半導体装アの製造方法によって達成される。
[Means for Solving the Problem] The problem is to deposit an amorphous semiconductor layer M on an insulating substrate provided with a single crystal semiconductor seed, and beam annealing the amorphous semiconductor layer to form the single crystal semiconductor. This is achieved by a method for manufacturing a semiconductor device in which a single crystal semiconductor layer is formed along the crystal orientation of a seed.

[作用] 即ち、単結晶半導体シードの上に、この半導体シードよ
り低い融点をもったアモルファス半導体層を被着し、低
パワーのビームアニールによってアモルファス半導体層
を溶融して単結晶化する。
[Operation] That is, an amorphous semiconductor layer having a melting point lower than that of the semiconductor seed is deposited on a single crystal semiconductor seed, and the amorphous semiconductor layer is melted and made into a single crystal by low power beam annealing.

そうすると、半導体シードを熔融しないで、良質の単結
晶半導体層が得られる。
In this way, a high quality single crystal semiconductor layer can be obtained without melting the semiconductor seed.

[実施例] 以下1図面を参照して実施例によって詳細に説明する。[Example] An embodiment will be described in detail below with reference to one drawing.

7fl 1図(al、 (blは本発明にかかる形成工
程順断面図を示しており、本図は従来の第2図(C1,
(d+に示す工程断面図に対応する本発明にかかる工程
断面図である。
7fl Figure 1 (al, (bl) shows sequential cross-sectional views of the forming process according to the present invention, and this figure is similar to the conventional Figure 2 (C1,
(This is a process sectional view according to the present invention corresponding to the process sectional view shown in d+.

即ち、第2図(blで説明したように、島状の単結晶シ
リコン膜3を埋没した5i02膜基板2,4が形成され
ており、その上に、第1図(alに示すように、膜厚4
000人のアモルファスシリコン層15を蒸 。
That is, as explained in FIG. 2 (bl), the 5i02 film substrates 2 and 4 in which the island-shaped single crystal silicon film 3 is buried are formed, and as shown in FIG. Film thickness 4
Vaporize an amorphous silicon layer of 15,000 people.

着法またはプラズマCVD法によって被着する。It is deposited by a deposition method or a plasma CVD method.

この場合、単結晶シリコンl18%i3の島状領域は、
例えば面積10.czm角、膜厚4000人の大きさで
、この島状領域がメツシュ状(市松模様状)に形成され
ているものである。
In this case, the island-like region of single crystal silicon l18%i3 is
For example, area 10. This island-like area is formed in a mesh shape (checkerboard pattern) with a size of czm square and a film thickness of 4,000 people.

次いで、第1図(blに示すように、連続アルゴンレー
ザビームを走査し、加熱熔融してアモルファスシリコン
膜を単結晶シリコンll5ti15に変成する。
Next, as shown in FIG. 1 (bl), a continuous argon laser beam is scanned to heat and melt the amorphous silicon film to transform it into single crystal silicon 115ti15.

その際、アニール条件は絶縁膜基板を約450℃に加熱
し、レーザ出力を6W、ビームスポット径を30〜50
μmφ、走査速度をlQcm / secにする。
At that time, the annealing conditions were to heat the insulating film substrate to about 450℃, laser output to 6W, and beam spot diameter to 30 to 50℃.
μmφ, and the scanning speed is set to lQcm/sec.

かように、レーザ出力を6Wと低くしても、アモルファ
スシリコン膜は溶融し、シリコンシードの単結晶シリコ
ン膜3の結晶方位に沿った単結晶シリコン膜15が形成
される。それは単結晶シリコンの融点が1400℃であ
るのに対して、アモルファスシリコンの融点が950°
Cと低いためである。
In this way, even if the laser output is reduced to 6 W, the amorphous silicon film is melted and a single crystal silicon film 15 is formed along the crystal orientation of the single crystal silicon film 3 as a silicon seed. The melting point of single crystal silicon is 1400°C, while the melting point of amorphous silicon is 950°C.
This is because it is low.

一方、多結晶シリコン膜を単結晶化する初期のレーザア
ニール工程では、他のアニール条件を同しにして、レー
ザ出力をIOW又はそれ以上の高い出力によって走査し
、多結晶シリコン膜を熔融させている。
On the other hand, in the initial laser annealing process for converting a polycrystalline silicon film into a single crystal, the laser output is scanned at IOW or higher output to melt the polycrystalline silicon film, with other annealing conditions being the same. There is.

そのため、レーザ出力が6Wの場合には、単結晶シリコ
ンシードが溶融することはなく、アモルファスシリコン
のみ低エネルギーで溶融されて、シリコンシードに沿っ
た単結晶シリコン膜15が形成される。
Therefore, when the laser output is 6 W, the single crystal silicon seed is not melted, and only the amorphous silicon is melted with low energy, forming the single crystal silicon film 15 along the silicon seed.

このようにすれば、立体的に限りなく良質の単結晶シリ
コンを積層することができる。
In this way, monocrystalline silicon of infinitely high quality can be stacked three-dimensionally.

[発明の効果] 以上の実施例の説明から明らかなように、本発明によれ
ば三次元LSIの製造方法において、結晶品質の良い単
結晶シリコン層が容易に積層され、三次元LSIの高性
能化・高品質化に大きく貢献するものである。
[Effects of the Invention] As is clear from the above description of the embodiments, according to the present invention, in the method for manufacturing a three-dimensional LSI, single-crystal silicon layers with good crystal quality can be easily stacked, and the high performance of the three-dimensional LSI can be improved. This greatly contributes to improved quality and improved quality.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(al、 (b1本発明にかかる形成方法を説明
するための工程順断面図、 第2図(al〜(d+は従来の一実施例の形成方法を説
明するための工程断面図である。 図において、 1はシリコン基板、 2.4はSiO2膜、 3.5は多結晶シリコン膜または単結晶シリコン膜、 15はアモルファスシリコン膜または単結晶シリコン膜 を示している。 第1σ 第2図
Figure 1 (al, (b1) is a step-by-step sectional view for explaining the forming method according to the present invention, Figure 2 (al~(d+ is a process sectional view for explaining the forming method of one conventional example) In the figure, 1 is a silicon substrate, 2.4 is a SiO2 film, 3.5 is a polycrystalline silicon film or a single crystal silicon film, and 15 is an amorphous silicon film or a single crystal silicon film. 1st σ 2nd figure

Claims (1)

【特許請求の範囲】[Claims] 単結晶半導体シードが設けられた絶縁基板上に、アモル
ファス半導体層を被着し、該アモルファス半導体層をビ
ームアニールして、前記単結晶半導体シードの結晶方位
に沿った単結晶半導体層を形成するようにしたことを特
徴とする半導体装置の製造方法。
An amorphous semiconductor layer is deposited on an insulating substrate provided with a single crystal semiconductor seed, and the amorphous semiconductor layer is beam annealed to form a single crystal semiconductor layer along the crystal orientation of the single crystal semiconductor seed. A method for manufacturing a semiconductor device, characterized in that:
JP17362984A 1984-08-20 1984-08-20 Manufacture of semiconductor device Pending JPS6151821A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17362984A JPS6151821A (en) 1984-08-20 1984-08-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17362984A JPS6151821A (en) 1984-08-20 1984-08-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6151821A true JPS6151821A (en) 1986-03-14

Family

ID=15964152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17362984A Pending JPS6151821A (en) 1984-08-20 1984-08-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6151821A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01276615A (en) * 1988-04-27 1989-11-07 Seiko Epson Corp Manufacture of semiconductor device
JP2013505578A (en) * 2009-09-16 2013-02-14 アプライド マテリアルズ インコーポレイテッド A method for solid-phase recrystallization of thin films using pulse train annealing.

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5893220A (en) * 1981-11-30 1983-06-02 Toshiba Corp Preparation of semiconductor single crystal film

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5893220A (en) * 1981-11-30 1983-06-02 Toshiba Corp Preparation of semiconductor single crystal film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01276615A (en) * 1988-04-27 1989-11-07 Seiko Epson Corp Manufacture of semiconductor device
JP2013505578A (en) * 2009-09-16 2013-02-14 アプライド マテリアルズ インコーポレイテッド A method for solid-phase recrystallization of thin films using pulse train annealing.

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