JPS59114857A - Semiconductor integrated circuit device wherein capacitor is formed - Google Patents

Abstract

PURPOSE:To obtain the remarkable facility of inspection by a method wherein a linear pattern made fine and folded back is adopted for a wiring layer, and both ends thereof are handled as an input terminal part and an output terminal part. CONSTITUTION:With a substrate or a diffused layer as an opposition electrode, the wiring layer pattern 7 of a capacitor part by the wiring layer pattern is formed. The output of a front stage circuit is connected to the input terminal part 8, the output terminal part 9 is connected to the input of the next stage circuit, and, when manufactured without any abnormality, a signal coming from the input terminal part 8 is transmitted to the output terminal part 9 and at the same time functions as the capacitor part. If defects generate in the wiring layer pattern by manufacturing failure, the capacitance reduces, and at the same time the part between the input terminal part 8 and the output terminal part 9 is cut. Since the signal from the front stage circuit is not transmitted to the next stage circuit, the signal can be easily detected by normal functional inspection performed after manufacture.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to a semiconductor integrated circuit device in which a capacitor is formed.
In particular, the present invention relates to a semiconductor integrated circuit device in which a capacitor is formed between a wiring layer and a substrate or between a wiring layer and a diffusion layer.

(2) Description of the prior art Conventionally, when forming a capacitive part using a wiring layer in a horizontal conductor integrated circuit, an area of 800 mm is prepared for the wiring pattern, and a substrate or a diffusion layer is used as a counter electrode. Ta. FIG. 1 shows a conventional wiring layer pattern of a capacitive part formed between a wiring layer and a substrate or between a wiring layer and a diffusion layer. 1 is a wiring layer pattern, 2 is an input terminal section, and 3 is an output terminal section. The output of the previous stage circuit is connected to the input terminal section 2, and the output terminal section 3 is connected to the input of the next stage circuit.

FIG. 2 shows a case where the wiring layer pattern shown in FIG. 1 is damaged due to a manufacturing defect. 4 is a wiring layer pattern, 5 is an input terminal section, and 6 is an output terminal section. When such a manufacturing defect occurs, if the capacitance decreases by a large amount due to a defect in the wiring layer pattern, it will be judged as a defect in the function test as a semiconductor integrated circuit, but the capacitance decrease is not large enough to reach the limit of functionality. If it is close to the point, it will not be considered defective in the functional test, but it will be determined by subsequent changes over time and changes in operating environment conditions.
A semiconductor integrated circuit becomes malfunctioning.

In order to detect defects caused by such economic changes and changes in operating environment conditions through post-manufacturing functional tests, there is a drawback that functional tests, accelerated tests, aging, etc. under various operating environment conditions are required. .

(3) Object of the Invention An object of the present invention is to provide a semiconductor integrated circuit device having a capacitive portion formed between a wiring layer and a substrate or between a wiring layer and a diffusion layer, which improves the above-mentioned drawbacks.

(4) Structure of the Invention The present invention employs a single linear pattern that has a capacitive part formed between the wiring layer and the substrate or between the wiring layer and the diffusion layer, and is made fine and folded in the wiring layer. If a defect occurs in the wiring layer pattern due to a manufacturing defect by treating the terminal as an input terminal section and an output terminal section, not only the capacitance will decrease, but also the connection between the input terminal section and the output terminal section will be severed. This is a semiconductor integrated circuit that allows easy inspection.

(5) Examples Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 shows a wiring layer pattern of a capacitor section with a wiring layer pattern having a substrate or a diffusion layer as a counter electrode. 7 is a wiring layer pattern, 8 is its input terminal portion, and 9 is its output terminal portion. The output of the previous stage circuit is connected to the input terminal section 8, and the output terminal section 9 is connected to the input of the next stage circuit.If the product is manufactured without any defects, the signal input from the input terminal section 8 will be transmitted to the output terminal section 9. At the same time, it functions as a capacitor. When a defect occurs in the wiring layer pattern due to a manufacturing defect, the capacitance decreases and at the same time the input terminal section 8 and the output terminal section 90 are disconnected. As a result, the signal from the previous stage circuit is not transmitted to the next stage circuit, so it can be easily detected in a normal functional test performed after manufacturing. As described above, the present invention can greatly contribute to the testing of semiconductor integrated circuits.

(6) Effects of the Invention As explained above, in the present invention, in a semiconductor integrated circuit having a capacitive part formed between a wiring layer and a substrate or between a wiring layer and a diffusion layer, the wiring layer can be miniaturized.

By adopting a single folded linear pattern and treating both ends of the pattern as an input terminal section and an output terminal section, the drawbacks of conventional semiconductor integrated circuits using capacitance sections are eliminated and inspection becomes significantly easier. effective.

[Brief explanation of the drawing]

Figure 1 shows a conventional wiring layer pattern of a capacitive part formed between a wiring layer and a substrate or between a wiring layer and a diffusion layer, and Figure 2 shows a pattern in which defects due to manufacturing defects are added to the wiring layer pattern of Figure 1. FIG. 3 shows a wiring layer pattern of a capacitive part formed between a wiring layer and a substrate or between a wiring layer and a diffusion layer according to an embodiment of the present invention. In Figure 2, 1, 4, 7... wiring layer patterns. 2.5.8...Input terminal part of wiring layer pattern,
3°6.9...This is the output terminal portion of the wiring layer pattern. Foil/Illustration? figure

Claims (1)

[Claims] In a semiconductor integrated circuit device in which a capacitor is formed inside,
A semiconductor integrated circuit device in which a capacitor is formed, characterized in that at least 10,000 of the pair of opposing electrodes forming the capacitor have a planar shape of continuous thin lines that are alternately folded back and arranged. .